CMO V470H1-LH2 Specification

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TFT LCD Approval Specification

MODEL NO.: V470H1 – LH2

Customer: Nexgen

Approved by:

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

Note:

Approved By

Reviewed By

TV Head Division

LY Chen

QA Dept. Product Development Div.

Hsin-nan Chen

WT Lin

LCD TV Marketing and Product Management Div

Prepared By

CY Chang TC Chao

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CONTENTS

1. GENERAL DESCRIPTION

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 PACKAGE STORAGE

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

2.3.2 BACKLIGHT INVERTER UNIT

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

3.2.1 CCFL

3.2.2 INVERTER CHARACTERISTICS

3.2.3 INVERTER INTERTFACE CHARACTERISTICS

(Cold Cathode Fluorescent Lamp) CHARACTERISTICS

------------------------------------------------------- 4

------------------------------------------------------- 5

--------------------------------------------------------7

4. BLOCK DIAGRAM -------------------------------------------------------13

4.1 TFT LCD MODULE

5. INPUT TERMINAL PIN ASSIGNMENT --------------------------------------------------------14

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT

5.3 INVERTER UNIT

5.4 BLOCK DIAGRAM OF INTERFACE

5.5 LVDS INTERFACE

5.6 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

6.2 POWER ON/OFF SEQUENCE

-------------------------------------------------------22

7. OPTICAL CHARACTERISTICS -------------------------------------------------------26

7.1 TEST CONDITIONS

7.2 OPTICAL SPECIFICATIONS

8. PRECAUTIONS -------------------------------------------------------30

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

8.2 SAFETY PRECAUTIONS

9.DEFINITION OF LABELS ------------------------------------------------------31

9.1 CMO MODULE LABEL

10. PACKAGING ----------------------------------------------32

10.1 PACKING SPECIFICATIONS

10.2 PACKING METHOD

11 MECHANICAL CHARACTERISTICS -----------------------------------------------34

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REVISION HISTORY

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

Version Date

Ver.2.0

Ver.2.1

Dec,01,08’

Jul,06,09’

Page

(New)

All

P. 2 6

P1

P11

P4

Section Description

All

7.2

cover

3.2.3

1.4

Approval specification was first issued

OPTICAL SPECIFICATIONS

Modify the owner of QA Dept. and LCD TV Marketing and Product

Management Div.

Modify the range of Internal PWM Control Voltage

Modify the Pixel Pitch

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V470H1-LH2 is a 47” TFT Liquid Crystal Display module with 20-CCFL Backlight unit and 4ch-LVDS

interface. This module supports 1920 x 1080 Full HDTV format and can display true 1.0G colors

(10-bit/color). The inverter module for backlight is built-in.

1.2 FEATURES

- High brightness (450 nits)

- High contrast ratio (2000:1)

- Fast response time (Gray to Gray average 4 ms)

- High color saturation (NTSC 88%)

- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format

- DE (Data Enable) only mode

- LVDS (Low Voltage Differential Signaling) interface

- Optimized response time for 120 Hz frame rate

- Ultra wide viewing angle : Super MVA technology

- 180 degree rotation display option

1.3 APPLICATION

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

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- Standard Living Room TVs.

- Public Display Application.

- Home Theater Application.

- MFM Application.

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note Active Area 1039.68(H) x 584.82(V) (47” diagonal) mm Bezel Opening Area 1049(H) x 593(V) mm Driver Element a-si TFT active matrix - Pixel Number 1920x R.G.B. x 1080 pixel Pixel Pitch(Sub Pixel) 0.5415 (V) x 0.1805(H) mm Pixel Arrangement RGB vertical stripe - Display Colors 1.0G color Display Operation Mode Transmissive mode / Normally black - -

Surface Treatment

Note (1) Please refer to the attached drawings in chapter 11 for more information about the front and

back outlines.

Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to

change this feature.

Anti-Glare coating (Haze 25%)

Hard coating (3H)

- (2)

(1)

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note Horizontal (H) - 1096 - mm

Module Size

Depth (D) - 52.7 - mm

Weight - 15500 - g -

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Note (2) Module Depth does not include connectors.

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 50 ºC (1)(2)

Shock (Non-Operating) S

Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta Љ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

NOP

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Model No.: V470H1-LH2

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Value

Min. Max.

X, Y axis - 50 G (3)(5)

Z axis - 35 G (3)(5)

- 1.0 G (4)(5)

NOP

Unit Note

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

Thermal management should be considered in your product design to prevent the surface temperature

of display area from being over 65 ºC. The range of operating temperature may degrade in case of

improper thermal management in your product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, and ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that

the module would not be twisted or bent by the fixture.

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2.2 PACKAGE STORAGE

When storing modules as spares for a long time, the following precaution is necessary.

(a) Do not leave the module in high temperature, and high humidity for a long time. It is highly recommended to

store the module with temperature from 0 to 35кat normal humidity without condensation.

(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent

light.

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

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Item Symbol

Min. Max.

Power Supply Voltage VCC -0.3 13.2 V

Logic Input Voltage VIN -0.3 3.6 V

Value

Unit Note

2.3.2 BACKLIGHT INVERTER UNIT

Item Symbol

Lamp Voltage V Power Supply Voltage VBL 0 30 V (1) Control Signal Level

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

Note (2) No moisture condensation or freezing.

Note (3) The control signals include On/Off Control, Internal PWM Control, External PWM Control and

Internal/External PWM Selection.

W

Ё

Value

Min. Max.

Ё

-0.3 7 V (1), (3)

3000 V

Unit Note

RMS

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)

Parameter Symbol

Power Supply Voltage VCC 10.8 12 13.2 V (1) Power Supply Ripple Voltage VRP - - 350 mV Rush Current I

White

Power Supply Current

Vertical Stripe - 2.0 - A LVDS Interface CMOS interface

Note (1) The module should be always operated within the above ranges.

Note (2) Measurement condition:

Common Input Voltage V Terminating Resistor RT - 100 - ohm Input High Threshold Voltage V Input Low Threshold Voltage VIL 0 - 0.7 V

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Value

Min. Typ. Max.

- - 7.0 A (2)

RUSH

- 2.5 3.0 A

I

CC

1.125 1.25 1.375 V

LVC

2.7 - 3.3 V

IH

Unit Note

Apporval

(3) Black - 1.5 - A

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GND

Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,

whereas a power dissipation check pattern below is displayed.

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

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Vcc rising time is 470us

Vcc

0.9Vcc

0.1Vcc

470us

a. White Pattern

Active Area

c. Vertical Stripe Pattern

b. Black Pattern

Active Area

G

B

R

B

G

B

R

B

G

B

R R

G

B

R

G

B

R

Active Area

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3.2 BACKLIGHT UNIT

3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)

Parameter Symbol

Lamp Input Voltage VL - 1400 - V Lamp Current IL 7.5 8.0 8.5 mA

Lamp Turn On Voltage V

Operating Frequency FL 40 - 80 KHz (3) Lamp Life Time LBL 50,000 - - Hrs (4)

S

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Value

Min. Typ. Max.

- - 2050 V

- - 1890 V

Unit Note

RMS

Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

(1)

RMS

(2), Ta = 0 ºC (2), Ta = 25 ºC

3.2.2 INVERTER CHARACTERISTICS (

Parameter Symbol

Ta = 25 ± 2 ºC)

Value

Min. Typ. Max.

Unit Note

Power Consumption PBL - 197 206 W (3)(4), IL = 8.0mA

Power Supply Voltage VBL 22.8 24 25.2 V

DC

Power Supply Current IBL - 8.2 8.6 A Input Ripple Noise - - - 912 mV

P-P

VBL=22.8V Oscillating Frequency FW 37 40 43 kHz Dimming frequency FB 150 160 170 Hz Minimum Duty Ratio D

- 20 - %

MIN

Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring

master and slave board.

Note (2) The lamp starting voltage V

should be applied to the lamp for more than 1 second after startup.

S

Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the

display input signals, and it may result in line flow on the display. In order to avoid interference, the

lamp frequency should be detached from the horizontal synchronous frequency and its harmonics

as far as possible.

Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and

the effective discharge length is longer than 80% of its original length (Effective discharge length is

defined as an area that has equal to or more than 70% brightness compared to the brightness at

the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25

2к and I

= 7.5~ 8.5mArms.

L

Note (5) The measurement condition of Max. value is based on 47" backlight unit under input voltage 24V,

average lamp current 8.3 mA and lighting 30 minutes later.

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1

A

2

A

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

HV (White -) HV(Pink -)

A A

Inverter LCD Module

A A

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV (White -)

1

HV(Pink -)

2

HV (White +)

1

HV(Pink +)

2

HV(Blue -)

1

HV (Pink -)

2

A A

HV (Pink +)

2

HV(Blue +)

1

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3.2.3 INVERTER INTERTFACE CHARACTERISTICS

Parameter Symbol

On/Off Control Voltage

Status Signal

Internal PWM Control

Voltage

External PWM Control

Voltage

ON

OFF

HI

LO

MAX

MIN

HI

LO 0

V

BLON

States

V

IPWM

V

EPWM

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Te st

Condition

Ё Ё

Ё

Min. Typ. Max.

2.0

3.0 3.3 3.6 V Normal

3.15

2.0

Value

0

0 0.8 V Abnormal

Ё

Ё Ё

Ё

Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

Unit Note

5.0 V

0.8 V

5

0

Ё

5.0 V duty on

0.8 V duty off

V maximum duty ratio V minimum duty ratio

VBL Rising Time Tr1 Ё 30 ЁЁ ms

10%-90%V

VBL Falling Time Tf1 Ё 30 ЁЁms

Control Signal Rising Time Tr

Control Signal Falling Time Tf

PWM Signal Rising Time T

PWM Signal Falling Time T

PWMR

PWMF

Input impedance R

PWM Delay Time T

BLON Delay Time T

BLON Off Time T

PWM

on1

OFF

IN

ЁЁЁ

Ё

1

ЁЁ MӨ

100 ms

50 us 50 us

Ё 100 Ё ms

Ё 300 ЁЁms Ё 300 ЁЁ ms

Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to

change the internal/external PWM signal during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure. For a certain

reason, the inverter has a possibility to be damaged with wrong power sequence and control

signal timing.

Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:

Turn ON sequence: VBL

Turn OFF sequence: BLOFF

Ш PWM signal Ш BLON

Ш PWM signal Ш VBL

BL

Note (4) In order to avoid the abnormal phenomenon at dimming condition, skipped range of VIPWM

2.85~3.15V is suggested.

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Model No.: V470H1-LH2

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V

VBLON

V

EPWM

V

IPWM

9%/

Toff

Tf1

9

%/

Tr1

BL

0

9

0

%/

2.0V

0.8V

9

Ton

%/

Ton1

Backlight on duration

Tr

Tf

Ext. Dimming Function

TPWMR

PWMF

2.0V

0

0.8V

T

PWM

T

Floating

3.0V

0

Floating

Int. Dimming Function

V

W

External

PWM

Period

External

PWM Duty

100%

Minimun

Duty

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(

)

(+/

)

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4. BLOCK DIAGRAM OF INTERFACE

4.1 TFT LCD MODULE

4RX0(+/-) 4RX1(+/-) 4RX2(+/-) 4RX3(+/-) 4RX4(+/-) 4CLK(+/-)

3RX0(+/-) 3RX1(+/-) 3RX2(+/-) 3RX3(+/-) 3RX4(+/-) 3CLK

2RX0(+/-) 2RX1(+/-) 2RX2(+/-) 2RX3(+/-) 2RX4(+/-) 2CLK(+/-)

1RX0(+/-) 1RX1(+/-) 1RX2(+/-) 1RX3(+/-) 1RX4(+/-) 1CLK(+/-) SELLVDS VCC GND

INPUT CONNECTOR

FI-RE41S-HF (JAE)

CNF2

-

INPUT CONNECTOR

FI-RE51S-HF (JAE)

CNF1

FRAME BUFFER

CONTROLLER

FRAME BUFFER

CONTROLLER

CONVERTER

& REFERENCE

GENERATOR

TIMING

(SLAVE)

TIMING

(MASTER)

DC/DC

VOLTAGE

SCAN DRIVER

TFT LCD PANEL

(1920x3x1080)

DATA DRIVER

RSDS

CN1.

VB

GND

Status

E_PWM

I_PWM

BLON

INVERTER

CONNECTOR

CN1:S14B-PH-SM4-TB(

D)(LF) or equivalent

CN2:S12B-PH-SM4-TB(

D)(LF) or equivalent

CN3-CN22:SM02 (12.0)B-BHS-1-TB(LF)(JST)

or equivalent

BACKLIGHT

UNIT

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD Module

CNF1 Connector Pin Assignment( FI-RE51S-HF (JAE) or equivalent )

Pin Name Description Note

1 GND Ground 2 N.C. 3 N.C.

N.C. No Connection (1)

4

N.C. No Connection (1)

5

N.C. No Connection (1)

6 7 SELLVDS LVDS data format Selection (2)

N.C. No Connection (1)

8 9 N.C. No Connection (1)

10 N.C. No Connection

11 GND Ground

12

RxAo-

13

RxAo+

14

RxBo-

15

RxBo+

16

RxCo-

17

RxCo+

18

GND

19

RxClko-

20

RxClko+

21

GND

22

RxDo-

23

RxDo+

24

RxEo-

25

RxEo+

26

NC

27

NC

28

RxAe-

29

RxAe+

30

RxBe-

31

RxBe+

32

RxCe-

33

RxCe+

34

GND

35

RxClke-

36

RxClke+

37

GND

38

RxDe-

39

RxDe+

40

RxEe-

41

RxEe+

42

GND

43

GND

44

GND

45

GND

46

GND

47

NC

48

Vin

49

Vin

No Connection (1) No Connection (1)

First pixel, Negative LVDS differential data input. Channel 0 First pixel, Positive LVDS differential data input. Channel 0 First pixel, Negative LVDS differential data input. Channel 1 First pixel, Positive LVDS differential data input. Channel 1 First pixel, Negative LVDS differential data input. Channel 2 First pixel, Positive LVDS differential data input. Channel 2 Ground First pixel, Negative LVDS differential clock input. First pixel, Positive LVDS differential clock input. Ground First pixel, Negative LVDS differential data input. Channel 3 First pixel, Positive LVDS differential data input. Channel 3 First pixel, Negative LVDS differential data input. Channel 4 First pixel, Positive LVDS differential data input. Channel 4 No Connection (1) No Connection (1) Second pixel, Negative LVDS differential data input. Channel 0 Second pixel, Positive LVDS differential data input. Channel 0 Second pixel, Negative LVDS differential data input. Channel 1 Second pixel, Positive LVDS differential data input. Channel 1 Second pixel, Negative LVDS differential data input. Channel 2 Second pixel, Positive LVDS differential data input. Channel 2 Ground Second pixel, Negative LVDS differential clock input. Second pixel, Positive LVDS differential clock input. Ground Second pixel, Negative LVDS differential data input. Channel 3 Second pixel, Positive LVDS differential data input. Channel 3

Second pixel, Negative LVDS differential data input. Channel 4 Second pixel, Positive LVDS differential data input. Channel 4

Ground Ground Ground Ground Ground No Connection Power input (+12V) Power input (+12V)

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50 51

Vin Vin

Power input (+12V) Power input (+12V)

CNF2 Connector Pin Assignment ( FI-RE41S-HF (JAE) or equivalent )

Pin Name Description Note

1 GND Ground 2 N.C. 3 N.C.

N.C. No Connection

4

N.C. No Connection

5

N.C. No Connection

6 7 NC No Connection (1)

N.C. No Connection

8 9 GND Ground

10

RxAo-

11

RxAo+

12

RxBo-

13

RxBo+

14

RxCo-

15

RxCo+

16

GND

17

RxClko-

18

RxClko+

19

GND

20

RxDo-

21

RxDo+

22

RxEo-

23

RxEo+

24

NC

25

NC

26

RxAe-

27

RxAe+

28

RxBe-

29

RxBe+

30

RxCe-

31

RxCe+

32

GND

33

RxClke-

34

RxClke+

35

GND

36

RxDe-

37

RxDe+

38

RxEe-

39

RxEe+ N.C. No Connection (1)

40 41 N.C. No Connection (1)

No Connection No Connection

Third pixel, Negative LVDS differential data input. Channel 0 Third pixel, Positive LVDS differential data input. Channel 0 Third pixel, Negative LVDS differential data input. Channel 1 Third pixel, Positive LVDS differential data input. Channel 1 Third pixel, Negative LVDS differential data input. Channel 2 Third pixel, Positive LVDS differential data input. Channel 2 Ground Third pixel, Negative LVDS differential clock input. Third pixel, Positive LVDS differential clock input. Ground Third pixel, Negative LVDS differential data input. Channel 3 Third pixel, Positive LVDS differential data input. Channel 3 Third pixel, Negative LVDS differential data input. Channel 4 Third pixel, Positive LVDS differential data input. Channel 4 No Connection (1) No Connection (1) Fourth pixel, Negative LVDS differential data input. Channel 0 Fourth pixel, Positive LVDS differential data input. Channel 0 Fourth pixel, Negative LVDS differential data input. Channel 1 Fourth pixel, Positive LVDS differential data input. Channel 1 Fourth pixel, Negative LVDS differential data input. Channel 2 Fourth pixel, Positive LVDS differential data input. Channel 2 Ground Fourth pixel, Negative LVDS differential clock input. Fourth pixel, Positive LVDS differential clock input. Ground Fourth pixel, Negative LVDS differential data input. Channel 3 Fourth pixel, Positive LVDS differential data input. Channel 3 Fourth pixel, Negative LVDS differential data input. Channel 4 Fourth pixel, Positive LVDS differential data input. Channel 4

(1) (1) (1) (1) (1)

(1)

(3)

Note (1) Please be reserved to open.

Note (2) Low or Open : VESA LVDS Format (default), High : JEIDA Format.

Note (3) LVDS 4-Port Data Mapping

Port CH of LVDS Data Stream

1st Port First pixel 1, 5, 9, ..........., 1913, 1917

2nd Port Second pixel 2, 6, 10, ........., 1914, 1918

3rd Port Third pixel 3, 7, 11, ........., 1915, 1919

4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920

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5.2 BACKLIGHT UNIT

The pin configuration for the housing and the leader wire is shown in the table below.

CN3-CN22: BHR-04VS-1 (JST). or equivalent

Pin Name Description Wire Color

1 HV High Voltage Pink 2 HV High Voltage White

Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1,

manufactured by JST. The mating header on inverter part number is

SM02 (12.0)B-BHS-1-TB(LF). or equivalent

1 HV(White)

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2 HV(Pink)

1 HV(White)

2 HV(Pink)

1 HV(White)

2 HV(Pink)

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5.3 INVERTER UNIT

CN1 (Header): S14B-PH-SM3-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10

VBL +24V

GND GND

power input

DC

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Model No.: V470H1-LH2

Apporval

11

12 E_PWM External PWM control signal

13 I_PWM Internal PWM Control Signal

14 BLON Backlight on/off control

Status

Normal (3.3V) Abnormal (GND)

Notice:

1. PIN 12:External PWM Control (Use Pin 12): Pin 13 must open.

2. PIN 13:Intermal PWM Control (Use Pin 13): Pin 12 must open.

3. Pin 12(E_PWM) and Pin 13(I_PWM) can’t open in same period.

CN2 (Header): S12B-PH-SM3-TB (D)(LF)(JST) or equivalent.

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10 11 NC NC 12 NC NC

VBL +24V

GND GND

power input

DC

CN3-CN22 (Header): SM02(12.0)B-BHS-1-TB (LF)(JST) or equivalent

Pin No. Symbol Description

1 2

CCFL HOT CCFL HOT

CCFL high voltage CCFL high voltage

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5.4 BLOCK DIAGRAM OF INTERFACE

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Model No.: V470H1-LH2

Apporval

RXAe+

RXAe-

RXBe+

RXBe-

RXCe+

RXCe-

RXDe+

RXDe-

RXEe+

RXEe-

RXCLKe+

RXCLKe-

51Ө

100pF

PLL

Rx-OUT

ER0-ER9

EG0-EG9

EB0-EB9

DE

OR0-OR9

OG0-OG9

OB0-OB9

DCLK

Timing Controller

RXAe+

RXAe-

RXBe+

RXBe-

RXCe+

RXCe-

RXDe+

RXDe-

RXEe+

RXEe-

RXCLKe+

RXCLKe-

LVDS Input

51Ө

100pF

51Ө

100pF

51Ө

100pF

51Ө

100pF

51Ө

100pF

51Ө

100pF

51Ө

LVDS Receiver

PLL

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ER0~ER9 : Even pixel R data

EG0~EG9 : Even pixel G data

EB0~EB9 : Even pixel B data

OR0~OR9 : Odd pixel R data

OG0~OG9: Odd pixel G data

OB0~OB9 : Odd pixel B data

DE : Data enable signal

DCLK : Data clock signal

Notes: (1) The system must have the transmitter to drive the module.

(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per

twist-pair line when it is used differentially.

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5.5 LVDS INTERFACE

SELLVDS = L or Open

RXCLK

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

RXAo

RXBo

RXCo

RXDo

RXEo

RXAe

RXBe

RXCe

RXDe

RXEe

LVDS_ SEL = H

OR5OG0 OR4 OR3 OR2 OR1

OB0 OG5OB1

ER5EG0 ER4 ER3 ER2 ER1

EB0 EG5EB1

OG3 OG2OG4

EG3 EG2EG4

OR0

OG1

OB2OB4 OB3OB5VS HSDE

OR6OG6 OR7OG7OB7 OB6RSVD

OR8OG8 OR9OG9OB9 OB8RSVD

ER0

EG1

EB2EB4 EB3EB5VS HSDE

ER6EG6 ER7EG7EB7 EB6RSVD

ER8EG8 ER9EG9EB9 EB8RSVD

RXCLK

RXAo

RXBo

RXCo

RXDo

RXEo

RXAe

RXBe

RXCe

RXDe

RXEe

OR9OG4 OR8 OR7 OR6 OR5

OB4 OG9OB5

ER9EG4 ER8ER7ER6ER5

EB4 EG9EB5

OG7 OG6OG8

EG7 EG6EG8

20

OR4

OG5

OB6OB8 OB7OB9VS HSDE

OR2OG2 OR3OG3OB3 OB2RSVD

OR0OG0 OR1OG1OB1 OB0RSVD

ER4

EG5

EB6EB8 EB7EB9VS HSDE

ER2EG2 ER3EG3EB3 EB2RSVD

ER0EG0 ER1EG1EB1 EB0RSVD

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B0~B9: Pixel B Data (9; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

RSVD

: Reserved.

5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for

the color. The higher the binary input, the brighter the color. The table below provides the assignment of the

color versus data input.

0 0 1 0 1 0 1 1

0 0 0

:

: 0 0 0

0 0 0

:

: 1 1 1

0 0 0

:

: 0 0 0

Data Signal

0

1

0

1

0

1

0

:

0

:

1

0

:

0

1

0

0 1 0 1 1

0 0 0

:

: 0 0 0

0 0 0

:

: 1 1 1

0 0 0

:

: 0 0 0

0

1

0

1

0

:

0

0 0

0

:

1

0

:

0

1

0

1

0

1

0

:

;

0

1

0

1

0

:

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

1

0

1

0

:

0

:

0

:

1

0

1

0

1

0

:

0

:

0

:

1

Basic Colors

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Color

Black Red Green Blue Cyan Magenta Yellow White

Red (0) / Dark Red (1) Red (2)

:

: Red (1021) Red (1022) Red (1023)

Green (0) / Dark Green (1) Green (2)

:

: Green (1021) Green (1022) Green (1023)

Blue (0) / Dark Blue (1) Blue (2)

:

: Blue (1021) Blue (1022) Blue (1023)

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0

1

0

1

0

1

0

:

0

:

0

Red Green Blue

0

1

0

1

0

:

1

0

:

0

:

0

1

0

1

0

:

1

0

:

0

:

0

1

0

1

0

1

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

:

0

1

0

1

0

:

0

:

0

1

0

1

0

:

1

0

1

0

1

Note (1) 0: Low Level Voltage, 1: High Level Voltage

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

LVDS Receiver Clock

LVDS Receiver Data

Vertical Active Display Term

Horizontal Active Display Term

Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low

Frequency Input cycle to cycle jitter Trcl - - 200 ps Setup Time Tlvsu 600 - - ps Hold Time Tlvhd 600 - - ps Frame Rate Fr Total Tv 1115 1125 1139 Th Tv=Tvd+Tvb Display Tvd 1080 1080 1080 Th Blank Tvb 35 45 59 Th Total Th 540 550 575 Tc Th=Thd+Thb Display Thd 480 480 480 Tc Blank Thb 45 70 95 Tc -

1/Tc 60 74.25 80 MH

- 120 - Hz (1)

Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

Z

=297/4

logic level. Otherwise, this module would operate abnormally..

INPUT SIGNAL TIMING DIAGRAM

Tv

Tvd

DE

Th

DCLK

Tc

Thb

DE

Tvb

Thd

DATA

Valid display data ( 480 clocks)

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RXCLK+/-

RXn+/-

Tlvsu

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LVDS INPUT INTERFACE TIMING DIAGRAM

Tc

Tlvhd

1T‘ 14

3T‘ 14

5T‘ 14

7T‘ 14

9T‘ 14

11T‘

14

13T‘

14

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6.2 POWER ON/OFF SEQUENCE

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Issue Date:Jul.06.2009

Model No.: V470H1-LH2

Apporval

Power Supply

2

3

50ms

T

CC

0V

4

V

0.5ЉT1Љ10ms

0

T

0

T

500ms

Signal

0V

Backlight (Recommended)

500ms

100ms

T

5

T6

0.9 V

CC

0.1V

Power On

CC

0.9 V

cc

0.1V

T3T1

T

2

T4

VA L I D

Power Off

50%

5

T

50%

T

6

Power ON/OFF Sequence

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the

diagram below.

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Note.

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the

LCD operation or the LCD turns off before the backlight turns off, the display may momentarily

become abnormal screen. There is no reliability issue when the T5, T6 timing missing the range.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.

(4) T4 should be measured after the module has been fully discharged between power off and on

period.

(5) Interface signal shall not be kept at high impedance when the power is on.

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x

Y

7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage VCC 12V V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" Lamp Current I Oscillating Frequency (Inverter) F Vertical Frame Rate Fr 120 Hz

7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in Note (6).

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR

Response Time

Center Luminance of White L

White Variation Cross Talk CT - - 4 % Note (5)

Red

Green Color Chromaticity

Viewing Angle

Blue

White

Color Gamut

Horizontal

Vertica l

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Model No.: V470H1-LH2

25r2

50r10

L

W

Gray to

gray

C

GW

=0q, TY =0q

T

x

Rx Ry

Viewing Angle at Normal Direction

Gx 0.201 Gy

Bx

By Wx Wy

+

T

Tx-

+

CRt20

TY-

8.5r0.5 r3

40

1200 2000 - - Note (2)

- 4 - ms Note (3)

380 450

-

- - 1.3 - Note (7)

0.649

0.326

Typ.-

0.03

0.665

0.153

Typ.+

0.03

0.066

0.280

0.285

--

88 - % NTSC 80 88 80 88 80 88 80 88 -

Issue Date:Jul.06.2009

Apporval

o

C

%RH

mA

KHz

cd/

Note (4)

2

m

-

Note (6)

-

Deg. Note (1)

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T

Note (1) Definition of Viewing Angle (Tx, Ty):

Viewing angles are measured by Eldim EZ-Contrast 160R

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Normal

Tx = Ty = 0º

Ty- Ty

TX- = 90º

x-

Tx

6 o’clock

T

y- = 90º

y-

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L255 / L0

L255: Luminance of gray level 255

L 0: Luminance of gray level 0

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note

(7)

Note (3) Definition of Gray-to-Gray Switching Time:

Tx

12 o’clock direction

y+

T

y+ = 90º

x+

TX+ = 90º

100%

90%

Optical

Response

10%

0%

ime

Gray to gray Switching time

The driving signal means the signal of gray level 0, 63, 127, 191, and 255.

Gray to gray average time means the average switching time of gray level 0, 63,127,191,255 to each other.

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A

Note (4) Definition of Luminance of White (LC):

Measure the luminance of gray level 255 at center point.

LC = L (5), where L (x) is corresponding to the luminance of the point X at the figure in Note (7).

Note (5) Definition of Cross Talk (CT):

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CT = | Y

– YA | / YAu 100 (%)

B

Where:

Y

= Luminance of measured location without gray level 0 pattern (cd/m2)

A

Y

= Luminance of measured location with gray level 0 pattern (cd/m2)

B

ctive Area

Gray 128

Y

(D/8,W/2)

A, L

Y

(D/2,7W/8)

A, D

(0, 0)

Note (6) Measurement Setup:

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting backlight for 1 hour in a windless room.

Y

A, U

Y

A, R

(D, W)

(D/2,W/8)

(7D/8,W/2)

(D/4,W/4)

Y

(D/8,W/2)

B, L

Y

(D/2,7W/8)

B, D

(0, 0)

ctive Area

Gray 0

Gray 128

Y

(D/2,W/8)

B, U

Y

(7D/8,W/2)

B, R

(3D/4,3W/4)

(D, W)

LCD Module

LCD Panel

Center of the Screen

Display Color Analyzer

(Minolta CA210)

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (7) Definition of White Variation (GW):

Measure the luminance of gray level 255 at 5 points

GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

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Horizontal Line

D

D/4 D/2 3D/4

W/4

W/2

W

Vertical Line

3W/4

1 2

X

5

3 4

Active Area

: Test Point

X=1 to 5

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8. PRECAUTIONS

8.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD

modules in the specified storage conditions.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of CCFL will be higher than that of room

temperature.

8.2 SAFETY PRECAUTIONS

(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while

assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

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9. DEFINITION OF LABELS

9.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

Apporval

V470H1 -LH2 Rev. XX

CHI MEI

OPTOELECTRONICS

(a) Model Name: V470H1-LH2

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

(c) Serial ID: X X

X X X X X Y M D L N N N N

X X X X X X X Y M D L N N N N

MADE IN TAIWAN

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

Revision

E207943

MADE IN TAIWAN

RoHS

Serial ID includes the information as below:

(a) Manufactured Date: Year: 0~9, for 2000~2009

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1

(b) Revision Code: Cover all the change

(c) Serial No.: Manufacturing sequence of product

(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.

CMO Internal Use

st

to 31st, exclude I ,O, and U.

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10. PACKAGING

10.1 PACKING SPECIFICATIONS

(1) 3 LCD TV modules / 1 Box

(2) Box dimensions : 1190(L)x280(W)x712(H)mm

(3) Weight : approximately 52Kg ( 3 modules per box)

(4) Desiccant ( Drier ) : Weight 30g / 1 piece, Quantity 3 pcs, Cobalt chloride free

10.2 PACKING METHOD

Figures 10-1 and 10-2 are the packing method

LCD TV Module

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Model No.: V470H1-LH2

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Anti-static Bag

3pcs Drier

Cushion(Bottom)

Carton

Figure.10-1 packing method

Figure.9-1 packing method

PP Belt

Carton Label

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Air Transportation &

Sea / Land Transportation (40ft Container)

(L1130*50*50mm)

Film

(L1150*W1190*H140mm)

(L1400*50*50mm)

Sea / Land Transportation (40ft HQ Container)

(L1130*50*50mm)

(L625*50*50mm)

Film

(L1400*50*50mm)

(L1150*W1190*H140mm)

Figure.10-2 packing

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11. MECHANICAL CHARACTERISTIC

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࡛ભሽ՗ٝڶૻֆ׹

%*+/'+

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࡛ભሽ՗ٝڶૻֆ׹

%*+/'+

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࡛ભሽ՗ٝڶૻֆ׹

%*+/'+

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CMO V470H1-LH2 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual