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TFT LCD Approval Specification
MODEL NO.: V460H2 – LE1
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Issue Date:Apr. 12.2010
Model No.: V460H2-LE1
Tentative
TV Head Division
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-nan Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
Ken Wu HT Hung
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CONTENTS
REVISION HISTORY.................................................................................................................................................4
1. GENERAL DESCRIPTION....................................................................................................................................5
1.1 OVERVIEW....................................................................................................................................................5
1.2 FEATURES ....................................................................................................................................................5
1.3 APPLICATION................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS ........................................................................................................................5
1.5 MECHANICAL SPECIFICATION.....................................................................................................................6
2. ABSOLUTE MAXIMUM RATINGS ........................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7
2.2 PACKAGE STORAGE....................................................................................................................................8
2.3 ELECTRICAL ABSOLUTE RATINGS..............................................................................................................8
2.3.1 TFT LCD MODULE...............................................................................................................................8
2.3.2 BACKLIGHT CONVERTER UNIT .........................................................................................................8
3. ELECTRICAL CHARACTERISTICS......................................................................................................................9
3.1 TFT LCD MODULE.........................................................................................................................................9
3.2.1 LED CHARACTERISTICS (Ta=25± 2 ºC)............................................................................................12
3.2.2 CONVERTER CHARACTERISTICS ................................................................................................... 12
3.2.3 CONVERTER INTERFACE CHARACTERISTICS...............................................................................13
4. BLOCK DIAGRAM OF INTERFACE ...................................................................................................................15
4.1 TFT LCD MODULE.......................................................................................................................................15
5. INPUT TERMINAL PIN ASSIGNMENT................................................................................................................16
5.1 TFT LCD Module Input .................................................................................................................................16
5.2 CONVERTER UNIT......................................................................................................................................24
5.3 BLOCK DIAGRAM OF INTERFACE .............................................................................................................25
5.4 LVDS INTERFACE .......................................................................................................................................27
5.5 COLOR DATA INPUT ASSIGNMENT............................................................................................................28
6. INTERFACE TIMING...........................................................................................................................................29
6.1 INPUT SIGNAL TIMING SPECIFICATIONS..................................................................................................29
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6.2 POWER ON/OFF SEQUENCE.....................................................................................................................32
7. OPTICAL CHARACTERISTICS ..........................................................................................................................33
7.1 TEST CONDITIONS..................................................................................................................................... 33
7.2 OPTICAL SPECIFICATIONS........................................................................................................................34
8. PRECAUTIONS .................................................................................................................................................. 37
8.1 ASSEMBLY AND HANDLING PRECAUTIONS .............................................................................................37
8.2 SAFETY PRECAUTIONS .............................................................................................................................37
9. DEFINITION OF LABELS ...................................................................................................................................38
9.1 CMO MODULE LABEL.................................................................................................................................38
10. PACKAGING.....................................................................................................................................................40
11. MECHANICAL CHARACTERISTICS ................................................................................................................41
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REVISION HISTORY
Version Date
Ver. 0.0 Apr. 12.’10 All All The Tentative Specification was first issued.
Page
(New)
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Model No.: V460H2-LE1
Tentative
Section Description
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V460H2-LE1 is a 46” TFT Liquid Crystal Display module with LED Backlight and 4ch-LVDS interface. This
module supports 1920 x 1080 Full HDTV format and can display true 1.07G colors (8bit+Hi-FRC -bit/color). The
converter module for backlight is built-in.
1.2 FEATURES
Ё
High brightness (450 nits)
Ё
High contrast ratio (3000:1)
Ё
Fast response time (Gray to gray average 5.5 ms)
Ё
High color saturation (NTSC 72%)
Ё
Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё
DE (Data Enable) only mode
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Ё
LVDS (Low Voltage Differential Signaling) interface
Ё
Optimized response time for 240 Hz frame rate
Ё
Ultra wide viewing angle : Super MVA technology
Ё
RoHS compliance
1.3 APPLICATION
Ё
Standard Living Room TVs.
Ё
Public Display Application.
Ё
Home Theater Application.
Ё
MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 1018.08 (H) x 572.67 (V) (46” diagonal) mm
Bezel Opening Area 1024.48 (H) x 578.67 (V) mm
Driver Element a-si TFT active matrix -
Pixel Number 1920 x R.G.B. x 1080 pixel
Pixel Pitch (Sub Pixel) 0.1805 (H) x 0.5405 (V) mm
Pixel Arrangement RGB vertical stripe -
Display Colors 1.07G color
Display Operation Mode Transmissive mode / Normally Black -
Surface Treatment
Anti-Glare Coating (Haze 11%)
Hard Coating (3H)
(1)
- (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATION
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal(H) - 1076.5 - mm
Vertical(V) - 634.7 - mm
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Depth(D) 10.8 mm To Rear
Depth(D)
Weight TBD g
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TBD
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Model No.: V460H2-LE1
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(1)
mm To converter
cover
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
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Value
Unit Note
Min. Max.
X,Y
Shock (Non-Operating) SNOP
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
Љ
40 ºC).
axis
Z axis 35 G (3), (5)
- 35 G (3), (5)
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
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store the module with temperature from 0 to 35
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
к
at normal humidity without condensation.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Value
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT CONVERTER UNIT
Item Symbol
Light Bar Voltage VW
Min. Max.
Value
Min. Max.
Ё
60 V
Unit Note
(1)
Unit Note
Converter Input Voltage VBL 0 30 V (1)
Ё
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum value s are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Contro.l Internal PWM Control and External PWM Control.
-0.3 7 V (1), (3)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(Single-end)
Terminating Resistor R
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage V
Horizontal Stripe
Black Pattern
- - 4 A (2)
RUSH
-
-
-
V
LVT H
- - -100 mV
V
LVTL
| 200 - 600 mV
|V
ID
- 100 - ohm
T
0 - 0.7 V
IL
- TBD A
- TBD A
- TBD A
+100 - - mV
(3)
(4)
Note (2) Measurement condition:
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GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 240 Hz,
whereas a power dissipation check pattern below is displayed.
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a. White Pattern
Active Area
c. Horizontal Pattern
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT UNIT
3.2.1 LED CHARACTERISTICS (Ta=25± 2 ºC)
Parameter Symbol
Forward Voltage VW
LED Current IL
3.2.2 CONVERTER CHARACTERISTICS
(Ta = 25 ± 2 ºC)
Parameter Symbol
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Value
Min. Typ. Max.
3.0 3.2 3.5
- 120
Value
Min. Typ. Max.
Unit Note
V IL =120.0mA
mA
Unit Note
Issue Date:Apr. 12.2010
Model No.: V460H2-LE1
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Power Consumption PBL - 108 118.8 W IL =120mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Power Supply Current IBL - 4.5 5.0 A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN 5 10 - % (2)
Note (1) The measurement condition of Max. value is based on 46" backlight unit under input voltage 24V,
average LED current 120mA and lighting 30 minutes later.
Note (2) 5% minimum duty ratio is only valid for electrical operation.
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3.2.3 CONVERTER INTERFACE CHARACTERISTICS
Issue Date:Apr. 12.2010
Model No.: V460H2-LE1
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Parameter Symbol
ON
On/Off Control Voltage
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
MAX
MIN
HI
LO
VIPWM
VEPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Te st
Condition
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Value
Unit Note
Min. Typ. Max.
Ё
2.0
5.0 V
Ё
0
0.8 V
2.85 3.0 3.15 V maximum duty ratio
Ё
0
2.0
0
Ё
Ё
3.0 3.3 3.6 V
0
30
30
Ё
Ё
Ё
Ё
Ё
Ё
5.0 V
0.8 V
0.8 V
Ё
Ё
100 ms
V minimum duty ratio
Duty on
Duty off
Normal
Abnormal
ms
10%-90%V
BL
ms
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
T
on
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
1
100
300
Ё
100 ms
Ё
50 us
Ё
50 us
Ё
Ё
Ё
Ё
Ё
Ё
MΩ
ms
ms
BLON Delay Time
T
on1
BLON Off Time Toff
Ё
300
300
Ё
Ё
Ё
ms
Ё
ms
Ё
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш
PWM signal Ш BLON
Ш
PWM signal Ш VBL
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V
V
V
BL
V
BLON
EPWM
IPWM
9
Toff
%/
Tf1
9
%/
Tr1
9
%/
9
%/
2.0V
0.8V
Ton
Ton1
0
0
Backlight on duration
Tr
Tf
Ext. Dimming Function
T
PWMR
2.0V
0
0.8V
T
PWM
PWMF
T
Floating
3.3V
0
Floating
Int. Dimming Function
V
W
External
PWM
Period
External
PWM Duty
100%
Minimun
Duty
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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A_CH1_0(+/-)
A_CH1_1(+/-)
A_CH1_2(+/-)
A_CH1_3(+/-)
A_CH1_4(+/-)
A_CH1_CLK(+/-)
A_CH3_0(+/-)
A_CH3_1(+/-)
A_CH3_2(+/-)
A_CH3_3(+/-)
A_CH2_0(+/-)
A_CH2_1(+/-)
A_CH2_2(+/-)
A_CH2_3(+/-)
A_CH2_4(+/-)
A_CH2_CLK(+/-)
A_CH4_0(+/-)
A_CH4_1(+/-)
A_CH4_2(+/-)
A_CH4_3(+/-)
SELLVDS
INPUT CONNECTOR
CNF1: FI-RE41S-HF,JAE
DC/DC POWER
Taiwan
TIMING
CONTROLLER
XL DATA DRIVER
TFT LCD PANEL
CNF2: FI-RE51S-HF,JAE Taiwan
(1920x3x1080)
INPUT CONNECTOR
or equivalent
DC/DC POWER
DC/DC POWER
B_CH1_0(+/-)
B_CH1_1(+/-)
B_CH1_2(+/-)
B_CH1_3(+/-)
B_CH1_4(+/-)
B_CH1_CLK(+/-)
B_CH3_0(+/-)
B_CH3_1(+/-)
B_CH3_2(+/-)
B_CH3_3(+/-)
B_CH2_0(+/-)
B_CH2_1(+/-)
B_CH2_2(+/-)
B_CH2_3(+/-)
B_CH2_4(+/-)
B_CH2_CLK(+/-)
B_CH4_0(+/-)
B_CH4_1(+/-)
B_CH4_2(+/-)
B_CH4_3(+/-)
INPUT CONNECTOR
CNF3: FI-RE41S-HF,JAE
Taiwan
TIMING
XR DATA DRIVER
CONTROLLER
CNF4: FI-RE51S-HF,JAE Taiwan
INPUT CONNECTOR
or equivalent
DC/DC CONVERTER
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment (FI-RE41S-HF(JAE) or equivalent)
Pin Name Description Note
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 GND Ground
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7 GND Ground
8 GND Ground
9 GND Ground
10 A_CH1[0]- First pixel of A source. Negative LVDS differential data input. Pair 0
11 A_CH1[0]+ First pixel of A source. Positive LVDS differential data input. Pair 0
12 A_CH1[1]- First pixel of A source. Negative LVDS differential data input. Pair 1
13 A_CH1[1]+ First pixel of A source. Positive LVDS differential data input. Pair 1
14 A_CH1[2]- First pixel of A source. Negative LVDS differential data input. Pair l 2
15 A_CH1[2]+ First pixel of A source. Positive LVDS differential data input. Pair 2
16 GND Ground
17 A_CH1CLK- First pixel of A source. Negative LVDS differential clock input.
18 A_CH1CLK+ First pixel of A source. Positive LVDS differential clock input.
19 GND Ground
20 A_CH1[3]- First pixel of A source. Negative LVDS differential data input. Pair 3
21 A_CH1[3]+ First pixel of A source. Positive LVDS differential data input. Pair 3
22 A_CH1[4]- First pixel of A source. Negative LVDS differential data input. Pair 4
23 A_CH1[4]+ First pixel of A source. Positive LVDS differential data input. Pair 4
24 GND Ground
25 A_CH3[0]- Third pixel of A source. Negative LVDS differential data input. Pair 0
26 A_CH3[0]+ Third pixel of A source. Positive LVDS differential data input. Pair 0
27 A_CH3[1]- Third pixel of A source. Negative LVDS differential data input. Pair 1
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28 A_CH3[1]+ Third pixel of A source. Positive LVDS differential data input. Pair 1
29 A_CH3[2]- Third pixel of A source. Negative LVDS differential data input. Pair 2
30 A_CH3[2]+ Third pixel of A source. Positive LVDS differential data input. Pair 2
31 GND Ground
32 A_CH3CLK- Third pixel of A source. Negative LVDS differential clock input.
33 A_CH3CLK+ Third pixel of A source. Positive LVDS differential clock input.
34 GND Ground
35 A_CH3[3]- Third pixel of A source. Negative LVDS differential data input. Pair 3
36 A_CH3[3]+ Third pixel of A source. Positive LVDS differential data input. Pair 3
37 A_CH3[4]- Third pixel of A source. Negative LVDS differential data input. Pair 4
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38 A_CH3[4]+ Third pixel of A source. Positive LVDS differential data input. Pair 4
39 GND Ground
40 GND Ground
41 GND Ground
CNF2 Connector Pin Assignment (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 VCC +12V power supply
2 VCC +12V power supply
3 VCC +12V power supply
4 VCC +12V power supply
5 VCC +12V power supply
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 A_CH2[0]-
11 A_CH2[0]+
12 A_CH2[1]-
13 A_CH2[1]+
14 A_CH2[2]-
Second pixel of A source. Negative LVDS differential data input.
Pair 0
Second pixel of A source. Positive LVDS differential data input. Pair
0
Second pixel of A source. Negative LVDS differential data input.
Pair 1
Second pixel of A source. Positive LVDS differential data input. Pair
1
Second pixel of A source. Negative LVDS differential data input.
Pair 2
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15 A_CH2[2]+
16 GND Ground
17 A_CH2CLK- Second pixel of A source. Negative LVDS differential clock input.
18 A_CH2CLK+ Second pixel of A source. Positive LVDS differential clock input.
19 GND Ground
20 A_CH2[3]-
21 A_CH2[3]+
22 A_CH2[4]-
23 A_CH2[4]+
24 GND Ground
Second pixel of A source. Positive LVDS differential data input. Pair
2
Second pixel of A source. Negative LVDS differential data input.
Pair 3
Second pixel of A source. Positive LVDS differential data input. Pair
3
Second pixel of A source. Negative LVDS differential data input.
Pair 4
Second pixel of A source. Positive LVDS differential data input. Pair
4
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25 A_CH4[0]-
26 A_CH4[0]+ Fourth pixel of A source Positive LVDS differential data input. Pair 0
27 A_CH4[1]-
28 A_CH4[1]+ Fourth pixel of A source Positive LVDS differential data input. Pair 1
29 A_CH4[2]-
30 A_CH4[2]+ Fourth pixel of A source Positive LVDS differential data input. Pair 2
31 GND Ground
32 A_CH4CLK- Fourth pixel of A source Negative LVDS differential clock input.
33 A_CH4CLK+ Fourth pixel of A source Positive LVDS differential clock input.
34 GND Ground
35 A_CH4[3]-
36 A_CH4[3]+ Fourth pixel of A source Positive LVDS differential data input. Pair 3
37 A_CH4[4]-
38 A_CH4[4]+ Fourth pixel of A source Positive LVDS differential data input. Pair 4
Fourth pixel of A source Negative LVDS differential data input. Pair
0
Fourth pixel of A source Negative LVDS differential data input. Pair
1
Fourth pixel of A source Negative LVDS differential data input. Pair
2
Fourth pixel of A source Negative LVDS differential data input. Pair
3
Fourth pixel of A source Negative LVDS differential data input. Pair
4
39 GND Ground
40 SCL_I No Connection
41 GND Ground
42 C_LUT1 No Connection
43 TCON_WP No Connection
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44 SDA_I No Connection
45 GMA_SEL No Connection
46 C_TST_AGE No Connection
47 A_SCL No Connection
48 A_SDA No Connection
49 GND Ground
50 C_SEL_POL No Connection
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51 LVDS_SEL
CNF3 Connector Pin Assignment (FI-RE41S-HF(JAE) or equivalent)
Pin Name Description Note
1 VCC +12V power supply
2 VCC +12V power supply
3 VCC +12V power supply
4 VCC +12V power supply
5 VCC +12V power supply
6 GND Ground
7 GND Ground
8 GND Ground
9 GND Ground
10 B_CH1[0]- First pixel of B source. Negative LVDS differential data input. Pair 0
11 B_CH1[0]+ First pixel of B source. Positive LVDS differential data input. Pair 0
LVDS data format Selection
Ш
(0V~0.7V/OPEN
VESA, 2.7V~3.3VШ JEIDA)
12 B_CH1[1]- First pixel of B source. Negative LVDS differential data input. Pair 1
13 B_CH1[1]+ First pixel of B source. Positive LVDS differential data input. Pair 1
14 B_CH1[2]-
15 B_CH1[2]+ First pixel of B source. Positive LVDS differential data input. Pair 2
16 GND Ground
17 B_CH1CLK- First pixel of B source. Negative LVDS differential clock input.
18 B_CH1CLK+ First pixel of B source. Positive LVDS differential clock input.
19 GND Ground
20 B_CH1[3]- First pixel of B source. Negative LVDS differential data input. Pair 3
First pixel of B source. Negative LVDS differential data input. Pair l
2
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21 B_CH1[3]+ First pixel of B source. Positive LVDS differential data input. Pair 3
22 B_CH1[4]- First pixel of B source. Negative LVDS differential data input. Pair 4
23 B_CH1[4]+ First pixel of B source. Positive LVDS differential data input. Pair 4
24 GND Ground
25 B_CH3[0]- Third pixel of B source. Negative LVDS differential data input. Pair 0
26 B_CH3[0]+ Third pixel of B source. Positive LVDS differential data input. Pair 0
27 B_CH3[1]- Third pixel of B source. Negative LVDS differential data input. Pair 1
28 B_CH3[1]+ Third pixel of B source. Positive LVDS differential data input. Pair 1
29 B_CH3[2]- Third pixel of B source. Negative LVDS differential data input. Pair 2
30 B_CH3[2]+ Third pixel of B source. Positive LVDS differential data input. Pair 2
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31 GND Ground
32 B_CH3CLK- Third pixel of B source. Negative LVDS differential clock input.
33 B_CH3CLK+ Third pixel of B source. Positive LVDS differential clock input.
34 GND Ground
35 B_CH3[3]- Third pixel of B source. Negative LVDS differential data input. Pair 3
36 B_CH3[3]+ Third pixel of B source. Positive LVDS differential data input. Pair 3
37 B_CH3[4]- Third pixel of B source. Negative LVDS differential data input. Pair 4
38 B_CH3[4]+ Third pixel of B source. Positive LVDS differential data input. Pair 4
39 GND Ground
40 GND Ground
41 GND Ground
CNF4 Connector Pin Assignment (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 VCC +12V power supply
2 VCC +12V power supply
3 VCC +12V power supply
4 VCC +12V power supply
5 VCC +12V power supply
6 GND Ground
7 GND Ground
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8 GND Ground
9 GND Ground
10 B_CH2[0]-
11 B_CH2[0]+
12 B_CH2[1]-
13 B_CH2[1]+
14 B_CH2[2]-
15 B_CH2[2]+
16 GND Ground
Second pixel of B source. Negative LVDS differential data input.
Pair 0
Second pixel of B source. Positive LVDS differential data input. Pair
0
Second pixel of B source. Negative LVDS differential data input.
Pair 1
Second pixel of B source. Positive LVDS differential data input. Pair
1
Second pixel of B source. Negative LVDS differential data input.
Pair 2
Second pixel of B source. Positive LVDS differential data input. Pair
2
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17 B_CH2CLK- Second pixel of B source. Negative LVDS differential clock input.
18 B_CH2CLK+ Second pixel of B source. Positive LVDS differential clock input.
19 GND Ground
20 B_CH2[3]-
21 B_CH2[3]+
22 B_CH2[4]-
23 B_CH2[4]+
24 GND Ground
25 B_CH4[0]-
26 B_CH4[0]+
27 B_CH4[1]-
28 B_CH4[1]+
29 B_CH4[2]-
30 B_CH4[2]+
31 GND Ground
Second pixel of B source. Negative LVDS differential data input.
Pair 3
Second pixel of B source. Positive LVDS differential data input. Pair
3
Second pixel of B source. Negative LVDS differential data input.
Pair 4
Second pixel of B source. Positive LVDS differential data input. Pair
4
Fourth pixel of B source. Negative LVDS differential data input. Pair
0
Fourth pixel of B source. Positive LVDS differential data input. Pair
0
Fourth pixel of B source. Negative LVDS differential data input. Pair
1
Fourth pixel of B source. Positive LVDS differential data input. Pair
1
Fourth pixel of B source. Negative LVDS differential data input. Pair
2
Fourth pixel of B source. Positive LVDS differential data input. Pair
2
32 B_CH4CLK- Fourth pixel of B source. Negative LVDS differential clock input.
33 B_CH4CLK+ Fourth pixel of B source. Positive LVDS differential clock input.
34 GND Ground
35 B_CH4[3]-
36 B_CH4[3]+
Fourth pixel of B source. Negative LVDS differential data input. Pair
3
Fourth pixel of B source. Positive LVDS differential data input. Pair
3
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37 B_CH4[4]-
38 B_CH4[4]+
39 GND Ground
40 N.C. No Connection
41 GND Ground
N240_SYNC_
42
ASIC
43 N240_EN No Connection
44 N.C. No Connection
45 TCK No Connection
Fourth pixel of B source. Negative LVDS differential data input. Pair
4
Fourth pixel of B source. Positive LVDS differential data input. Pair
4
No Connection
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46 TDO No Connection
47 TMS No Connection
48 TDI No Connection
49 GND Ground
50 V33F No Connection
51 N.C. No Connection
Note (1) Reserved for internal use. Please leave it open.
Note (2)
High=connect to +3.3V : JEIDA Format Ι Low= connect to GND or Open : VESA Format.
Note (3) Interface optional pin has internal scheme as following diagram. Customer
should keep the interface voltage level requirement as below.
System Board Panel Board
1K ohm
IC
Interface Voltage Level
VH > 3.0V
VL < 0.7V
>20K ohm
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Note (4) LVDS 4-port of 1 source Data Mapping
Port CH of LVDS Data Stream
Port 1 1st pixel 1, 3, 5, ..........., 1917, 1919
Port 2 2nd pixel 2, 4, 6, ........., 1918, 1920
Port 3 1st pixel 1, 3, 5, ..........., 1917, 1919
Port 4 2nd pixel 2, 4, 6, ........., 1918, 1920
Note (3) I2C Clock and Data interface
Connectors on Control Board Arrangement:
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TCON B TCON A
CNF1 CNF2 CNF3 CNF4
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5.2 CONVERTER UNIT
CN1:
CI0114M1HR0-LF (CvilLux)
Pin № Symbol Feature
1
2
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or equivalent
3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Note (2) Pin 13: Internal PWM control (use pin 13): Pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN2~CN5: 51281-1094 (Molex) ,
187059-51221 (P-TWO),
Pin № Symbol Feature NOTE
1 VLED
2 VLED
3 NC
4 NC
5 NC
6 N1
7 N2
8 N3
9 N4
10 N5
Positive of LED String
No Connection
Negative of LED String
24
7083K-F10N-00L (E&T)
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5.3 BLOCK DIAGRAM OF INTERFACE
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
The third and fourth pixel are followed the same rules.
CR0~CR9: Third pixel R data
CG0~CG9: Third pixel G data
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CB0~CB9: Third pixel B data
DR0~DR9: Fourth pixel R data
DG0~DG9: Fourth pixel G data
DB0~DB9: Fourth pixel B data
Note (1) A ~ D channel are first, second, third and fourth pixel respectively.
Note (2) The system must have the transmitter to drive the module.
Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line
when it is used differentially.
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5.4 LVDS INTERFACE
VESA Format : SELLVDS = H or Open
JEIDA Format : SELLVDS = L
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AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE: Data enable signal
DCLK: Data clock signal
RSV: Reserved
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)
5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of
color versus data input.
Color
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0)/Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0
Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue(0)/Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
R9R8R7R6R5R4R3R2R1R0G9G8G7G6G5G4G3G2G1G0B9B8B7B6B5B4B3B2B1B
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
/
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
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0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
0
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
0
1
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Signal
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
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0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
;
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
:
:
:
:
:
:
1
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
1
0
0
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
LVDS
Receiver
Clock
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
(=1/TC)
F
Spread spectrum
modulation frequency
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F
clkin
- - 200 ps (3)
T
rcl
clkin_mod
- - 200 KHz
F
SSM
60 74.25 80 MHz
F
-2% - F
clkin
+2% MHz
clkin
(4)
LVDS
Receiver
Data
Setup Time Tlvsu 600 - - ps
(5)
Hold Time Tlvhd 600 - - ps
Fr5 97 100 103 Hz
(6)
Tv=Tvd+T vb
Ё
Ё
Th=Thd+Thb
Ё
Ё
Vertical
Active
Display
Term
Horizontal
Active
Display
Term
Frame Rate
117 120 123 Hz
F
r6
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Th 540 550 575 Tc
Display Thd 480 480 480 Tc
Blank Thb 60 70 95 Tc
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2
ʼʳ ʳ ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˼˸˿ʳ˶˿˶˾ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼ˍʳ ʳ ʳ
˙
˶˿˾˼ʻ˴ʼ
ʳЊʳ˙
ˉ
ʳ Ѽʳ ˧ʳ Ѽʳ ˧˻
ʳ
˙
ˈ
ʳ Ѽʳ ˧ʳ Ѽʳ ˧˻ʳ Њʳ ˙
˶˿˾˼ʻ˼ʼ
ʳ
ʳ
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INPUT SIGNAL TIMING DIAGRAM
DE
Th
DCLK
DE
DATA
Tvd
Tv
Tvb
Thd
Valid display data ( 960 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T
– TI
1
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Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
RXCLK+/-
RXn+/-
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
Tlvsu
Tlvhd
Note (6) : (ODSEL) = H/L or open for 100/120Hz frame rate. Please refer to 5.1 for detail information
ᙑᙑᙑᙑ
ᎄᎄᎄᎄ
3T
!
14
5T
14
7T
14
9T
14
11T
14
13T
14
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6.2 POWER ON/OFF SEQUENCE
TBD
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
LED Current IL
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
25±2
50±10
120 ±3.6
oC
%RH
mA
LCD Module
LCD Panel
Field of View = 1º
500 mm
CS - 2000
Light Shield Room
(Ambient Luminance < 2 lux)
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR 2000 3000 - - Note (2)
Response Time
Center Luminance of White L
White Variation
Cross Talk CT - - 4 % Note (5)
Red
Green
Color
Chromaticity
Viewing
Angle
Blue
White
Color Gamut
Horizontal
Vertical
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Model No.: V460H2-LE1
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Gray to
gray
C
δW
θ
=0°, θY =0°
Rx TBD Ry
Gx
Gy
Bx
By
Wx
Wy
θx+
θ
-
x
θY+
θ
-
Y
x
Viewing angle at
normal direction
CR≥20
- TBD ms Note (3)
450 - cd/m2Note (4)
- - 1.3 - Note (6)
TBD
TBD
Typ.-
0.03
80 88 80 88 80 88 80 88 -
TBD
TBD
TBD
TBD
TBD
72 - % NTSC
Typ.+
0.03
-
-
-
-
-
-
-
Deg. Note (1)
Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80.
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
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Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
Note (3) Definition of Gray-to-Gray Switching Time:
The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892, and 1023.Gray to
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
gray. Average time means the average switching time of gray level 0, 124, 252, 380, 508, 636, 764, 892, and
1023 to each other.
Note (4) Definition of Luminance of White (LC):
Measure the luminance of gray level 1023 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
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(
)
(
)
Note (5) Definition of Cross Talk (CT):
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Model No.: V460H2-LE1
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CT = | Y
– YA | / YA × 100 (%)
B
Where:
(a)
= Luminance of measured location without gray level 1023 pattern (cd/m2)
Y
A
= Luminance of measured location with gray level 1023 pattern (cd/m2)
Y
B
(0,
XR
Active Area
Y
(D/8,W/2)
A, L
Gray 512
Y
(D/2,7W/8)
A, D
Note (6) Definition of White Variation (
δ
W):
Y
Y
D, W
A, U
A, R
(D/2,W /8)
(7D/8,W/2)
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
TIMING
B,
0, 0
Active Area
Gray 0
Gray 1023
Gray 512
Y
(D/2,W /8)
B, U
Y
B, R
(3D/4,3W/4)
(D, W)
(7D/8,W/
Measure the luminance of gray level 1023 at 5 points
δ
W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
Horizontal Line
D
W
4
W
D
4
D
2
1 2
5
3D
4
X
Test point :
X = 1 ~ 5
2
3 4
3W
4
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
к
recommended to store the module with temperature from 0 to 35
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
at normal humidity without
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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Model No.: V460H2-LE1
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CHI MEI
OPTOELECTRONICS
CHI MEI
OPTOELECTRONICS
Model Name: V460H2-LE1
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
V460H2–LE1 Rev. XX
X X X X X X X Y M D L N N N N
X X X X X X X Y M D L N N N N
Serial No.
Product Line
E207943
MADE IN TAIWAN
GEMN
RoHS
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year: 2001=1,2002=2,2003=3,2004=4…2010=0,2011=1,2012=2..
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
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Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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10. PACKAGING
TBD
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11. MECHANICAL CHARACTERISTICS
TBD
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