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TFT LCD Approval Specification
MODEL NO.: V420H2 – LH3
Customer :
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Issue Date : Apr.06.2010
Model No.: V420H2-LH3
Approval
Approved by :
Note :
TV Head Division
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
KC Ko WT Lin
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Ken Wu Huii Wen
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Issue Date : Apr.06.2010
Model No.: V420H2-LH3
Approval
CONTENTS
REVISION HISTORY................................................................................................................................................................4
1. GENERAL DESCRIPTION...................................................................................................................................................5
1.1 OVERVIEW..................................................................................................................................................................5
1.2 FEATURES...................................................................................................................................................................5
1.3 APPLICATION............................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS....................................................................................................................................5
1.5 MECHANICAL SPECIFICATIONS...........................................................................................................................6
2. ABSOLUTE MAXIMUM RATINGS....................................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT............................................................................................................ 7
2.2 PACKAGE STORAGE.................................................................................................................................................8
2.3 ELECTRICAL ABSOLUTE RATINGS........................................................................................................................8
2.3.1 TFT LCD MODULE.......................................................................................................................................... 8
2.3.2 BACKLIGHT INVERTER UNIT ......................................................................................................................8
3. ELECTRICAL CHARACTERISTICS ................................................................................................................................... 9
3.1 TFT LCD MODULE.....................................................................................................................................................9
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION.......................................................................................... 12
3.2.1 LAMP SPECIFICATION ................................................................................................................................12
3.2.2 ELECTRICAL SPECIFICATION....................................................................................................................12
3.2.3 INVERTER INTERFACE CHARACTERISTICS ...........................................................................................13
4. BLOCK DIAGRAM OF INTERFACE................................................................................................................................ 16
4.1 TFT LCD MODULE...................................................................................................................................................16
5. INPUT TERMINAL PIN ASSIGNMENT..........................................................................................................................17
5.1 TFT LCD Module Input ............................................................................................................................................17
5.2 BACKLIGHT UNIT................................................................................................................................................... 21
5.3 INVERTER UNIT....................................................................................................................................................... 21
5.4 BLOCK DIAGRAM OF INTERFACE.......................................................................................................................22
5.5 LVDS INTERFACE....................................................................................................................................................24
5.6 COLOR DATA INPUT ASSIGNMENT................................................................................................................... 25
6. INTERFACE TIMING.........................................................................................................................................................26
6.1 INPUT SIGNAL TIMING SPECIFICATIONS.........................................................................................................26
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Model No.: V420H2-LH3
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6.2 POWER ON/OFF SEQUENCE ................................................................................................................................ 28
7. OPTICAL CHARACTERISTICS ........................................................................................................................................29
7.1 TEST CONDITIONS.................................................................................................................................................. 29
7.2 OPTICAL SPECIFICATIONS ................................................................................................................................... 30
8. PRECAUTIONS .................................................................................................................................................................. 33
8.1 ASSEMBLY AND HANDLING PRECAUTIONS...................................................................................................33
8.2 SAFETY PRECAUTIONS.......................................................................................................................................... 33
9. DEFINITION OF LABELS.................................................................................................................................................. 34
9.1 CMO MODULE LABEL............................................................................................................................................ 34
10. PACKAGING.................................................................................................................................................................... 35
10.1 PACKAGING SPECIFICATIONS .......................................................................................................................... 35
10.2 PACKAGING METHOD ........................................................................................................................................ 35
11. MECHANICAL CHARACTERISTIC..............................................................................................................................37
Appendix – TWO Wire BUS INTRODUCTION................................................................................................................... 39
A.1 PIN ASSIGNMENT..................................................................................................................................................39
A.2 I2C BUS APPLICATION NOTE.............................................................................................................................. 39
A.3 TWO WIRE BUS DEVICE ADDRESS .....................................................................................................................39
A.4 TWO WAY TO CONTROL THE TWO WIRE BUS................................................................................................ 41
A.5 TWO WIRE BUS COMMAND TABLE...................................................................................................................42
A.6 TWO WIRE BUS REQUIREMENT..........................................................................................................................45
A.6 TWO WIRE BUS REQUIREMENT..........................................................................................................................46
A.7 THE TWO WIRE BUS SEQUENCE.........................................................................................................................46
A.7 THE TWO WIRE BUS SEQUENCE.........................................................................................................................47
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Version Date Page(New) Section Description
Ver. 2.0 Apr. 06, 2010 All All The approval specification was first issued.
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Issue Date : Apr.06.2010
Model No.: V420H2-LH3
Approval
REVISION HISTORY
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H2-LH3 is a 42” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit). The inverter module
for backlight is built-in.
1.2 FEATURES
Ё High brightness (450 nits)
Ё High contrast ratio (5000:1)
Ё Fast response time (Gray to gray average 6.5 ms)
Ё High color saturation (NTSC 72%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs
Ё Public Display Application
Ё Home Theater Application
Ё MFM Application
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 930.24(H) x 523.26 (V) (42.02” diagonal) mm
Bezel Opening Area 939 (H) x 531 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
(1)
Pixel Pitch(Sub Pixel) 0.1615 (H) x 0.4845 (V) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment Anti-Glare coating (Haze 11%) - (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 982.0 983.0 984.0 mm (1)
Vertical (V) 575.0 576.0 577.0 mm (1)
Module Size
Depth (D) 46.1 47.1 48.1 mm (2)
Depth (D) 49.8 50.8 51.8 mm (3)
Weight - 10100 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Note (3) Module Depth is between bezel to Inverter cover.
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
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Value
Unit Note
Min. Max.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature
of display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so
that the module would not be twisted or bent by the fixture.
Љ 40 ºC).
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended
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to store the module with temperature from 0 to 35
(b) The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
к at normal humidity without condensation.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Value
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT INVERTER UNIT
Item Symbol
Lamp Voltage VW
Min. Max.
Value
Min. Max.
Ё
3000 VRMS
Unit Note
(1)
Unit Note
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
Ё
-0.3 7 V (1), (3)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
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Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
Terminating Resistor R
CMOS
interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
RUSH
Ё Ё
Ё Ё
Ё Ё
V
LVTH
V
LVTL
| 200
|V
ID
T
0
IL
+100
Ё Ё
1.81
1.54
0.85
Ё Ё
Ё Ё
Ё
Ё
100
Ё
Ё
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
4.2 A (2)
Ё
Ё
Ё
A
A
A
(3)
mV
-100 mV
(4)
600 mV
Ё
ohm
3.3 V
0.7 V
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GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
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= 60 Hz,
v
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Model No.: V420H2-LH3
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c. Horizontal Pattern
a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows :
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
Issue Date : Apr.06.2010
Model No.: V420H2-LH3
Approval
Value
Unit Note
Lamp Input Voltage VL - (1090) - V
Lamp Current IL
10.0 10.5 11.0
8.5 9.0 9.5
- - (1910) V
mA
RMS
RMS
RMS
Lamp Turn On Voltage VS
- - (1560) V
RMS
Operating Frequency FL 35 - 70 KHz
Lamp Life Time LBL 50,000 - - Hrs
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Unit Note
Min. Typ. Max.
- 130 142 (5),(6) IL = 10.5 mA
Power Consumption PBL
- 110 122 W (5),(6) IL = 9.0 mA
Ta = 0 ºC
Ta = 25 ºC
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
- 5.4 5.9
Power Supply Current IBL
A Non Dimming
4.6 5.1
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 39 42 45 kHz (3)
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio D
- 20 - %
MIN
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.
Note (2) The lamp starting voltage V
should be applied to the lamp for more than 1 second after startup.
S
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
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display input signals, and it may result in line flow on the display. In order to avoid interference,
the lamp frequency should be detached from the horizontal synchronous frequency and its
harmonics as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value
and the effective discharge length is longer than 80% of its original length (Effective discharge
length is defined as an area that has equal to or more than 70% brightness compared to the
brightness at the center point of lamp.) as the time in which it continues to operate under the
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condition at Ta = 25 ±2
Note (5) The power supply capacity should be higher than the total inverter power consumption P
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 42" backlight unit under input voltage 24V,
average lamp current 9.3 mA and 10.8 mA and lighting 30 minutes later.
к and I
= (8.5~ 11.0) mArms.
L
. Since
BL
3.2.3 INVERTER INTERFACE CHARACTERISTICS
Parameter Symbol
Test
Value
13
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Min. Typ. Max.
ON
On/Off Control Voltage
V
BLON
OFF
Internal PWM Control
Voltage
MAX
MIN
V
IPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time T
PWM Signal Falling Time T
PWMR
PWMF
Input Impedance RIN
Ё
2.0
Ё
Ё
0
3.15
Ё
Ё
Ё
5.0 V
0.8 V
5.0 V Max. Duty Ratio
Ё Ё
Ё
Ё
Ё
Ё
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё
3.0 3.3 3.6 V Normal
0
30
30
1
0
Ё
Ё
Ё
Ё Ё
Ё
V Min. Duty Ratio
0.8 V Abnormal
Ё
Ё
100 ms
100 ms
50 us
ms
ms
10%-90%V
BL
50 us
MΩ
PWM Delay Time
BLON Delay Time
BLON Off Time
T
PWM
T
T
on1
on
Ё
Ё
Ё
100
300
300
Ё Ё
Ё Ё
Ё Ё
ms
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
→
PWM signal → BLON
→
PWM signal → VBL
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(Adin Function will be change to EPWM)
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ODD_RIN0+/ODD_RIN1+/ODD_RIN2+/ODD_RIN3+/ODD_RIN4+/ODD_CLK+/-
EVEN_RIN0+/EVEN_RIN1+/EVEN_RIN2+/EVEN_RIN3+/EVEN_RIN4+/EVEN_CLK+/-
RPF
MEN
MCFG 0
MCFG 1
LVDS8b
GV_mode
SELLVDS
ODSE
SCL
(FI-RE51S-HF (JAE)) or equivalent
INPUT CONNECTOR
FRAME
BUFFER
MEMC
& REFERENCE VOLTAGE
VIN
GND
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TIMING
CONTROLLER
DC/DC CONVERTER
GENERATOR
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SCAN DRIVER
TFT LCD PANEL
(1920x3x1080)
Data Driver (mini-LVDS
VBL
GND
Status
A_DIM
I_PWM
BLON
INVERTER
CONNECTOR
CN1:S14B-PH-SM4-TB
(D)(LF) or equivalent
CN2-CN7:SM02 (13.0)-BDAS-3-TB(LF)(JST) or equivalent
BACKLIGHT
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
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CNF1 Connector Part No.: JAE Taiwan (
Pin Name Description Note
1 RPF Reverse picture function (default low) 8
2 MEN MEMC function selection 5
3 MCFG0 MEMC function selection 5
4 MCFG1 MEMC function selection 5
5 LVDS8b 8bit/10bit LVDS input selection 6
6 GV_mode Graphic / Video mode selection 7
7 SELLVDS LVDS data format Selection 3
8 SCL I2C CLK Signal ʳ
9 SDA. I2C Data Signal ʳ
10 ODSEL Overdrive Lookup Table Selection 4
11 GND Ground ʳ
12 ERX0- 2nd pixel Negative LVDS differential data input. Channel 0 ʳ
13 ERX0+ 2nd pixel Positive LVDS differential data input. Channel 0 ʳ
14 ERX1- 2nd pixel Negative LVDS differential data input. Channel 1 ʳ
15 ERX1+ 2nd pixel Positive LVDS differential data input. Channel 1 ʳ
16 ERX2- 2nd pixel Negative LVDS differential data input. Channel 2 ʳ
17 ERX2+ 2nd pixel Positive LVDS differential data input. Channel 2 ʳ
18 GND Ground ʳ
19 ECLK- 2nd pixel Negative LVDS differential clock input. ʳ
20 ECLK+ 2nd pixel Positive LVDS differential clock input. ʳ
21 GND Ground ʳ
22 ERX3- 2nd pixel Negative LVDS differential data input. Channel 3 ʳ
23 ERX3+ 2nd pixel Positive LVDS differential data input. Channel 3 ʳ
24 ERX4- 2nd pixel Negative LVDS differential data input. Channel 4 ʳ
25 ERX4+ 2nd pixel Positive LVDS differential data input. Channel 4 ʳ
26 N.C. No Connection 2
27 N.C. No Connection 2
28 ORX0- 1st pixel Negative LVDS differential data input. Channel 0 ʳ
29 ORX0+ 1st pixel Positive LVDS differential data input. Channel 0 ʳ
30 ORX1- 1st pixel Negative LVDS differential data input. Channel 1 ʳ
31 ORX1+ 1st pixel Positive LVDS differential data input. Channel 1 ʳ
32 ORX2- 1st pixel Negative LVDS differential data input. Channel 2 ʳ
33 ORX2+ 1st pixel Positive LVDS differential data input. Channel 2 ʳ
34 GND Ground ʳ
35 OCLK- 1st pixel Negative LVDS differential clock input. ʳ
36 OCLK+ 1st pixel Positive LVDS differential clock input. ʳ
37 GND Ground ʳ
38 ORX3- 1st pixel Negative LVDS differential data input. Channel 3 ʳ
39 ORX3+ 1st pixel Positive LVDS differential data input. Channel 3 ʳ
40 ORX4- 1st pixel Negative LVDS differential data input. Channel 4 ʳ
ሽ) FI-RE51S-HF or equivalent.
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41 ORX4+ 1st pixel Positive LVDS differential data input. Channel 4 ʳ
42 N.C. No Connection 2
43 N.C. No Connection 2
44 GND Ground ʳ
45 GND Ground ʳ
46 GND Ground ʳ
47 N.C. No Connection 2
48 VCC +12V power supply ʳ
49 VCC +12V power supply ʳ
50 VCC +12V power supply ʳ
51 VCC +12V power supply ʳ
Note (1) LVDS connector pin order defined as follows
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Note (2) Reserved for internal use. Please leave it open.
Note (3)
SELLVDS Mode
L(default) VESA
H JEIDA
L: Connect to GND, H: Connect to +3.3V
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
ODSEL Description
L(default) Lookup table was optimized for 60 Hz frame rate input.
H Lookup table was optimized for 50 Hz frame rate input.
L: Connect to GND, H: Connect to +3.3V
Note (5) Motion Engine (ME) Level & Demo Function Table
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Motion engine level must be adjusted after video mode is selected (or entered).
Adjusting the motion engine level in graphic mode has no effect
MEN MCFG1 MCFG0 Notes
Blanking disable 0 0 0 (a)
Blanking
Demo mode (d) 0 1 1 Demo Window
ME
Level
(a) Module re-starts processing video signals from Frontend scaler control board.
Auto blanking 0 0 1 (b)
Blanking enable 0 1 0 (c)
Strong 1 0 0 Enable Strong Strong
Medium(Default) 1 0 1 Enable Normal Normal
Weak 1 1 0 Enable Weak ×
OFF 1 1 1 × × ×
(e) (f) (g)
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(b) During sync unstable period such as format change, 60Hz <-> 50Hz .
MCFG0 can be used to insert blanking of 500ms. This signal is toggled.
(c) Module continues to insert blanking until blanking disable signal is received from frontend scaler board.
(d) Demo window mode: Demo Window appears to the left half of display area. Left side with frame is
120Hz with MEMC, and right side is 120Hz w/o motion compensation.
(e) GPIO (General Purpose I/O) sequence of ME Level: (1) MEN; (2) MCFG1; (3) MCFG0.
GPIO sequence of Blanking Enable, Blanking Disable and Demo window: (1) MCFG1; (2) MCFG0; (3)
MEN.
(f) Each scaler command must be maintained the same voltage level at least 100ms.
(g) 0 : Connect to GND, 1 : +3.3V
Note (6) 8bit/10bit LVDS input selection
LVDS8b Bit depth
H(default) 8bit
L 10bit
L : Connect to GND, H : Connect to +3.3V
ʳ
ʳ
Note (7) Graphic / Video mode selection
There is no prohibited time period for switching between Graphic mode and Video mode.
When this switching signal is input, LCD will be reset and will re-start selected mode.
GV_mode Mode select MEMC ON/OFF
H(default) Graphic mode MEMC OFF
L Video mode MEMC ON
L : Connect to GND, H : Connect to +3.3V
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Note (8)
SELLVDS Mode
L(default) Normal Display
H Rotation Display
L: Connect to GND, H: Connect to +3.3V
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color
1 HV High Voltage White
2 HV High Voltage Pink
1 HV(White)
2 HV(Pink)
1 HV(White)
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2 HV(Pink)
1 HV(White)
2 HV(Pink)
5.3 INVERTER UNIT
CN1: S14B-PH-SM3-TB(D)(LF)(JST) or equivalent
Pin № Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 STATUS
12 A_DIM
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Amplitude Dimming Control
HI (2.0V ~ 5.0V)
LO(0V~0.8V)
CN2-CN7: SM02 -BDAS-3-TB(JST) or equivalent
Pin No. Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
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5.4 BLOCK DIAGRAM OF INTERFACE
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ARx0 +
ARx0 -
ARx1 +
ARx1 -
ARx2 +
ARx2 -
ARx3 +
ARx3 -
ARx4 +
ARx4 -
ACLK +
ACLK -
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
100pF
100pF
PLL
RxOUT
– AR9
AR0
– AG9
AG0
– AB9
AB0
DE
BRx0 +
BRx0 -
BRx1 +
BRx1 -
BRx2 +
BRx2 -
BRx3 +
BRx3 -
BRx4 +
BRx4 -
BCLK +
BCLK -
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
100pF
100pF
PLL
BR0
– BR9
– BG9
BG0
– BB9
BB0
DCLK
DCLK
Timing
Controller
LVDS Receiver
(MASTER)
LVDS INPUT
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ER0~ER7 Even pixel R data OR0~OR7 Odd pixel R data
EG0~EG7 Even pixel G data OG0~OG7 Odd pixel G data
EB0~EB7 Even pixel B data OB0~OB7 Odd pixel B data
DE Data enable signal
DCLK Data clock signal
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9 : First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9 : First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9 : First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG 1 AG0 AR1 AR0AR0 REV
24
DE
REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus
data input.
Data Signal
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (253)
Blue (254)
Blue (255)
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
0
:
:
:
:
1
0
0
0
1
0
0
0
0
0
0
0
:
:
:
:
0
1
0
1
0
1
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
F
clkin
Frequency
(=1/TC
)
LVDS
Receiver
Clock
Input cycle to
cycle jitter
Spread spectrum
modulation range
T
clkin_mo
F
rcl
d
Spread spectrum
modulation
F
SSM
frequency
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60 74.25 78 MHz
30
Ё Ё
F
-2%
clkin
Ё
Ё
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Model No.: V420H2-LH3
Approval
200 ps (2)
F
+2% MHz
clkin
(3)
50 KHz
LVDS
Setup Time Tlvsu 600
Ё Ё
Receiver
Data
Hold Time Tlvhd 600
Ё Ё
Fr5 47 50 53 Hz
Frame Rate
57 60 62 Hz
F
Vertical
Active
Display
Term
Total Tv 1110 1125 1135 Th
Display Tvd 1080 1080 1080 Th
r6
Blank Tvb 30 45 55 Th
Horizontal
Active
Display
Term
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
Note (1) Please make sure the range of frame rate has follow the below equationΚ
Fr(max) Њ Fclkin Я Tv×Th Љ Fr(min)
Note (2) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
ps
ps
Tv=Tvd+Tvb
Th=Thd+Th b
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Note (3) The SSCG (Spread spectrum clock generator) is defined as below figures.
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
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50ms
50ms
Љ
T4
0V
0.5ЉT1Љ10ms
ЉT2Љ
0
0
ЉT3Љ
500ms
0.1V
CC
3
T1
T
T
2
0.1V
T4
cc
LVDS Signals
0V
Power On
VALI D
Power Off
0ЉT7ЉT2
0
Љ
T8
T7
8
T
Option Signals
(SELLVDS,GPIO setting..…)
Backlight (Recommended)
Љ
1500ms
100ms
T5
Љ
T6
50%
5
T
50%
T
6
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
Power ON/OFF Sequence
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL 10.5 mA
Oscillating Frequency (Inverter) FW 42 KHz
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change
during measuring. In order to stabilize the luminance, the measurement should be executed after lighting
backlight for 1 hour in a windless room.
25±2
50±10
oC
%RH
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR 4000 6000 - - Note (2)
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Response Time
Center Luminance of White LC 360 450 -
White Variation
Cross Talk CT - - 4 % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Color Gamut C.G
Gray to
gray
δW
Rx 0.635 -
Ry 0.323 -
Gx 0.288 -
Gy 0.600 -
Bx 0.148 -
By 0.050 -
Wx 0.280 -
Wy
θx=0°, θy =0°
Viewing angle
at normal direction
- 5.5 10 ms Note (3)
- - 1.3 - Note (6)
Typ.
-0.03
0.290
68 72 - % NTSC
Typ.
+0.03
cd/m
2
-
Note (4)
-
θx+
Horizontal
Viewing
Angle
Vertical
Note (1) Definition of Viewing Angle (θx, θy) :
Viewing angles are measured by Conoscope Cono-80
Note (2) Definition of Contrast Ratio (CR) :
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
θx-
θY+
θY-
CR≥20
30
80 88 -
80 88 -
80 88 -
80 88 -
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
Deg. Note (1)
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Note (3) Definition of Gray-to-Gray Switching Time:
Optical Response
100 %
90 %
10 %
0 %
Gray to Gray
Switching Time
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Switching Time
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Time
The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892 and 1023.
Gray to gray average time means the average switching time of gray level 0, 124, 252, 380, 508, 636, 764,
892 and 1023. to each other.
Note (4) Definition of Luminance of White (L
Measure the luminance of gray level 255 at center point and 5 points
L
= L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
C
Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA × 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
, L
):
C
AVE
Note (6) Definition of White Variation (δW):
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Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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W
Vertical Line
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The dust
and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
кat normal humidity without
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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Issue Date : Apr.06.2010
Model No.: V420H2-LH3
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Model Name: V420H2-LH3
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
CHI MEI
OPTOELECTRONICS
CHI MEI
OPTOELECTRONICS
V420H2 –LH3 Rev. XX
X X X X X X X Y M D L N N N N
V420H2 –LH3 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
E207943
MADE IN TAIWAN
GEMN
RoHS
MADE IN CHINA
LEOO(or CAPG or C ANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year : 2001=1, 2002=2, 2003=3, 2004=4…2010=0, 2011=1, 2012=2…
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Revision Code : Cover all the change
Serial No. : Manufacturing sequence of product
Product Line : 1
Ш Line1, 2 Ш Line 2, …etc.
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
(1) 4 LCD TV modules / 1 Box
(2) Box dimensions : 1085(L)x296(W)x653(H)mm
(3) Weight : Approx. 53.17Kg(4 modules per carton)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method
LCD TV Module
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Anti-Static Bag
Cushion(Bottom)
Carton
Cushion(Top)
PP Belt
Carton Label
Figure 10-1 packing method
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Sea / Land Transportation
(40ft Container)
Air Transportation
Figure 10-2 packing method
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11. MECHANICAL CHARACTERISTIC
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CHI MEI
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CHI MEI
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Appendix – TWO Wire BUS INTRODUCTION
A.1 PIN ASSIGNMENT
51pins LVDS connector
Pin8: SCL
Pin9: SDA
A.2 I2C BUS APPLICATION NOTE
I2C bus: (The I2C bus must for MEMC only or prevent the I2C bus voltage drop down in initial state)
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A.3 TWO WIRE BUS DEVICE ADDRESS
Two wire device address: default is 0x40, 1 byte
Two wire command: the range is 0x00 to 0xFF, 1 byte, see the two wire command table.
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Two wire bus format:
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A.4 TWO WAY TO CONTROL THE TWO WIRE BUS
There are two options to control the two wires bus command.
Two wire bus 6 bytes format
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Two wire bus 3 bytes format
Note :
A transmission basically consists of a START condition, a SLA+R/W, one or more data packets and a STOP
condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the
wired-ANDing of the SCL line can be used to implement handshaking between the master and the slave. The slave
can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the master is too
fast for the slave, or the slave needs extra time for processing between the data transmissions. The slave extending the
SCL low period will not affect the SCL high period, which is determined by the master. As a consequence, the slave
can reduce the TWI data transfer speed by prolonging the SCL duty cycle.
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A.5 TWO WIRE BUS COMMAND TABLE
There is two wire bus command table.
Command Name
All OSD Protection 0x00 R/W OSDx Enable Flag Contorl
OSD1_Start_Protection 0x01 R/W OSD1 Protection Start Position
OSD2_Start_Protection 0x02 R/W OSD2 Protection Start Position
OSD3_Start_Protection 0x03 R/W OSD3 Protection Start Position
OSD4_Start_Protection 0x04 R/W OSD4 Protection Start Position
OSD1_End_Protection 0x05 R/W OSD1 Protection End Position
OSD2_End_Protection 0x06 R/W OSD2 Protection End Position
OSD3_End_Protection 0x07 R/W OSD3 Protection End Position
OSD4_End_Protection 0x08 R/W OSD4 Protection End Position
Demo Window 0x09 R/W ME Performance Demo
MEMC Level 0x0A R/W ME Performance
GV Mode 0x0B R/W ME Operation
Blanking 0x0C R/W Blinking the screen
RPF 0x0D R/W Rotation picture function
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Access
Mode
Description
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Enable All OSD Protection
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OSD # 1~4 Start Protection
OSD # 1~4 End Protection
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Demo Window
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MEMC Level
GV Mode
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Blanking (Enable/Disable)
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Rotation Panel Function
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A.6 TWO WIRE BUS REQUIREMENT
Symbol Parameter Condition Min Max Unit
V
L
V
H
t
r
t
cf
I
i
C
i
f
SCL
R
P
t
HDSTA
t
LOW
t
HIGH
t
SU ST A
t
HDDAT
t
SUDAT
t
SU ST O
t
QLF
Input Low-voltage
Inp ut High-voltage
˃ ˃ˁˊ
˅ˁˊ ˆˁˆ
Rise Time for both SDA and SCL 20 + 0.1C
Output Fall Time from V
Input Current each I/O Pin 0.1VCC < Vi < 0.9V
IHmin
to V
ILmax
10 pF < Cb < 400 pF 20 + 0.1C
CC
ˀ˄˃ ˄˃
Capacitance for each I/O Pin NA
SCL Clock Frequency
Value of Pull-up resistor f
Hold Time (repeated) STAR Condition f
Low Period of the SCL Clock f
High Period of the SCL Clock f
Set-up time for a repeated STAR Condition f
Data hold time f
Data setup time f
Setup time for STOP Condition f
Bus free time between a STOP and START Condition f
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
Љ 50KHz
SCL
ˇˈ˃
ˆ˃˃˃
ˇ
ˇˁˊ
ˇ
ˇˁˊ
˃ ˆˁˇˈ
˅ˈ˃
ˇ
ˇˁˊ
ˆ˃˃
b
˅ˈ˃
b
˄˃
1000ns/C
NA us
NA us
NA us
NA us
NA ns
NA us
NA us
b
V
V
ns
ns
uA
pF
KHz
Ө
us
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A.7 THE TWO WIRE BUS SEQUENCE
I. Initial state
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II. Stable state
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