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TFT LCD Tentative Specification
MODEL NO.: V420H2 – LH3
Customer: _________________________________
Approved by:_______________________________
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Note:
TV Head Division
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-Nan Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
CY Chang Ben Wai
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CONTENTS
REVISION HISTORY ..................................................................................................................................................4
1. GENERAL DESCRIPTION......................................................................................................................................5
1.1 OVERVIEW....................................................................................................................................................5
1.2 FEATURES ....................................................................................................................................................5
1.3 APPLICATION................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS ........................................................................................................................5
1.5 MECHANICAL SPECIFICATIONS ..................................................................................................................6
2. ABSOLUTE MAXIMUM RATINGS ...........................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT....................................................................................................7
2.2 PACKAGE STORAGE ....................................................................................................................................8
2.3 ELECTRICAL ABSOLUTE RATINGS..............................................................................................................8
2.3.1 TFT LCD MODULE...............................................................................................................................8
2.3.2 BACKLIGHT INVERTER UNIT .............................................................................................................8
3. ELECTRICAL CHARACTERISTICS........................................................................................................................9
3.1 TFT LCD MODULE.........................................................................................................................................9
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION.....................................................................................12
3.2.1 LAMP SPECIFICATION......................................................................................................................12
3.2.2 ELECTRICAL SPECIFICATION.......................................................................................................... 12
3.2.3 INVERTER INTERFACE CHARACTERISTICS...................................................................................14
4. BLOCK DIAGRAM OF INTERFACE ...................................................................................................................... 16
4.1 TFT LCD MODULE.......................................................................................................................................16
5. INPUT TERMINAL PIN ASSIGNMENT..................................................................................................................17
5.1 TFT LCD Module Input .................................................................................................................................17
5.2 BACKLIGHT UNIT........................................................................................................................................ 20
5.3 INVERTER UNIT..........................................................................................................................................20
5.4 BLOCK DIAGRAM OF INTERFACE .............................................................................................................22
5.5 LVDS INTERFACE .......................................................................................................................................24
5.6 COLOR DATA INPUT ASSIGNMENT............................................................................................................25
6. INTERFACE TIMING............................................................................................................................................. 26
6.1 INPUT SIGNAL TIMING SPECIFICATIONS..................................................................................................26
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7. OPTICAL CHARACTERISTICS.............................................................................................................................29
7.1 TEST CONDITIONS ..................................................................................................................................... 29
7.2 OPTICAL SPECIFICATIONS........................................................................................................................30
8. PRECAUTIONS ....................................................................................................................................................33
8.1 ASSEMBLY AND HANDLING PRECAUTIONS .............................................................................................33
8.2 SAFETY PRECAUTIONS .............................................................................................................................33
9. DEFINITION OF LABELS......................................................................................................................................34
9.1 CMO MODULE LABEL.................................................................................................................................34
10. PACKAGING ....................................................................................................................................................... 35
10.1 PACKAGING SPECIFICATIONS.................................................................................................................35
10.2 PACKAGING METHOD .............................................................................................................................. 35
11. MECHANICAL CHARACTERISTIC......................................................................................................................37
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REVISION HISTORY
Version Date Page(New) Section Description
Ver. 0.0 Oct. 02, 2009 All All The tentative specification was first issued.
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H2-L01 is a 42” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit/color). The inverter
module for backlight is built-in.
1.2 FEATURES
Ё
High brightness (450 nits)
Ё
High contrast ratio (5000:1)
Ё
Fast response time (Gray to gray average 6.5 ms)
Ё
High color saturation (NTSC 72%)
Ё
Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё
DE (Data Enable) only mode
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Ё
LVDS (Low Voltage Differential Signaling) interface
Ё
Optimized response time for 120 Hz frame rate
Ё
Ultra wide viewing angle : Super MVA technology
Ё
RoHS compliance
1.3 APPLICATION
Ё
Standard Living Room TVs.
Ё
Public Display Application.
Ё
Home Theater Application.
Ё
MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 930.24(H) x 523.26 (V) (42.02” diagonal) mm
Bezel Opening Area 939 (H) x 531 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
(1)
Pixel Pitch(Sub Pixel) 0.1615 (H) x 0.4845 (V) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment Anti-Glare coating (Haze 11%) - (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 982.0 983.0 984.0 mm
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Vertical (V) 575.0 576.0 577.0 mm Module Size
Depth (D) 46.1 47.1 48.1 mm
Weight - (9600) - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
(1), (2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
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Value
Unit Note
Min. Max.
(a) 90 %RH Max. (Ta
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
Љ
40 ºC).
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
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store the module with temperature from 0 to 35
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
к
at normal humidity without condensation.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Value
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT INVERTER UNIT
Item Symbol
Lamp Voltage VW
Min. Max.
Value
Min. Max.
Ё
3000 VRMS
Unit Note
(1)
Unit Note
Power Supply Voltage VBL 0 30 V (1)
Ё
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
-0.3 7 V (1), (3)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Rush Current I
White Pattern
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Min. Typ. Max.
Ё
Ё
RUSH
Ё
Value
Ё
1.7
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Unit Note
3.5 A (2)
Ё
A
Power Supply Current
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
Common Input Voltage VCM 1.0 1.25 2 V
Differential input voltage |VID| 100
Terminating Resistor R
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
Horizontal Stripe
Black Pattern
Ё
Ё
V
LVT H
V
LVTL
T
0
IL
Ё
Ё
+100
Ё
Ё
2 2.4 A
0.8
Ё
Ё
Ё
100
Ё
Ё
(3)
Ё
Ё
-100 mV
600 mV
Ё
3.3 V
0.7 V
A
mV
(4)
ohm
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GND
Vcc rising time is 470us
0.9Vcc
0.1Vcc
470us
Vcc
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
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= 60 Hz,
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a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
Issue Date:Oct.02.2009
Model No.: V420H2-LH3
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Value
Unit Note
Lamp Input Voltage VL - (1090) -
Lamp Current IL
Lamp Turn On Voltage VS
Operating Frequency FL 35 - 70
Lamp Life Time LBL 50,000 - -
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Consumption PBL
(9.7) (10.2) (10.7) A_dim=HI
8.2 8.7 9.2
- - (1910)
- - (1560)
Value
Min. Typ. Max.
- 130
- 110
˄ˆˋ
˄˄ˋ
Lamp Input
Voltage
Lamp
Current
Lamp Turn
On Voltage
Operating
Frequency
Lamp Life
Time
Unit Note
(5),(6) IL = 10.2 mA
W
(5),(6) IL = 8.7 mA
VL
A_dim=LO
VS
FL
LBL
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
ˈˁˊˈ
ˇˁˌ
A Non Dimming
ʻˆʼ
- 5.4
Power Supply Current IBL
4.6
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 39 42 45 kHz
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio D
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
- 20 - %
MIN
should be applied to the lamp for more than 1 second after startup.
S
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as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
±2
к
and IL = (8.2~ 10.7)mArms.
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Note (5) The power supply capacity should be higher than the total inverter power consumption P
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 42" backlight unit under input voltage 24V,
average lamp current
ˌˁ˃ʳmAʳ˴˷ʳ˄˃ˁˈʳ
mA and lighting 30 minutes later.
. Since
BL
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3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Parameter Symbol
ON
On/Off Control Voltage
V
BLON
OFF
Internal PWM Control
Voltage
MAX
MIN
V
IPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time T
PW MR
Condition
Te st
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Ё
Value
Unit Note
Min. Typ. Max.
2.0
Ё
5.0 V
0
3.0 3.15 3.3 V Max. Duty Ratio
Ё
3.0 3.3 3.6 V Normal
0
30
30
Ё
Ё
Ё
Ё
0.8 V
0
Ё
Ё
Ё
Ё
Ё
Ё
Ё
V Min. Duty Ratio
0.8 V Abnormal
Ё
ms
10%-90%V
Ё
100 ms
100 ms
50 us
ms
BL
PWM Signal Falling Time T
PW MF
Input Impedance RIN
PWM Delay Time
BLON Delay Time
BLON Off Time
T
PW M
T
T
on
on1
Ё
Ё
Ё
Ё
Ё
1
100
300
300
Ё
50 us
Ё
Ё
MΩ
Ё
Ё
ms
Ё
Ё
ms
Ё
Ё
ms
Ё
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
Ш
PWM signal Ш BLON
Ш
PWM signal Ш VBL
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ODD_RIN0+/-
FRAME
ODD_RIN1+/-
ODD_RIN2+/-
ODD_RIN3+/-
ODD_RIN4+/-
ODD_CLK+/-
MEN
MCFG 0
(FI-RE51S-HF (JAE)) or equivalent
INPUT CONNECTOR
BUFFER
MEMC
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TIMING
CONTROLLER
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SCAN DRIVER
TFT LCD PANEL
(1920x3x1080)
MCFG 1
LVDS8b
VIN
GND
VBL
GND
Status
A_DIM
I_PWM
BLON
DC/DC CONVERTER
& REFERENCE VOLTAGE
INVERTER
CONNECTOR
CN1:S14B-PH-SM4-TB
(D)(LF) or equivalent
DATA DRIVER (RSDS
GENERATOR
CN2-CN7:SM02 (13.0)-BDAS-3-TB(LF)(JST) or equivalent
BACKLIGHT
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
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CNF1 Connector Part No.: JAE Taiwan (
Pin Name Description Note
1 GND Ground
2 MEN MEMC function selection 5
3 MCFG0 MEMC function selection 5
4 MCFG1 MEMC function selection 5
5 LVDS8b 8bit/10bit LVDS input selection 6
6 GV_mode Graphic / Video mode selection 7
7 SELLVDS LVDS data format Selection 3
8 SCL I2C CLK Signal
9 SDA. I2C Data Signal
10 ODSEL Overdrive Lookup Table Selection 4
11 GND Ground
12 ERX0- 2nd pixel Negative LVDS differential data input. Channel 0
13 ERX0+ 2nd pixel Positive LVDS differential data input. Channel 0
14 ERX1- 2nd pixel Negative LVDS differential data input. Channel 1
15 ERX1+ 2nd pixel Positive LVDS differential data input. Channel 1
16 ERX2- 2nd pixel Negative LVDS differential data input. Channel 2
17 ERX2+ 2nd pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ECLK- 2nd pixel Negative LVDS differential clock input.
20 ECLK+ 2nd pixel Positive LVDS differential clock input.
21 GND Ground
22 ERX3- 2nd pixel Negative LVDS differential data input. Channel 3
23 ERX3+ 2nd pixel Positive LVDS differential data input. Channel 3
24 ERX4- 2nd pixel Negative LVDS differential data input. Channel 4 ʳ
25 ERX4+ 2nd pixel Positive LVDS differential data input. Channel 4
26 N.C. No Connection 2
27 N.C. No Connection 2
28 ORX0- 1st pixel Negative LVDS differential data input. Channel 0
29 ORX0+ 1st pixel Positive LVDS differential data input. Channel 0
30 ORX1- 1st pixel Negative LVDS differential data input. Channel 1
31 ORX1+ 1st pixel Positive LVDS differential data input. Channel 1
32 ORX2- 1st pixel Negative LVDS differential data input. Channel 2
33 ORX2+ 1st pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- 1st pixel Negative LVDS differential clock input.
36 OCLK+ 1st pixel Positive LVDS differential clock input.
37 GND Ground
38 ORX3- 1st pixel Negative LVDS differential data input. Channel 3
39 ORX3+ 1st pixel Positive LVDS differential data input. Channel 3
40 ORX4- 1st pixel Negative LVDS differential data input. Channel 4
ሽ
) FI-RE51S-HF or equivalent.
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
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41 ORX4+ 1st pixel Positive LVDS differential data input. Channel 4
42 N.C. No Connection 2
43 N.C. No Connection 2
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection 2
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
Note (1) LVDS connector pin orderdefined as follows
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ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
ʳ
Note (2) Reserved for internal use. Please leave it open.
Note (3)
SELLVDS Mode
L(default)
H JEIDA
VESA
L: Connect to GND, H: Connect to +3.3V
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
frame rate to optimize image quality.
ODSEL Description
L(default)
H Lookup table was optimized for 50 Hz frame rate input.
L: Connect to GND, H: Connect to +3.3V
Lookup table was optimized for 60 Hz frame rate input.
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Note (5) Motion Engine (ME) Level & Demo Function Table
Motion engine level must be adjusted after video mode is selected (or entered).
Adjusting the motion engine level in graphic mode has no effect
MEN MCFG1 MCFG0 Notes
Blanking disable
Blanking
Demo mode (d)
ME
Level
(a) Module re-starts processing video signals from Frontend scaler control board.
Auto blanking
Blanking enable
Strong
Medium(Default)
Weak
OFF
(e) (f) (g)
0 0 0
0 0 1
0 1 0
0 1 1 Demo Window
1 0 0 Enable Strong Strong
1 0 1 Enable Normal Normal
1 1 0 Enable × ×
1 1 1 × × ×
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(a)
(b)
(c)
(b) During sync unstable period such as format change, 60Hz <-> 50Hz .
MCFG0 can be used to insert blanking of 500ms. This signal is toggled.
(c) Module continues to insert blanking until blanking disable signal is received from frontend scaler board.
(d) Demo window mode: Demo Window appears to the left half of display area. Left side with frame is 120Hz
with MEMC, and right side is 120Hz w/o motion compensation.
(e) GPIO (General Purpose I/O) sequence of ME Level: (1) MEN; (2) MCFG1; (3) MCFG0.
GPIO sequence of Blanking Enable, Blanking Disable and Demo window: (1) MCFG1; (2) MCFG0; (3)
MEN.
(f) Each scaler command must be maintained the same voltage level at least 100ms.
(g) 0 : Connect to GND, 1 : +3.3V
Note (6) 8bit/10bit LVDS input selection
LVDS8b Bit depth
H(default)
L
L : Connect to GND, H : Connect to +3.3V
10bit
8bit
ʳ
ʳ
Note (7) Graphic / Video mode selection
There is no prohibited time period for switching between Graphic mode and Video mode.
When this switching signal is input, LCD will be reset and will re-start selected mode.
GV_mode Mode select MEMC ON/OFF
H(default)
L
L : Connect to GND, H : Connect to +3.3V
Graphic mode MEMC OFF
Video mode MEMC ON
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color
1 HV High Voltage White
2 HV High Voltage Pink
1 HV(White)
2 HV(Pink)
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1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin № Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 STATUS
12 A_DIM
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
Amplitude Dimming Control
HI (2.0V ~ 5.0V)
LO(0V~0.8V)
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CN2-CN7: SM02 -BDAS-3-TB(JST) or equivalent
Pin No. Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
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5.4 BLOCK DIAGRAM OF INTERFACE
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Model No.: V420H2-LH3
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ARx0 +
ARx0 -
ARx1 +
ARx1 -
ARx2 +
ARx2 -
ARx3 +
ARx3 -
ARx4 +
ARx4 -
ACLK +
ACLK -
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
100pF
100pF
PLL
RxOUT
– AR9
AR0
– AG9
AG0
– AB9
AB0
DE
BRx0 +
BRx0 -
BRx1 +
BRx1 -
BRx2 +
BRx2 -
BRx3 +
BRx3 -
BRx4 +
BRx4 -
BCLK +
BCLK -
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
100pF
100pF
PLL
– BR9
BR0
– BG9
BG0
– BB9
BB0
DCLK
DCLK
Timing
Controller
LVDS Receiver
(MASTER)
LVDS INPUT
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
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Model No.: V420H2-LH3
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is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Model No.: V420H2-LH3
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Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV
24
DE
REV
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus
data input.
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (253)
Blue (254)
Blue (255)
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
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Data Signal
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
:
:
:
:
:
:
:
:
1
1
0
1
1
1
0
1
1
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
F
(=1/TC)
clkin_mod
F
F
LVDS
Receiver
Clock
LVDS
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Setup Time Tlvsu 600
Receiver
Data
Hold Time Tlvhd 600
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clkin
T
rcl
30
SSM
60 74.25 78 MHz
Ё
F
-2%
clkin
Ё
Ё
Ё
Ё
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Model No.: V420H2-LH3
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200 ps (2)
F
+2% MHz
clkin
(3)
50 KHz
Ё
ps
Ё
ps
Frame Rate
Fr5 47 50 53 Hz
57 60 62 Hz
F
Vertical
Active
Display
Term
Total Tv 1110 1125 1135 Th
Display Tvd 1080 1080 1080 Th
r6
Blank Tvb 30 45 55 Th
Horizontal
Active
Display
Term
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
Note (1)
ˣ˿˸˴˸ʳ˴˾˸ʳ˸ʳ˻˸ʳ˴˺˸ʳ˹ʳ˹˴˸ʳ˴˸ʳ˻˴ʳ˹˿˿ʳ˻˸ʳ˵˸˿ʳ˸˴˼Κʳ ʳ ʳ
˙ʻ˴ʼʳ Њʳ ˙˶˿˾˼ʳ Яʳ ˧˧˻ʳ Љʳ ˙ʻ˼ʼʳ
Note (2) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Tv=Tvd+T vb
Th=Thd+Thb
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Note (3) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Model No.: V420H2-LH3
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
10ms
50ms
50ms
ЉЉЉЉ
T4
0V
0.5
ЉЉЉЉ
T
1
ЉЉЉЉ
0
ЉЉЉЉ
T
2
ЉЉЉЉ
ЉЉЉЉ
T
3
0
500ms
ЉЉЉЉ
0.1V
CC
3
T1
T
T
2
0.1V
T4
cc
LVDS Signals
0V
Power On
VALI D
Power Off
0
ЉЉЉЉ
T
7
ЉЉЉЉ
ЉЉЉЉ
T8
T2
T7
8
T
0
Option Signals
(SELLVDS,GPIO setting..…)
Backlight (Recommended)
ЉЉЉЉ
1000ms
100ms
T5
ЉЉЉЉ
T
6
50%
5
T
50%
6
T
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Note:
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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Power ON/OFF Sequence
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Model No.: V420H2-LH3
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL (10.2) mA
Oscillating Frequency (Inverter) FW TBD KHz
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
25±2
50±10
oC
%RH
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR TBD (5000) - - Note (2)
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Response Time
Center Luminance of White LC TBD (450) - cd/m2Note (4)
White Variation
Cross Talk CT - - (4) % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Color Gamut C.G
Gray to
gray
δW
Rx (0.636) -
Ry (0.323) -
Gx (0.292) -
Gy (0.600) -
Bx (0.147) -
By (0.052) -
Wx (0.280) -
Wy
θx=0°, θy =0°
Viewing angle
at normal direction
- (4.5) TBD ms Note (3)
- - (1.3) - Note (6)
Typ.
-0.03
(0.285)
(68) (72) - % NTSC
Typ.
+0.03
-
-
θx+
Horizontal
θx-
Viewing Angle
θY+
Vertical
θY-
Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Conoscope Cono-80
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
CR≥20
80 88 -
80 88 -
80 88 -
80 88 -
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
Deg. Note (1)
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Note (3) Definition of Gray-to-Gray Switching Time:
Optical Response
100 %
90 %
10 %
0 %
Gray to Gray
Switching Time
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Gray to Gray
Switching Time
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Time
The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892 and 1023.
Gray to gray average time means the average switching time of gray level 0, 124, 252, 380, 508, 636,
764, 892 and 1023. to each other.
Note (4) Definition of Luminance of White (L
Measure the luminance of gray level 255 at center point and 5 points
= L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
L
C
Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
×
100 (%)
, L
):
C
AVE
δ
Note (6) Definition of White Variation (
Measure the luminance of gray level 255 at 5 points
δ
W = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
W):
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
к
recommended to store the module with temperature from 0 to 35
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
at normal humidity without
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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Issue Date:Oct.02.2009
Model No.: V420H2-LH3
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CHI MEI
OPTOELECTRONICS
Model Name: V420H2-L01
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
CHI MEI
OPTOELECTRONICS
V420H2 –LH3 Rev. XX
V420H2 –LH3 Rev. XX
Serial No.
Product Line
E207943
MADE IN TAIWAN
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
(1) 4 LCD TV modules / 1 Box
(2) Box dimensions : 1085(L)x296(W)x653(H)mm
(3) Weight : Approx. 53.17Kg(4 modules per carton)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method
LCD TV Module
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Issue Date:Oct.02.2009
Model No.: V420H2-LH3
Ten tati ve
Anti-Static Bag
Cushion(Bottom)
Carton
Cushion(Top)
PP Belt
Carton Label
Figure.10-1 packing method
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(40ft Container)
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Issue Date:Oct.02.2009
Model No.: V420H2-LH3
Ten tati ve
Air TransportationSea / Land Transportation
Figure.10-2 packing method
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Global LCD Panel Exchange Center
11. MECHANICAL CHARACTERISTIC
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Issue Date:Oct.02.2009
Model No.: V420H2-LH3
Ten tati ve
ڻႝηިҽԖ Ϧљ
CHI MEI
37
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Global LCD Panel Exchange Center
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Issue Date:Oct.02.2009
Model No.: V420H2-LH3
Ten tati ve
ڻႝηިҽԖϦљ
CHI MEI
38
Version 0. 0
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
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