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TFT LCD Tentaive Specification
MODEL NO.: V420H2 – L01
Customer: _________________________________
Approved by:_______________________________
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Note:
TV Head Division
Approved By
Chao-Chun Chung
Reviewed By
QA Dept. Product Development Div.
Hsin-Nan Chen WT Lin
Version 0.0
Prepared By
LCD TV Marketing and Product Management Div.
CY Chang Justin wang
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Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
CONTENTS
REVISION HISTORY.........................................................................................................................................................4
1. GENERAL DESCRIPTION............................................................................................................................................ 5
1.1 OVERVIEW ..........................................................................................................................................................5
1.2 FEATURES...........................................................................................................................................................5
1.3 APPLICATION ...................................................................................................................................................... 5
1.4 GENERAL SPECIFICATIONS .............................................................................................................................5
1.5 MECHANICAL SPECIFICATIONS ....................................................................................................................... 6
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT........................................................................................................7
2.2 PACKAGE STORAGE..........................................................................................................................................8
2.3 ELECTRICAL ABSOLUTE RATINGS ..................................................................................................................8
2.3.1 TFT LCD MODULE ....................................................................................................................................8
2.3.2 BACKLIGHT INVERTER UNIT..................................................................................................................8
3. ELECTRICAL CHARACTERISTICS .............................................................................................................................9
3.1 TFT LCD MODULE ............................................................................................................錯誤! 尚未定義書籤。
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION.......................................................................................122
3.2.1 LAMP SPECIFICATION .........................................................................................................................122
3.2.2 ELECTRICAL SPECIFICATION............................................................................................................. 122
3.2.3 INVERTER INTERFACE
CHARACTERISTICS………………………………………………………………144
4. BLOCK DIAGRAM OF INTERFACE .........................................................................................................................166
4.1 TFT LCD MODULE ..........................................................................................................................................166
5. INPUT TERMINAL PIN ASSIGNMENT.....................................................................................................................177
5.1 TFT LCD Module Input.....................................................................................................................................177
5.2 BACKLIGHT UNIT..............................................................................................................................................20
5.3 INVERTER UNIT................................................................................................................................................20
5.4 BLOCK DIAGRAM OF INTERFACE..................................................................................................................22
5.5 LVDS INTERFACE.............................................................................................................................................24
5.6 COLOR DATA INPUT ASSIGNMENT ................................................................................................................25
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Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
6. INTERFACE TIMING...................................................................................................................................................26
6.1 INPUT SIGNAL TIMING SPECIFICATIONS......................................................................................................26
6.2 POWER ON/OFF SEQUENCE.......................................................................................................................... 29
7. OPTICAL CHARACTERISTICS ..................................................................................................................................30
7.1 TEST CONDITIONS...........................................................................................................................................30
7.2 OPTICAL SPECIFICATIONS .............................................................................................................................31
8. PRECAUTIONS...........................................................................................................................................................34
8.1 ASSEMBLY AND HANDLING PRECAUTIONS .................................................................................................34
8.2 SAFETY PRECAUTIONS ..................................................................................................................................34
9. DEFINITION OF LABELS............................................................................................................................................35
9.1 CMO MODULE LABEL ......................................................................................................................................35
10. PACKAGING..............................................................................................................................................................36
10.1 PACKAGING SPECIFICATIONS .....................................................................................................................36
10.2 PACKAGING METHOD....................................................................................................................................36
11. MECHANICAL CHARACTERISTICS ........................................................................................................................38
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REVISION HISTORY
Version Date Page(New) Section Description
Ver. 0.0 Sep. 29, 2009 All All The tentative specification was first issued.
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H2-L01 is a 42” TFT Liquid Crystal Display module with 12-CCFL Backlight unit and 2ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display 16.7M colors (8-bit/color). The inverter
module for backlight is built-in.
1.2 FEATURES
－ High brightness (450 nits)
－ High contrast ratio (5000:1)
－ Fast response time (Gray to gray average 6.5 ms)
－ High color saturation (NTSC 72%)
－ Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
－ DE (Data Enable) only mode
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
－ LVDS (Low Voltage Differential Signaling) interface
－ Optimized response time for 60 Hz frame rate
－ Ultra wide viewing angle : Super MVA technology
－ RoHS compliance
1.3 APPLICA TION
－ Standard Living Room TVs.
－ Public Display Application.
－ Home Theater Application.
－ MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 930.24(H) x 523.26 (V) (42.02” diagonal) mm
Bezel Opening Area 939 (H) x 531 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
(1)
Pixel Pitch(Sub Pixel) 0.1615 (H) x 0.4845 (V) mm -
Pixel Arrangement RGB vertical stripe - -
Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment Anti-Glare coating (Haze 11%) - (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 982.0 983.0 984.0 mm
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Module Size
Weight - (9500) - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Vertical (V) 575.0 576.0 577.0 mm
Depth (D) 48.5 49.5 50.5 mm
(1), (2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta ≦ 40 ºC).
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Value
Unit Note
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 ℃ at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Value
Unit Note
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT INVERTER UNIT
Value
Item Symbol
Min. Max.
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
－
－
-0.3 7 V (1), (3)
3000 VRMS
Unit Note
(1)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Supply Current
Differential Input High
Threshold Voltage
Differential Input Low
Threshold Voltage
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage |VID| 200
Terminating Resistor R
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
Horizontal Stripe
Black Pattern
RUSH
－ －
－ －
－ －
V
LVT H
V
LVT L
T
0
IL
+100
－ －
0.98
0.98 1.2 A
0.51
－ －
－ －
－
－
100
－
－
3.5 A (2)
－
－
-100 mV
600 mV
－
3.3 V
0.7 V
A
(3)
A
mV
(4)
ohm
Note (2) Measurement condition:
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Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Vcc
(LCD Module Input)
C3
1uF
(Low to High)
Control Signal
SW
+12V
Q1 Si4485DY
Fuse
R1
1k
VR1
47k
C1
0.01uF
R2
Q2
2N7002
1k
Vcc rising time is 470us
Vcc
GND
0.1Vcc
0.9Vcc
470us
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
whereas a power dissipation check pattern below is displayed.
= 60 Hz,
v
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a. White Pattern
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
b. Black Pattern
Note (4) The LVDS input characteristics are as follows:
Active Area
Active Area
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Value
Unit Note
Lamp Input Voltage VL - (1090) -
Lamp Current IL 9.7 (10.2) 10.7
- - (1910)
Lamp Turn On Voltage VS
- - (1560)
Operating Frequency FL 35 - 70
Lamp Life Time LBL 50,000 - -
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Value
Parameter Symbol
Min. Typ. Max.
- 130
Power Consumption PBL
- 110
138
118
Lamp Input
Voltage
Lamp
Current
Lamp Turn
On Voltage
Operating
Frequency
Lamp Life
Time
Unit Note
(5),(6) IL = 10.2 mA
W
(5),(6) IL = 8.7 mA
VL
IL
VS
FL
LBL
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
- 5.4
Power Supply Current IBL
4.6
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 39 42 45 kHz
Dimming Frequency FB 150 160 170 Hz
Minimum Duty Ratio D
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
master and slave board.
Note (2) The lamp starting voltage V
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
- 20 - %
MIN
should be applied to the lamp for more than 1 second after startup.
S
5.75
A Non Dimming
4.9
(3)
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as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at
the center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
±2℃ and I
Note (5) The power supply capacity should be higher than the total inverter power consumption P
the pulse width modulation (PWM) mode was applied for backlight dimming, the driving current
changed as PWM duty on and off. The transient response of power supply should be considered
for the changing loading when inverter dimming.
Note (6) The measurement condition of Max. value is based on 42" backlight unit under input voltage 24V,
average lamp current 9.0 mA and 10.5 mA and lighting 30 minutes later.
= 8.2~ 10.7mArms.
L
. Since
BL
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3.2.3 INVERTER INTERFACE CHARACTERISTICS
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Parameter Symbol
ON
On/Off Control Voltage
V
BLON
OFF
Internal PWM Control
Voltage
MAX
MIN
V
IPWM
HI
Status Signal
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time T
PWMR
Condition
Te st
Value
Min. Typ. Max.
－
－
－
2.0
0
3.0 3.15 3.3 V Max. Duty Ratio
－ －
－
－
－
－
3.0 3.3 3.6 V Normal
0
30
30
－ － －
－ － －
－ － －
－
－
0
－
－
－
Unit Note
5.0 V
0.8 V
－
V Min. Duty Ratio
0.8 V Abnormal
－
－
100 ms
100 ms
50 us
ms
ms
10%-90%V
BL
PWM Signal Falling Time T
PWMF
Input Impedance RIN
PWM Delay Time
BLON Delay Time
BLON Off Time
T
T
PWM
T
on1
on
－ － －
－
－
－
－
1
100
300
300
－ －
－ －
－ －
－ －
50 us
MΩ
ms
ms
ms
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure. For a certain
reason, the inverter has a possibility to be damaged with wrong power sequence and control
signal timing.
Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:
Turn ON sequence: VBL
Turn OFF sequence: BLOFF
→ PWM signal → BLON
→ PWM signal → VBL
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Model No.: V420H2-L01
Tentative
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)
A
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
SELLVDS
ODSEL
(FI-RE51S-HF (JAE)) or equivalent
INPUT CONNECTOR
FRAME
BUFFER
TIMING
CONTROLLER
SCAN DRIVER
DATA DRIVER (RSDS
Issue Date:Sep.29.2009
Model No.: V420H2-L01
TFT LCD PANEL
(1920x3x1080)
Tentative
Vcc
GND
CN1
VBL
GND
Status
_DIM
I_PWM
BLON
DC/DC CONVERTER
CN11: 528520870 (Molex) or equivalent
CN2-CN7:SM02 (13.0)-BDAS-3-TB(LF)(JST) or equivalent
INVERTER
CONNECTOR
CN1:S14B-PH-SM4-TB
(D)(LF) or equivalent
& REFERENCE
VOLTAGE
GENERATOR
BACKLIGHT
UNIT
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
Pin Name Description Note
1 GND Ground
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (3)(5)
N.C. No Connection
8
9 ODSEL
10 N.C. No Connection (2)
11 N.C. No Connection (2)
12 ERX0- Even pixel Negative LVDS differential data input. Channel 0
13 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
14 ERX1- Even pixel Negative LVDS differential data input. Channel 1
15 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
16 ERX2- Even pixel Negative LVDS differential data input. Channel 2
17 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ECLK- Even pixel Negative LVDS differential clock input
20 ECLK+ Even pixel Positive LVDS differential clock input
21 GND Ground
22 ERX3- Even pixel Negative LVDS differential data input. Channel 3
23 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
26 N.C. No Connection
27 N.C. No Connection
28 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
29 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
30 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
31 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
32 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
33 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 OCLK- Odd pixel Negative LVDS differential clock input.
36 OCLK+ Odd pixel Positive LVDS differential clock input.
37 GND Ground
38 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
39 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
40 N.C. No Connection
41 N.C. No Connection
42 N.C. No Connection
43 N.C. No Connection
44 GND Ground
45 GND Ground
46 GND Ground
47 GND Ground
Overdrive Lookup Table Selection
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
(2)
(2)
(4)(6)
(2)
(2)
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y
g
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
Note (1) LVDS connector pin orderdefined as follows
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Note (2) Reserved for internal use. Please leave it open.
Note (3)
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
Low = Open or connect to GND, High = Connect to +3.3V
Note (5) LVDS signal pin connected to the LCM side has the following diagram.
Low = Open or connect to GND: VESA Format, High = Connect to +3.3V: JEIDA Format.
frame rate to optimize image quality.
ODSEL Note
L or open Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
R1
Selector (pin7)
R2
Settin
TCON
S
stem side
System side: R1 < 1K
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Note (6) ODSEL signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
Selector (pin9)
Selector (pin9)
System side
System side
R1
R1
R2
R2
R3
R3
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
TCON
TCON
Setting
Setting
LCM side
LCM side
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color
1 HV High Voltage White
2 HV High Voltage Pink
1 HV(White)
2 HV(Pink)
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin № Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 STATUS
12 A_DIM
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
CN2-CN7: SM02 -BDAS-3-TB(JST) or equivalent
Pin No. Symbol Description
1
2
VBL +24V
GND GND
CCFL HOT
CCFL HOT
CCFL high voltage
CCFL high voltage
Normal (3.3V)
Abnormal(GND)
Amplitude Dimming Control
HI (2.0V ~ 5.0V)
LO(0V~0.8V)
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CN8: 528520870 (Molex) or equivalent
Pin No. Symbol Description
1 Board to Board
2 Board to Board
3 Board to Board
4 Board to Board
5 Board to Board
6 Board to Board
7 Board to Board
8
Note (1) Floating of any control signal is not allowed.
Control
Signal
Board to Board
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
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OB0
OG0
C
OB0
OG0
p
O
ORx0
0
r
0
G0-EG
0
G0-EG
5.4 BLOCK DIAGRAM OF INTERFACE
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
ER0-ER7
E
EB
-EB7
DE
OR0-OR7
-OG7
-OB7
D
LK
Host
Graphics
Controller
7
TxIN
PLL
ERx0+
-
ERx
ERx1+
ERx1-
ERx2+
ERx2-
ERx3+
ERx3-
ECLK+
ORx0+
ORx1+
ORx1-
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
51Ω
100pF
100pF
100pF
100pF
RxOUT
ER0-ER7
E
EB
-EB7
DE
OR0-OR7
-OG7
7
-OB7
51Ω
-
100pF
51Ω
PLL
DCLK
Timing
51Ω
51Ω
51Ω
100pF
100
F
-
Controlle
ORx2+
ORx3+
ORx3-
OCLK+
PLL
LVDS Transmitter
Rx2-
51Ω
100pF
51Ω
51Ω
100pF
51Ω
51Ω
-
100pF
51Ω
LVDS Receiver
PLL
THC63LVDM83A
(LVDF83A)
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ER0~ER7: Even pixel R data
EG0~EG7: Even pixel G data
EB0~EB7: Even pixel B data
OR0~OR7: Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7: Odd pixel B data
DE: Data enable signal
DCLK: Data clock signal
Notes (1) The system must have the transmitter to drive the module.
Notes (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
is used differentially.
Notes (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and
the second pixel is even pixel.
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5.5 LVDS INTERFACE
VESA LVDS format：(SELLVDS pin=L)
RXCLK±
RXCLK±
Current cycle
Current cycle
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
ORX0±
ORX0±
ORX1±
ORX1±
ORX2±
ORX2±
ORX3±
ORX3±
ERX0±
ERX0±
ERX1±
ERX1±
ERX2±
ERX2±
ERX3±
ERX3±
JEDIA LVDS format：(SELLVDS pin=H)
G0
G0
G0
G0
R0R5 R4 R3 R2 R1
R0R5 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G6G7B7 B6RSVD
G6G7B7 B6RSVD
B0 G5B1
B0 G5B1
G6G7B7 B6RSVD
G6G7B7 B6RSVD
Current cycle
Current cycle
G1G3 G2G4
G1G3 G2G4
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6R7
R6R7
R0R5 R4 R3 R2 R1
R0R5 R4 R3 R2 R1
G1G3 G2G4
G1G3 G2G4
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6R7
R6R7
RXCLK±
RXCLK±
ORX0±
ORX0±
ORX1±
ORX1±
ORX2±
ORX2±
ORX3±
ORX3±
ERX0±
ERX0±
ERX1±
ERX1±
ERX2±
ERX2±
ERX3±
ERX3±
G2
G2
G2
G2
R2R7 R6 R5 R4 R3
R2R7 R6 R5 R4 R3
B2 G7B3
B2 G7B3
G0G1B1 B0RSVD
G0G1B1 B0RSVD
B2 G7B3
B2 G7B3
G0G1B1 B0RSVD
G0G1B1 B0RSVD
G3G5 G4G6
G3G5 G4G6
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0R1
R0R1
R2R7 R6 R5 R4 R3
R2R7 R6 R5 R4 R3
G3G5 G4G6
G3G5 G4G6
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0R1
R0R1
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R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the color.
The higher the binary input, the brighter the color. The table below provides the assignment of the color versus
data input.
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (253)
Blue (254)
Blue (255)
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Data Signal
Red Green Blue
0
0
0
0
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
0
1
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
0
0
0
0
0
0
0
0
1
0
0
1
:
:
1
0
0
1
1
1
0
0
0
0
0
0
:
:
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
F
(=1/TC)
clkin_mod
F
F
LVDS
Receiver
Clock
Frequency
Input cycle to
cycle jitter
Spread spectrum
modulation range
Spread spectrum
modulation frequency
Issue Date:Sep.29.2009
Model No.: V420H2-L01
clkin
T
rcl
200 KHz
SSM
60 74.25 80 MHz
－ －
F
-2%
clkin
－
200 ps (3)
F
+2% MHz
clkin
Tentative
(4)
LVDS
Receiver
Data
Setup Time Tlvsu 600
Hold Time Tlvhd 600
－ －
－ －
ps
(5)
ps
Fr5 47 50 53 Hz
(6)
Tv=Tvd+Tvb
－
－
Th=Thd+Thb
－
－
Vertical
Active
Display
Te rm
Horizontal
Active
Display
Te rm
Frame Rate
57 60 63 Hz
F
r6
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Th 1050 1100 1150 Tc
Display Thd 960 960 960 Tc
Blank Thb 90 140 190 Tc
Note (1) Please make sure the range of pixel clock has follow the below equation：
F
clkin(max) ≧ Fr6 ╳ Tv ╳ Th
Fr5 ╳ Tv ╳ Th ≧ Fclkin(min)
Note (2) This module is operated in DE only mode and please follow the input signal timing diagram below：
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Model No.: V420H2-L01
Tentative
T
vd
T
v
vb
T
DE
T
h
DCLK
T
c
hd
T
Thb
DE
DATA
Valid display data ( 960 clocks)
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
– TI
1
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
RXCLK+/-
RXn+/-
Tlvsu
Tlvhd
1T
14
LVDS RECEIVER INTERFACE TIMING DIAGRAM
Tc
3T
14
5T
14
7T
14
9T
14
11T
14
13T
14
Note (6) : (ODSEL) = H/L or open for 50/60Hz frame rate. Please refer to 5.1 for detail information
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
0.5≦T1≦10ms
0≦T
0≦T
500ms ≦T
2≦50ms
3≦50ms
0V
4
0.1V
CC
3 T1
T
2
T
0.1V
cc
T4
VALID
LVDS Signals
0V
Power On
Power Off
0≦T7≦T2
0≦T
8≦T3
T
7
T
8
Option Signals
(SELLVDS,OD_SEL)
Backlight (Recommended)
500ms≦T
100ms≦T6
5
50%
T
5
50%
T
6
Power ON/OFF Sequence
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL TBD mA
Oscillating Frequency (Inverter) FW TBD KHz
Vertical Frame Rate Fr 60 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
M
LCD
odule
anel
P
CS
2000
-
LCD
25±2
50±10
oC
%RH
Field of View = 1º
mm500
Light Shield Room
Ambient
uminance < 2
L
x)
lu(
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR TBD (5000) - - Note (2)
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Response Time
Center Luminance of White LC TBD (450) - cd/m2Note (4)
White Variation
Cross Talk CT - - (4) % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Color Gamut C.G
Gray to
gray
δW
Rx (0.636) -
Ry (0.323) -
Gx (0.292) -
Gy (0.600) -
Bx (0.147) -
By (0.052) -
Wx (0.280) -
Wy
θx=0°, θy =0°
Viewing angle
at normal direction
- (6.5) (12) ms Note (3)
- - (1.3) - Note (6)
Typ.
-0.03
(0.285)
(68) (72) - % NTSC
Typ.
+0.03
-
-
θx+
Horizontal
θx-
Viewing Angle
θY+
Vertical
θY-
Note (1) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Conoscope Cono-80
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).
CR≥20
80 88 -
80 88 -
80 88 -
80 88 -
pixels whiteall withLuminance Surface
pixels black all withLuminance Surface
Deg. Note (1)
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Note (3) Definition of Gray-to-Gray Switching Time:
Optical R esp o n se
100 %
90 %
10 %
0 %
Gray to Gray
Switching Time
Gray to Gray
Switching Time
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Time
The driving signal means the signal of gray level 0, 31, 63, 95, 127, 159, 191, 223 and 255.
Gray to gray average time means the average switching time of gray level 0, 31, 63, 95, 127, 159, 191,
223 and 255 to each other.
Note (4) Definition of Luminance of White (L
Measure the luminance of gray level 255 at center point and 5 points
L
= L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).
C
Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA × 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
(0,0)
Active Area
Y
A,U
(D/2,W/8)
, L
):
C
AVE
(0,0)
Active Area
(D/4,W/4)
Y
B,U
(D/2,W/8)
Gray 512
(D/8,W/2) Y
Y
A,L
Y
A,D
A,R
(D/2,7W/8)
(7D/8,W/2)
Y
(D/8,W/2) Y
B,L
Gray 0
Gray 128
Y
(D/2,7W/8)
B,D
B,R
Note (6) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Model No.: V420H2-L01
Tentative
Horizontal Line
D
D
4
1 2
W
4
W
W
2
Vertical Line
3W
4
3 4
5
D
3D
2
4
X
Test point :
X = 1 ~ 5
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Tentative
8. PRECAUTIONS
8.1 ASSEMBL Y AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35℃at normal humidity without
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Model Name: V420H2-L01
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
CHI MEI
OPTOELECTRONICS
CHI MEI
OPTOELECTRONICS
V420H2 –L01 Rev. XX
X X X X X X X Y M D L N N N N
V420H2 –L01 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
E207943
MADE IN TAIWAN
GEMN
RoHS
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
(1) 4 LCD TV modules / 1 Box
(2) Box dimensions : 1085(L)x296(W)x653(H)mm
(3) Weight : Approx. 53.17Kg(4 modules per carton)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method
LCD TV Module
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Anti-Static Bag
Cushion(Bottom)
Carton
Cushion(Top)
PP Belt
Carton Label
Figure.10-1 packing method
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Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
Sea / Land Transportation
(40ft Container)
Air Transportation
Figure.10-2 packing method
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11. MECHANICAL CHARACTERISTIC
Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
奇美電子股份有限公司
CHI MEI
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Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
奇美電子股份有限公司
CHI MEI
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Issue Date:Sep.29.2009
Model No.: V420H2-L01
Tentative
奇美電子股份有限公司
CHI MEI
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