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TFT LCD Preliminary Specification
MODEL NO.: V420H1 – LH4
Customer: _________________________________
Approved by:_______________________________
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Note:
TV Head Division
Approved By
LY Chen
Reviewed By
QRA Dept. Product Development Div.
Tomy Chen WT Lin
Prepared By
LCD TV Marketing and Product Management Div.
Ken Wu CY Chang
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
CONTENTS
REVISION HISTORY.........................................................................................................................................................4
1. GENERAL DESCRIPTION............................................................................................................................................ 5
1.1 OVERVIEW ..........................................................................................................................................................5
1.2 FEATURES...........................................................................................................................................................5
1.3 APPLICATION ......................................................................................................................................................5
1.4 GENERAL SPECIFICATIONS .............................................................................................................................5
1.5 MECHANICAL SPECIFICATIONS ....................................................................................................................... 6
2. ABSOLUTE MAXIMUM RATINGS ................................................................................................................................7
2.1 ABSOLUTE RATINGS OF ENVIRONMENT........................................................................................................7
2.2 PACKAGE STORAGE..........................................................................................................................................7
2.3 ELECTRICAL ABSOLUTE RATINGS ..................................................................................................................8
2.3.1 TFT LCD MODULE ....................................................................................................................................8
2.3.2 BACKLIGHT INVERTER UNIT ..................................................................................................................8
3. ELECTRICAL CHARACTERISTICS .............................................................................................................................9
3.1 TFT LCD MODULE ..............................................................................................................................................9
3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION......................................................................................... 11
3.2.1 LAMP SPECIFICATION...........................................................................................................................11
3.2.2 ELECTRICAL SPECIFICATION............................................................................................................... 11
3.2.3 INVERTER INTERFACE CHARACTERISTICS ......................................................................................13
4. BLOCK DIAGRAM OF INTERFACE ...........................................................................................................................15
4.1 TFT LCD MODULE ............................................................................................................................................15
5. INPUT TERMINAL PIN ASSIGNMENT.......................................................................................................................16
5.1 TFT LCD Module Input.......................................................................................................................................16
5.2 BACKLIGHT UNIT..............................................................................................................................................20
5.3 INVERTER UNIT................................................................................................................................................20
5.4 BLOCK DIAGRAM OF INTERFACE.................................................................................................................. 22
5.5 LVDS INTERFACE.............................................................................................................................................24
5.5 COLOR DATA INPUT ASSIGNMENT ................................................................................................................25
6. INTERFACE TIMING...................................................................................................................................................26
6.1 INPUT SIGNAL TIMING SPECIFICATIONS ......................................................................................................26
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
6.2 POWER ON/OFF SEQUENCE.......................................................................................................................... 28
7. OPTICAL CHARACTERISTICS ..................................................................................................................................30
7.1 TEST CONDITIONS...........................................................................................................................................30
7.2 OPTICAL SPECIFICATIONS .............................................................................................................................31
8. PRECAUTIONS...........................................................................................................................................................34
8.1 ASSEMBLY AND HANDLING PRECAUTIONS .................................................................................................34
8.2 SAFETY PRECAUTIONS ..................................................................................................................................34
9. DEFINITION OF LABELS............................................................................................................................................35
9.1 CMO MODULE LABEL ......................................................................................................................................35
10. PACKAGING..............................................................................................................................................................36
10.1 PACKAGING SPECIFICATIONS .....................................................................................................................36
10.2 PACKAGING METHOD....................................................................................................................................36
11. MECHANICAL CHARACTERISTICS ........................................................................................................................38
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REVISION HISTORY
Version Date
Ver.1.0
Jun, 25,’08
Page
(New)
All
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Section Description
All
Preliminary Specification was first issued.
Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H1-LH4 is a 42” TFT Liquid Crystal Display module with 24-CCFL Backlight unit and 4ch-LVDS interface.
This module supports 1920 x 1080 Full HDTV format and can display true 1.07G colors (10-bit/color). The
inverter module for backlight is built-in.
1.2 FEATURES
Ё High brightness (500 nits)
Ё High contrast ratio (4000:1)
Ё Fast response time (Gray to gray average 4.0 ms)
Ё High color saturation (NTSC 92%)
Ё Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
Ё DE (Data Enable) only mode
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Model No.: V420H1-LH4
Preliminary
Ё LVDS (Low Voltage Differential Signaling) interface
Ё Optimized response time for 120 Hz frame rate
Ё Ultra wide viewing angle : Super MVA technology
Ё RoHS compliance
1.3 APPLICATION
Ё Standard Living Room TVs.
Ё Public Display Application.
Ё Home Theater Application.
Ё MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 930.24(H) x 523.26 (V) (42.02” diagonal) mm
Bezel Opening Area 937.24 (H) x 530.26 (V) mm
Driver Element a-si TFT active matrix - -
Pixel Number 1920 x R.G.B. x 1080 pixel -
Pixel Pitch(Sub Pixel) 0.1615 (H) x 0.4845 (V) mm -
Pixel Arrangement RGB vertical stripe - -
(1)
Display Colors 1.07G color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment Hot Coating Low Reflection - (2)
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and back outlines.
Note (2) The spec. of the surface treatment is temporarily for this phase. CMO reserves the rights to change this
feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) - 957.24 - mm
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Module Size
Weight - 11600 - g -
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth is between bezel to T-CON cover.
Vertical (V) - 550.26 - mm
Depth (D) - 32.0 - mm
(1), (2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Item Symbol
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) SNOP - 50 G (3), (5)
Vibration (Non-Operating) VNOP - 1.0 G (4), (5)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Value
Unit Note
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
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light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Item Symbol
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
2.3.2 BACKLIGHT INVERTER UNIT
Item Symbol
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V (1)
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3) The control signals include On/Off Control and Internal PWM Control.
Ё
Min. Max.
Min. Max.
Ё
-0.3 7 V (1), (3)
Value
Unit Note
Value
Unit Note
3000 VRMS
(1)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Power Supply Ripple Voltage VRP - - 350 mV
Rush Current IRUSH - - 6.0 A (2)
White Pattern - - 1.6 2.0 A
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Model No.: V420H1-LH4
Preliminary
Value
Unit Note
Min. Typ. Max.
Power Supply Current
LVDS
interface
CMOS
interface
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
Common Input Voltage VLVC 1.125 1.25 1.375 V
Terminating Resistor RT - 100 - ohm
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage VIL 0 - 0.7 V
Vertical Stripe
Black Pattern - - 1.0 - A
-
- 1.5 - A
(3)
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, fv = 120 Hz,
whereas a power dissipation check pattern below is displayed.
a. White Pattern
Active Area
c. Vertical Stripe Pattern
b. Black Pattern
Active Area
Active Area
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3.2 BACKLIGHT CONNECTOR PIN CONFIGURATION
3.2.1 LAMP SPECIFICATION
(Ta = 25 ± 2 ºC)
Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Parameter Symbol
Min. Typ. Max.
Lamp Input Voltage VL - (1490) - VRMS -
Lamp Current IL 4.5 5.0 5.5 mARMS (1)
- - (2370) VRMS Ta = 0 ºC
Lamp Turn On Voltage VS
- - (2160) VRMS Ta = 25 ºC
Operating Frequency FL 40 - 70 KHz
Lamp Life Time LBL 50,000 60,000 - Hrs (2)
3.2.2 ELECTRICAL SPECIFICATION
(Ta = 25 ± 2 ºC)
Parameter Symbol
Min. Typ. Max.
Power Consumption PBL - 170 - W (5), IL =5.0mA
Power Supply Voltage VBL 22.8 24.0 25.2 VDC
Value
Unit Note
Value
Unit Note
Power Supply Current IBL - 7.1 - A Non Dimming
Input Ripple Noise - - - 912 mVP-P VBL=22.8V
Oscillating Frequency FW 40 43 46 kHz
Dimming frequency FB 150 160 170 Hz
Minimum Duty Ratio DMIN - 10 - %
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring master
and slave board.
Note (2) The lamp starting voltage VS should be applied to the lamp for more than 1 second after startup.
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the display input
signals, and it may result in line flow on the display. In order to avoid interference, the lamp frequency
should be detached from the horizontal synchronous frequency and itó harmonics as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and the
effective discharge length is longer than 80% of its original length (Effective discharge length is defined
as an area that has equal to or more than 70% brightness compared to the brightness at the center point
of lamp.) as the time in which it continues to operate under the condition at Ta = 25 ±2к and IL =4.5~
5.5mArms.
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Model No.: V420H1-LH4
Note (5) The measurement condition of Max. value is based on 42” backlight unit under input voltage 24V,
average lamp current 5.5 mA and lighting 30 minutes later.
Note (6)
Preliminary
Inverter
(Master)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink -)
2
LCD Module
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
HV(Pink -)
HV(White +)
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
Inverter
(Slavor)
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3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Parameter Symbol
On/Off Control Voltage
ON
VBLON
OFF
Internal PWM Control
Voltage
External PWM Control
Voltage
Status Signal
MAX
MIN
HI
LO
HI
VIPWM
VEPWM
Status
LO
VBL Rising Time Tr1
VBL Falling Time Tf1
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time TPWMR
PWM Signal Falling Time TPWMF
Input Impedance Rin
PWM Delay Time TPWM
BLON Delay Time Ton
BLON Off Time Toff
Te st
Condition
Ё
Ё
Ё
Min. Typ. Max.
2.0
0
2.85 3.0 3.15 V
Ё Ё
Ё
Ё
Ё
Ё
Ё
Ё
2.0
0
3.0 3.3 3.6 V
0
30
30
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё Ё Ё
Ё
Ё
Ё
Ё
1
100
300
300
Value
Ё
Ё
0
Ё
Ё
Ё
Ё
Ё
Ё Ё
Ё
Ё
Ё
Unit Note
5.0 V
0.8 V
Ё
V
5.0 V
0.8 V
0.8 V
50 ms
50 ms
100 ms
100 ms
50 us
50 us
M
300 ms
500 ms
500 ms
Max. Duty Ratio
Min. Duty Ratio
Duty on
Duty off
Normal
Abnormal
See as below
Note (1) The dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to change
the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure.
Note (3) The power sequence and control signal timing must follow the figure below. For a certain reason, the
inverter has a possibility to be damaged with wrong power sequence and control signal timing.
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
V
VBLON
V
EPWM
V
IPWM
Tr1
BL
2.0V
0.8V
2.0V
0.8V
3.0V
PWM
Ton
PWM
T
Backlight on duration
Tr
TPWMR
Tf
PWMF
T
External
PWM Duty
0
0
0
0
V
W
External
Period
Tf1
Toff
100%
Minimun
Duty
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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Model No.: V420H1-LH4
Preliminary
DRX0(+/-)
DRX1(+/-)
DRX2(+/-)
DRX3(+/-)
DRX4(+/-)
DCLK(+/-)
CRX0(+/-)
CRX1(+/-)
CRX2(+/-)
CRX3(+/-)
CRX4(+/-)
CCLK(+/-)
BRX0(+/-)
BRX1(+/-)
BRX2(+/-)
BRX3(+/-)
BRX4(+/-)
BCLK(+/-)
ARX0(+/-)
ARX1(+/-)
ARX2(+/-)
ARX3(+/-)
ARX4(+/-)
ACLK(+/-)
SELLVDS
DCREN
Vcc
GND
FRAME
BUFFER
TIMING
CONTROLLER
(SLAVE)
FRAME
BUFFER
TIMING
CONTROLLER
(MASTER)
TFT LCD PANEL
1920 X 3 X 1080
DATA DRIVER(RSDS)
CN1
VBL
GND
Status
E_PWM
I_PWM
BLON
DC/DC CONVERTER &
INVERTER
CONNECTOR
CN1: S14B-PH-SM4-
TB(D)(LF) or equivalent
(Master)
REFERENCE
VOLTAGE
GENERATOR
BACKLIGHT
CN3~CN26: SM02(12.0)B-BHS-
1-TB(LF)(JST) or equivalent
CN27, CN28: 528521070(Molex)
UNIT
INVERTER
CONNECTOR
CN2: S12B-PH-SM4-
TB(D)(LF) or equivalent
(Slave)
CN2
VBL
GND
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 GND Ground
2 N.C. No Connection (1)
3 N.C. No Connection (1)
4 N.C. No Connection (1)
5 N.C. No Connection (1)
6 N.C. No Connection (1)
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Model No.: V420H1-LH4
Preliminary
7 SELLVDS LVDS Data Format Selection (2)
8 N.C. No Connection (1)
9 N.C. No Connection (1)
10 N.C. No Connection (1)
11 GND Ground
12 ARX0- First pixel Negative LVDS differential data input. Channel 0
13 ARX0+ First pixel Positive LVDS differential data input. Channel 0
14 ARX1- First pixel Negative LVDS differential data input. Channel 1
15 ARX1+ First pixel Positive LVDS differential data input. Channel 1
16 ARX2- First pixel Negative LVDS differential data input. Channel 2
17 ARX2+ First pixel Positive LVDS differential data input. Channel 2
18 GND Ground
19 ACLK- First pixel Negative LVDS differential clock input.
20 ACLK+ First pixel Positive LVDS differential clock input.
21 GND Ground
22 ARX3- First pixel Negative LVDS differential data input. Channel 3
23 ARX3+ First pixel Positive LVDS differential data input. Channel 3
24 ARX4- First pixel Negative LVDS differential data input. Channel 4
25 ARX4+ First pixel Positive LVDS differential data input. Channel 4
26 N.C. No Connection (1)
27 N.C. No Connection (1)
28 BRX0- Second pixel Negative LVDS differential data input. Channel 0
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29 BRX0+ Second pixel Positive LVDS differential data input. Channel 0
30 BRX1- Second pixel Negative LVDS differential data input. Channel 1
31 BRX1+ Second pixel Positive LVDS differential data input. Channel 1
32 BRX2- Second pixel Negative LVDS differential data input. Channel 2
33 BRX2+ Second pixel Positive LVDS differential data input. Channel 2
34 GND Ground
35 BCLK- Second pixel Negative LVDS differential clock input.
36 BCLK+ Second pixel Positive LVDS differential clock input.
37 GND Ground
38 BRX3- Second pixel Negative LVDS differential data input. Channel 3
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39 BRX3+ Second pixel Positive LVDS differential data input. Channel 3
40 BRX4- Second pixel Negative LVDS differential data input. Channel 4
41 BRX4+ Second pixel Positive LVDS differential data input. Channel 4
42 N.C. No Connection (1)
43 N.C. No Connection (1)
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (1)
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
CNF2 Connector Pin Assignment (FI-RE41S(JAE) or equivalent)
Pin Name Description Note
1 GND Ground
2 N.C. No Connection (1)
3 N.C. No Connection (1)
4 N.C. No Connection (1)
5 N.C. No Connection (1)
6 N.C. No Connection (1)
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7 N.C. No Connection (1)
8 N.C. No Connection (1)
9 GND Ground
10 CRX0- Third pixel Negative LVDS differential data input. Channel 0
11 CRX0+ Third pixel Positive LVDS differential data input. Channel 0
12 CRX1- Third pixel Negative LVDS differential data input. Channel 1
13 CRX1+ Third pixel Positive LVDS differential data input. Channel 1
14 CRX2- Third pixel Negative LVDS differential data input. Channel 2
15 CRX2+ Third pixel Positive LVDS differential data input. Channel 2
16 GND Ground
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Model No.: V420H1-LH4
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17 CCLK- Third pixel Negative LVDS differential clock input.
18 CCLK+ Third pixel Positive LVDS differential clock input.
19 GND Ground
20 CRX3- Third pixel Negative LVDS differential data input. Channel 3
21 CRX3+ Third pixel Positive LVDS differential data input. Channel 3
22 CRX4- Third pixel Negative LVDS differential data input. Channel 4
23 CRX4+ Third pixel Positive LVDS differential data input. Channel 4
24 N.C. No Connection (1)
25 N.C. No Connection (1)
26 DRX0- Fourth pixel Negative LVDS differential data input. Channel 0
27 DRX0+ Fourth pixel Positive LVDS differential data input. Channel 0
28 DRX1- Fourth pixel Negative LVDS differential data input. Channel 1
29 DRX1+ Fourth pixel Positive LVDS differential data input. Channel 1
30 DRX2- Fourth pixel Negative LVDS differential data input. Channel 2
31 DRX2+ Fourth pixel Positive LVDS differential data input. Channel 2
32 GND Ground
33 DCLK- Fourth pixel Negative LVDS differential clock input.
34 DCLK+ Fourth pixel Positive LVDS differential clock input.
35 GND Ground
36 DRX3- Fourth pixel Negative LVDS differential data input. Channel 3
37 DRX3+ Fourth pixel Positive LVDS differential data input. Channel 3
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38 DRX4- Fourth pixel Negative LVDS differential data input. Channel 4
39 DRX4+ Fourth pixel Positive LVDS differential data input. Channel 4
40 N.C. No Connection (1)
41 N.C. No Connection (1)
Note (1) Please be reserved to open.
Note (2) Low or Open: VESA Format (Default), High: JEIDA Format.
Note (3) LVDS 4-port Data Mapping
Port Channel of LVDS Data Stream
1st Port First Pixel 1, 5, 9, ……1913, 1917
2nd Port Second Pixel 2, 6, 10, ….1914, 1918
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Model No.: V420H1-LH4
Preliminary
3rd Port Third Pixel 3, 7, 11, ….1915, 1919
4th Port Fourth Pixel 4, 8, 12, ….1916, 1920
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Model No.: V420H1-LH4
Preliminary
5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
CN3~CN26: BHR-04VS-1 (JST).
Pin Name Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST. The
mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).
5.3 INVERTER UNIT
CN1: S14B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
3
4
5
6
7
8
9
10
11 STATUS
12 E_PWM External PWM Control Signal
VBL +24V
GND GND
Normal (3.3V)
Abnormal(GND)
13 I_PWM Internal PWM Control Signal
14 BLON BL ON/OFF
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Note (1) Pin 12: External PWM control (use pin 12): Pin 13 must open.
Note (2) Pin 13: Internal PWM control (use pin 13): 0~3.0V and pin 12 must open.
Note (3) Pin 12 and Pin 13 can’t open in the same period.
CN2: S12B-PH-SM4-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
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Preliminary
3
4
5
6
7
8
9
10
11 NC NC
12 NC NC
CN3~CN26: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent
Pin Symbol Description
1 CCFL HOT CCFL high voltage
2 CCFL HOT CCFL high voltage
CN27, CN28: 528521070 (Molex)
VBL +24V
GND GND
Pin Symbol Description
1 Board to Board
2 Board to Board
3 Board to Board
4 Board to Board
5 Board to Board
6 Board to Board
7 Board to Board
8 Board to Board
9 Board to Board
10
Control Signal
Board to Board
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5.4 BLOCK DIAGRAM OF INTERFACE
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Model No.: V420H1-LH4
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AR0~AR9: First pixel R data
AG0~AG9: First pixel G data
AB0~AB9: First pixel B data
BR0~BR9: Second pixel R data
BG0~BG9: Second pixel G data
BB0~BB9: Second pixel B data
DE: Data enable signal
DCLK: Data clock signal
The third and fourth pixel are followed the same rules.
CR0~CR9: Third pixel R data
CG0~CG9: Third pixel G data
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CB0~CB9: Third pixel B data
DR0~DR9: Fourth pixel R data
DG0~DG9: Fourth pixel G data
DB0~DB9: Fourth pixel B data
Note (1) A ~ D channel are first, second, third and fourth pixel respectively.
Note (2) The system must have the transmitter to drive the module.
Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
used differentially.
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5.5 LVDS INTERFACE
VESA Format : SELLVDS = L or Open
JEIDA Format : SELLVDS = H
VESA Format
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Current Cycle
AR 0P
AR 0N
AR 1P
AR 1N
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
JEIDA Format
AR 0P
AR 0N
AR 1P
AR 1N
AR0
AG1
AB2
AR6
AR4
AG5
AG0 AR5
AB1
DE VS HS AB5 AB4 AB3 AB2
REV AB7 AB6 AG7 AG6 AR7 AR6
REV AB9 AB8 AG9 AG8 AR9 AR8 AR8 REV
AG4 AR7
AB5
AB0 AG5 AG4 AG3 AG2 AG1
AB4 AG7 AG6 AG5 AG9 AG8
AR4 AR3 AR2 AR1 AR0
AR6 AR5 AR4 AR9 AR8
AG0
AB1
DE
REV
AG4
AB5
AR 2P
AR 2N
AR 3P
AR 3N
AR 4P
AR 4N
AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)
AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)
AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
RSVD : Reserved
AB6
AR2
DE VS HS AB7 AB6 AB9 AB8
REV AB3 AB2 AG3 AG2 AR3 AR2
REV AB1 AB0 AG1 AG0 AR1 AR0 AR0 REV
DE
REV
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5.5 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Color
Black
Red
Green
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (1021)
Red (1022)
Red (1023)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (1021)
Green (1022)
Green (1023)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (1021)
Blue (1022)
Blue (1023)
R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Red Green Blue
0
0
0
1
0
0
0
1
1
1
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Note (1) 0: Low Level Voltage, 1: High Level Voltage
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0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
:
:
:
:
:
:
1
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
0
1
1
1
0
0
1
1
1
1
1
1
0
0
0
1
0
0
0
0
0
:
:
:
:
:
:
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
Data Signal
0
0
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
1
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
;
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
:
:
:
:
:
:
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
1
0
0
1
0
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
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Model No.: V420H1-LH4
Preliminary
LVDS Receiv er
Clock
LVDS Receiv er
Data
Vertical
Active Display
Te rm
Horizontal
Active Display
Te rm
Note : Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low logic
level. Otherwise, this module would operate abnormally.
Frequency 1/Tc 60 74.25 80 MHz -
Input cycle to
cycle jitter
Setup Time Tlvsu 600 - - ps -
Hold Time Tlvhd 600 - - ps -
Frame Rate - 120 - Hz
Total Tv 1115 11 25 1139 Th
Display Tvd 1080 1080 1080 Th -
Blank Tvb 35 45 59 Th -
Total Th 540 550 575 Tc
Display Thd 480 480 480 Tc -
Blank Thb 45 70 95 Tc -
Trcl - - 200 ps -
Tv=Tvd+Tvb
Th=Thd+Thb
Valid display data (480 clocks)
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Model No.: V420H1-LH4
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6.2 POWER ON/OFF SEQUENCE
(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram
below.
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Note.
Signal Min. Typ. Max. Unit Note
T1 0.5 - 10 ms -
T2 0 - 50 ms -
T3 0 - 50 ms -
T4 500 - - ms -
T5 500 - - ms -
T6 100 - - ms -
T7 0 - T2 - -
T8 0 - - - -
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(a) The supply voltage of the external system for the module input should follow the definition of Vcc.
(b) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become abnormal
screen.
(c) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(d) T4 should be measured after the module has been fully discharged between power off and on period.
(e) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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Model No.: V420H1-LH4
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Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
LCD Module
LCD Panel
Center of the Screen
25r 2
50r 10
5.0r 0.5
43r 3
Display Color Analyzer
(Minolta CA210)
oC
%RH
mA
KHz
Light Shield Room
(Ambient Luminance < 2 lux)
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
Contrast Ratio CR (3000) (4000) - - Note (2)
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Response Time
Center Luminance of White LC (400) (500) - cd/m2Note (4)
White Variation
Cross Talk CT - - (4) % Note (5)
Red
Green
Color
Chromaticity
Viewing Angle
Blue
White
Color Gamut C.G
Horizontal
Vertical
Gray to
gray
G W
Rx (0.658) -
Ry (0.328) -
Gx
Gy
Bx
By
Wx
Wy
Tx+
Tx-
TY+
TY-
Tx=0q, Ty =0q
Viewing angle
at normal direction
CRt 20
- (4.0) (8.0) ms Note (3)
- - (1.3) - Note (7)
(0.190)
Typ.
-0.03
(0.675)
(0.151)
(0.061)
(0.280)
(0.285)
- (92) - % NTSC
80 88 -
80 88 -
80 88 -
80 88 -
Typ.
+0.03
-
-
-
-
-
-
Deg. Note (1)
-
Gamma - (2.2) - - -
Note (1) Definition of Viewing Angle (Tx, Ty):
Viewing angles are measured by Eldim EZ-Contrast 160R
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Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
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Contrast Ratio (CR) =
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (7).
Note (3) Definition of Gray-to-Gray Switching Time:
The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892 and 1023.
pixels white all with Luminance Surface
pixels black all with Luminance Surface
Gray to gray average time means the average switching time of gray level 0, 124, 252, 380, 508, 636, 764, 892,
1023 to each other.
Note (4) Definition of Luminance of White (LC, LAVE):
Measure the luminance of gray level 1023 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
CT = | YB – YA | / YA u 100 (%)
Where:
YA = Luminance of measured location without gray level 0 pattern (cd/m2)
YB = Luminance of measured location with gray level 0 pattern (cd/m2)
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Note (6) Definition of White Variation (GW):
Measure the luminance of gray level 1023 at 5 points
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GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 6 ] Do not disassemble the module.
[ 7 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 8 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 9 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 9.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35к at normal humidity without
condensation.
[ 9.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 10 ] When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
Model Name: V420H1-LH4
CHI MEI
OPTOELECTRONICS
V420H1 -LH4 Rev. XX
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
E207943
MADE IN TAIW A N
RoHS
X X X X X X X Y M D L N N N N
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
Serial ID includes the information as below:
Manufactured Date:
Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
CMO Internal Use
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
5 LCD TV modules / 1 Box
Box dimensions: 1040(L) X 310 (W) X 640(H)
Weight: approximately 60 Kg (5 modules per box)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method.
LCD TV Module
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Anti-static Bag
Cushion(Top)
Figure.10-1 Packing method
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
Sea / Land Transportation (40ft Container)
(Pallet:L1250*W1050*H140mm)
Air Transportation
(Pallet:L1250*W1050*H140mm)
Figure.10-2 Packing method
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11. MECHANICAL CHARACTERISTICS
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
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Issue Date:Jun.25.2008
Model No.: V420H1-LH4
Preliminary
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