CMO V420H1-LE1 Specification

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TFT LCD Preliminary Specification

MODEL NO.: V420H1 – LE1

Customer: _________________________________

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Approved by:_______________________________

Note:

TV Product Marketing & Management Div

Approved By

Chao-Chun Chung

Reviewed By

QA Dept. Product Development Div.

Hsin-Nan Chen WT Lin

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Prepared By

LCD TV Marketing and Product Management Div.

CY Chang CY Sung

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

- CONTENTS -

REVISION HISTORY ------------------------------------------------------- 3

1. GENERAL DESCRIPTION ------------------------------------------------------- 4

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 5

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2PACKAGE STORAGE

2.3ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

2.3.2 BACKLIGHT UNIT

3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 7

3.1 TFT LCD MODULE

3.2 BACKLIGHT CONVERTER UNIT

3.2.1

3.2.2 CONVERTER CHARACTERISTICS

4. BLOCK DIAGRAM ------------------------------------------------------- 10

4.1 TFT LCD MODULE

5. INTERFACE PIN CONNECTION ------------------------------------------------------- 11

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT

5.3 CONVERTER UNIT

5.4 BLOCK DIAGRAM OF INTERFACE

5.5 LVDS INTERFACE

5.6 COLOR DATA INPUT ASSIGNMENT

6. INTERFACE TIMING ------------------------------------------------------- 21

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS ------------------------------------------------------- 24

7.1 TEST CONDITIONS

7.2 OPTICAL SPECIFICATIONS

8. DEFINITION OF LABELS ------------------------------------------------------- 28

8.1 CMO MODULE LABEL

9. PACKAGING ------------------------------------------------------- 29

9.1 PACKING SPECIFICATIONS

9.2 PACKING METHOD

10. PRECAUTIONS ------------------------------------------------------- 31

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

10.2 SAFETY PRECAUTIONS

11. MECHANICAL CHARACTERISTICS ------------------------------------------------------- 32

LED LIGHT BARCHARACTERISTICS

3.2.3 CONVERTER INTERFACE CHARACTERISTICS

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Model No.: V420H1 – LE1

Preliminary

REVISION HISTORY

Version Date

Aug 28,09’

Ver 0.0

Page

(New)

All

Section Description

All

Preliminary Specification was first issued.

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

V420 H1- LE1 is a 42” TFT Liquid Crystal Display module with 6pcs LED Light Bar Backlight and

2ch-LVDS interface. This module supports 1920 x 1080 Full HDTV format and can display 1.07G colors

( 8-bit +FRC). The converter module for backlight is built-in.

1.2 FEATURES

-High brightness (450 nits)

- Ultra-high contrast ratio (4000:1)

- Faster response time (gray to gray average 4ms)

- High color saturation NTSC 72%

- Ultra wide viewing angle : 176(H)/176(V) (CRt20) with Super MVA technology

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- DE (Data Enable) only mode

- LVDS (Low Voltage Differential Signaling) interface

- Color reproduction (nature color)

- Low color shift function

1.3 APPLICATION

- TFT LCD TVs

- Multi-Media Display

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note Active Area 930.24 (H) x 523.26 (V) (42" diagonal) mm Bezel Opening Area 937.24 (H) x 530.26 (V) mm Driver Element a-si TFT active matrix - Pixel Number 1920 x R.G.B. x 1080 pixel Pixel Pitch (Sub Pixel) 0.1615 (H) x 0.4845 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors Display Operation Mode Transmissive mode / Normally Black -

Surface Treatment

Anti-Glare Coating (Haze 11%)

1.07G

Hard Coating (3H)

color

(1)

-

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal(H) - 983 - mm (1)

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Vertical(V) - 576 - mm (1) Depth(D) 11 12 13 mm Depth(D) 26.8 mm To converter cover

Weight 8600

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2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 +50 ºC (1), (2) Shock (Non-Operating) S Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta Љ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The maximum operating temperature is based on the test condition that the surface temperature of

display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.

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Preliminary

Value

Min. Max.

- 50 G (3), (5)

NOP

- 1.0 G (4), (5)

NOP

Unit Note

Thermal management should be considered in final product design to prevent the surface temperature of

display area from being over 65 ºC. The range of operating temperature may degrade in case of improper

thermal management in final product design.

Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.

Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so

that the module would not be twisted or bent by the fixture.

Relative Humidity (%RH)

100

90

80

60

Operating Range

40

-40 -20 0 20 40 60 80

20

10

Storage Range

Temperature (ºC)

5

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2.2 Package storage

When storing modules as spares for a long time, the following precaution is necessary.

(a) Do not leave the module in high temperature, and high humidity for a long time. It is highly recommended to

store the module with temperature from 0 to 35кat normal humidity without condensation.

(b)The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or

fluorescent light.

2.3 ELECTRICAL ABSOLUTE RATINGS

2.3.1 TFT LCD MODULE

Item Symbol

Power Supply Voltage Vcc -0.3 13.5 V Input Signal Voltage VIN -0.3 3.6 V

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Value

Min. Max.

Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Unit Note

2.3.2 BACKLIGHT UNIT

Item Symbol

Light Bar Voltage VW Ta = 25 к - - 60 V

Converter Input Voltage VBL - 0 - 30 V

Control Signal Level - - -0.3 - 7 V

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Functional operation

should be restricted to the conditions described under normal operating conditions.

Note (2) No moisture condensation or freezing.

Note (3) The control signals includes Backlight On/Off Control, I_PWM Control, E_PWM Control and

signal for converter status output.

Te st

Condition

Min. Type Max. Unit Note

RMS

STATUS

6

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3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE Ta = 25 ± 2 ºC

Value

Parameter Symbol

Min. Typ. Max.

Unit Note

Power Supply Voltage

Power Supply Ripple Voltage

Rush Current

White Pattern

VCC 10.8 12 13.2 V (1)

VRP - - 350 mV

IRUSH - - 5.4 A (2)

- - 1.32 1.716 A

-

Power Supply Current

Vertical Stripe

- 1.3 - A

- - 0.83 - A

VLVC 1.125 1.25 1.375 V

RT - 100 - ohm

VIH 2.7 - 3.3 V

VIL 0 - 0.7 V

LVDS

interface

CMOS

interface

Black Pattern

Common Input Voltage

Terminating Resistor

Input High Threshold Voltage

Input Low Threshold Voltage

Note (1) The module should be always operated within above ranges.

Note (2) Measurement Conditions:

+12.0V

Q1 Si4 435DY

FUSE

R1

1K

C3

1uF

(3)

Vcc

(LCD Module Input)

VR1

(Low to High)

(Control Signal)

SW

R2

1K

47K

Q2

2N7002

C1

0.01uF

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Vcc rising time is 470us

0.1Vcc

GND

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+12V

0.9Vcc

470us

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Model No.: V420H1 – LE1

Preliminary

Note (3) The specified power supply current is under the conditions at Vcc =12V, Ta = 25 ± 2 ºC, f

whereas a power dissipation check pattern below is displayed.

a. White Pattern

Active Area

c. Vertical Stripe Pattern

b. Black Pattern

Active Area

R

G

B

R

B

R

G

B

R

= 60 Hz,

v

B

G

B

Active Area

8

R

G

B

R

RR

G

B

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3.2 BACKLIGHT CONVERTER UNIT

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Model No.: V420H1 – LE1

Preliminary

3.2.1 LED LIGHT BARCHARACTERISTICS (

Parameter Symbol

Light Bar Voltage VW

LED Forward Voltage Vf

LED Current IL

3.2.2 CONVERTER CHARACTERISTICS (

Parameter Symbol

Power Consumption PBL - 84 92 W

Converter Input Voltage VBL

Converter Input Current IBL

Dimming Frequency FB 150 160 170 Hz

Minimum Duty Ratio D

- 5 - %

MIN

Min. Typ. Max.

- - 44.2

3.0 3.2 3.4

56.4 60 63.6

Ta = 25 ± 2 ºC)

Min. Typ. Max.

22.8 24 25.2

-

3.2.3 CONVERTER INTERFACE CHARACTERISTICS

External dimming: 150Hz~170Hz, duty ratio: 5%~100%

Ta = 25 ± 2 ºC)

Value

3.5

Unit Note

V

I

RMS

V

I

RMS

=60 mA

L

=60mA

L

mA

Unit Note

VDC

-

A

Parameter Symbol

ON

On/Off Control Voltage

VBLON

OFF

Internal PWM Control

MAX

VIPWM

Voltage

External PWM Control

Voltage

MIN

HI

LO

VEPWM

HI

Status Signal

Status

LO

VBL Rising Time Tr1

VBL Falling Time Tf1

Control Signal Rising Time Tr

Te st

Condition

Ё

Min. Typ. Max.

2.0

0

3.15

Ё Ё

Ё

2.0

0

3.0 3.3 3.6 V Normal

0

30

Ё Ё Ё

Value

Ё

0

Ё

Ё Ё

Unit Note

5.0 V

0.8 V

3.45

Ё

maximum duty ratio

V

minimum duty ratio

V

5.0 V Duty on

0.8 V Duty off

0.8 V Abnormal

ms

10%-90%V

BL

ms

100 ms

Control Signal Falling Time Tf

PWM Signal Rising Time TPWMR

PWM Signal Falling Time TPWMF

Ё Ё Ё

9

100 ms

50 us

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Model No.: V420H1 – LE1

Preliminary

Input Impedance Rin

PWM Delay Time TPWM

Ton

Ё

1

100

300

Ё Ё

M

ms

BLON Delay Time

T

on1

BLON Off Time Toff

Ё

300

Ё Ё

ms

Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to

change the internal/external PWM signal during backlight turn on period.

Note (2) The power sequence and control signal timing are shown in the following figure. For a certain

reason, the converter has a possibility to be damaged with wrong power sequence and control

signal timing.

Note (3) While system is turned ON or OFF, the power sequences must follow as below descriptions:

Turn ON sequence: VBL Ш PWM signal Ш BLON

Turn OFF sequence: BLOFF Ш PWM signal Ш VBL

Tr1

BL

V

BLON

0

9

%/

2.0V

0.8V

9%/

Ton

Backlight on duration

Tr

Tf

Ton1

%/

9

Toff

Tf1

9

%/

V

EPWM

IPWM

V

Ext. Dimming Function

PWMR

T

2.0V

0

W

0.8V

3.3V

External

PWM

Period

T

PWM

Floating

PWMF

T

External

PWM Duty

10

Floating

Int. Dimming Function

100%

Minimun

Duty

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4.1 TFT LCD MODULE

CNF1 : FI-RE41S-HF(JAE)

DRX0(+/-)

DRX1(+/-)

DRX2(+/-)

DRX3(+/-)

DRX4(+/-)

DCLK(+/-)

CRX0(+/-)

CRX1(+/-)

CRX2(+/-)

CRX3(+/-)

CRX4(+/-)

CCLK(+/-)

INPUT CONNECTOR

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4. BLOCK DIAGRAM

FRAME

BUFFER

Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

SCAN DRIVER

TFT LCD PANEL

1920 X 3 X 1080

BRX0 (+/-)

BRX1 (+/-)

BRX2 (+/-)

BRX3 (+/-)

BRX4 (+/-)

BCLK (+/-)

ARX0 (+/-)

ARX1 (+/-)

ARX2 (+/-)

ARX3 (+/-)

ARX4 (+/-)

ACLK (+/-)

SELLVDS

Vcc

GND

TIMING

CONTROLLER

INPUT CONNECTOR

CNF2 : FI-RE51S-HF(JAE)

DC/DC CONVERTER &

REFERENCE

VOLTAGE

GENERATOR

DATA DRIVER(RSDS)

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5. INTERFACE PIN CONNECTION

5.1 TFT LCD MODULE

CNF1 Connector Pin Assignment (FI-RE41S-HF(JAE) or equivalent)

Pin Name Description Note

1 GND Ground 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 N.C. No Connection 6 N.C. No Connection 7 N.C. No Connection 8 N.C. No Connection 9 GND Ground

10 CH3_0N Third Pixel Negative LVDS differential data input. Channel 0

11 CH3_0P Third Pixel Positive LVDS differential data input. Channel 0 12 CH3_1N Third Pixel Negative LVDS differential data input. Channel 1 13 CH3_1P Third Pixel Positive LVDS differential data input. Channel 1 14 CH3_2N Third Pixel Negative LVDS differential data input. Channel 2 15 CH3_2P Third Pixel Positive LVDS differential data input. Channel 2 16 GND Ground

17 CH3_CLKN

Third Pixel Negative LVDS differential clock input.

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(1)

(4)

18 CH3_CLKP

Third Pixel Positive LVDS differential clock input.

19 GND Ground 20 CH3_3N Third Pixel Negative LVDS differential data input. Channel 3 21 CH3_3P Third Pixel Positive LVDS differential data input. Channel 3 22 CH3_4N Third Pixel Negative LVDS differential data input. Channel 4 23 CH3_4P Third Pixel Positive LVDS differential data input. Channel 4 24 N.C. No Connection 25 N.C. No Connection 26 CH4_0N Fourth Pixel Negative LVDS differential data input. Channel 0 27 CH4_0P Fourth Pixel Positive LVDS differential data input. Channel 0 28 CH4_1N Fourth Pixel Negative LVDS differential data input. Channel 1 29 CH4_1P Fourth Pixel Positive LVDS differential data input. Channel 1 30 CH4_2N Fourth Pixel Negative LVDS differential data input. Channel 2 31 CH4_2P Fourth Pixel Positive LVDS differential data input. Channel 2 32 GND Ground

33 CH4_CLKN

34 CH4_CLKP

Fourth Pixel Negative LVDS differential clock input.

Fourth Pixel Positive LVDS differential clock input.

35 GND Ground 36 CH4_3N Fourth Pixel Negative LVDS differential data input. Channel 3 37 CH4_3P Fourth Pixel Positive LVDS differential data input. Channel 3 38 CH4_4N Fourth Pixel Negative LVDS differential data input. Channel 4 39 CH4_4P Fourth Pixel Positive LVDS differential data input. Channel 4 40 N.C. No Connection 41 N.C. No Connection

(4)

(1)

(4)

(1)

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CNF2 Connector Pin Assignment (FI-RE51S-HF (JAE) or equivalent )

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Model No.: V420H1 – LE1

Preliminary

Pin Name

Description Note

1 N.C. No Connection 2 N.C. No Connection 3 N.C. No Connection 4 N.C. No Connection 5 ODSEL Overdrive Lookup Table Selection (3) 6 N.C. No Connection (1) 7 SELLVDS LVDS data format Selection (2) 8 N.C. No Connection 9 N.C. No Connection

10 N.C. No Connection

11 GND Ground 12 CH1_0N First Pixel Negative LVDS differential data input. Channel 0 13 CH1_0P First Pixel Positive LVDS differential data input. Channel 0 14 CH1_1N First Pixel Negative LVDS differential data input. Channel 1 15 CH1_1P First Pixel Positive LVDS differential data input. Channel 1 16 CH1_2N First Pixel Negative LVDS differential data input. Channel 2 17 CH1_2P First Pixel Positive LVDS differential data input. Channel 2 18 GND Ground

CH1_CLK

19

N CH1_CLK

20

P

First Pixel Negative LVDS differential clock input.

First Pixel Positive LVDS differential clock input.

21 GND Ground 22 CH1_3N First Pixel Negative LVDS differential data input. Channel 3 23 CH1_3P First Pixel Positive LVDS differential data input. Channel 3 24 CH1_4N First Pixel Negative LVDS differential data input. Channel 4 25 CH1_4P First Pixel Positive LVDS differential data input. Channel 4 26 N.C. No Connection 27 N.C. No Connection 28 CH2_0N Second Pixel Negative LVDS differential data input. Channel 0 29 CH2_0P Second Pixel Positive LVDS differential data input. Channel 0 30 CH2_1N Second Pixel Negative LVDS differential data input. Channel 1 31 CH2_1P Second Pixel Positive LVDS differential data input. Channel 1 32 CH2_2N Second Pixel Negative LVDS differential data input. Channel 2 33 CH2_2P Second Pixel Positive LVDS differential data input. Channel 2 34 GND Ground

CH2_CLK

35

N CH2_CLK

36

P

Second Pixel Negative LVDS differential clock input.

Second Pixel Positive LVDS differential clock input.

37 GND Ground 38 CH2_3N Second Pixel Negative LVDS differential data input. Channel 3 39 CH2_3P Second Pixel Positive LVDS differential data input. Channel 3

(1)

(4)

(1)

(4)

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40 CH2_4N Second Pixel Negative LVDS differential data input. Channel 4 41 CH2_4P Second Pixel Positive LVDS differential data input. Channel 4 42 N.C. No Connection 43 N.C. No Connection 44 GND Ground 45 GND Ground 46 GND Ground 47 N.C. No Connection (1) 48 Vin Power input (+12V) 49 Vin Power input (+12V) 50 Vin Power input (+12V) 51 Vin Power input (+12V)

Note (1) Please be reserved to open.

Note (2) Low or Open: VESA Format(default), connect to GND. High: JEIDA Format, connect to

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Model No.: V420H1 – LE1

Preliminary

(1)

+3.3V.

Note (3) Overdrive lookup table selection. The overdrive lookup table should be selected in

accordance with the frame rate to optimize image quality.

ODSEL Note

L Lookup table was optimized for 120 Hz frame rate.

H

Lookup table was optimized for 100 Hz frame rate.

Note (4) LVDS 4-Port Data Mapping

Port CH of LVDS Data Stream

1st Port First pixel 1, 5, 9, ..........., 1913, 1917

2nd Port Second pixel 2, 6, 10, ........., 1914, 1918

3rd Port Third pixel 3, 7, 11, ........., 1915, 1919

4th Port Fourth pixel 4, 8, 12, ........., 1916, 1920

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5.2 BACKLIGHT UNIT

The pin configuration for the housing and leader wire is shown in the table below.

CN2-CN7 (Housing): 51281-0994 (Molex) or equivalent

Pin No. Symbol Description

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Model No.: V420H1 – LE1

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1 VLED 2 VLED 3 NC 4 NC 5 N1 6 N2 7 N3 8 N4 9 N5

Note (1) The backlight interface housing for high voltage side is a model 51281-0994, manufactured by Molex or

equivalent

. The mating header on converter part number is 51281-0994

Positive of LED String

No Connection

Negative of LED String

15

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5.3 CONVERTER UNIT

CN1(Header): CI0114M1HR0-LF (CvilLux) or equivalent

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

10

11 STAT U S

12 E_PWM External PWM control signal 13 I_PWM Internal PWM control signal 14 BLON Backlight on/off control

Notice:

VBL +24V Power input

GND Ground

Normal (3.3V) Abnormal (0V)

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Model No.: V420H1 – LE1

Preliminary

#PIN 12:PWM Dimming Control (Use Pin 12) : Pin 13 must open.

#PIN 13:Analog Dimming Control (Use Pin 13) : 0V~3.3V and Pin 12 must open.

#Pin 13(I_PWM) and Pin 12(E_PWM) can not open in same period.

CN2

~CN7: 51281-1294 (Molex) or equivalent

Pin No. Symbol Description

1 2 3 4 5 6 7 8 9

VLED VLED

NC NC

N1 N2 N3 N4 N5

Positive of LED String

No Connection

Negative of LED String

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5.4 BLOCK DIAGRAM OF INTERFACE

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Model No.: V420H1 – LE1

Preliminary

ARx0 +

ARx0 -

ARx1 +

ARx1 -

ARx2 +

ARx2 -

ARx3 +

ARx3 -

ARx4 +

ARx4 -

ACLK +

ACLK -

51

100pF

RxOUT

AR0 Ω AR9

AG0 Ω AG9

AB0 Ω AB9

DE

PLL

BRx0 +

BRx0 -

BRx1 +

BRx1 -

BRx2 +

BRx2 -

BRx3 +

BRx3 -

BRx4 +

BRx4 -

BCLK +

BCLK -

51

100pF

PLL

BR0 Ω BR9

BG0 Ω BG9

BB0 Ω BB9

DCLK

DCLK Timing Controller

LVDS Receiver (MASTER)

LVDS INPUT

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AR0~AR9: First pixel R data

AG0~AG9: First pixel G data

AB0~AB9: First pixel B data

BR0~BR9: Second pixel R data

BG0~BG9: Second pixel G data

BB0~BB9: Second pixel B data

DE: Data enable signal

DCLK: Data clock signal

The third and fourth pixel are followed the same rules.

CR0~CR9: Third pixel R data

CG0~CG9: Third pixel G data

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Model No.: V420H1 – LE1

Preliminary

CB0~CB9: Third pixel B data

DR0~DR9: Fourth pixel R data

DG0~DG9: Fourth pixel G data

DB0~DB9: Fourth pixel B data

Note (1) A ~ D channel are first, second, third and fourth pixel respectively.

Note (2) The system must have the transmitter to drive the module.

Note (3) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line

when it is used differentially.

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5.5 LVDS INTERFACE

VESA Format : SELLVDS = L or Open

JEIDA Format : SELLVDS = H

VESA Format

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Model No.: V420H1 – LE1

Preliminary

Current Cycle

AR 0P

AR 0N

AR 1P

AR 1N

AR 2P

AR 2N

AR 3P

AR 3N

AR 4P

AR 4N

JEIDA Format

AR 0P

AR 0N

AR 1P

AR 1N

AR0

AG1

AB2

AR6

AR4

AG5

AG0 AR5

AB1

DE VS HS AB5 AB4 AB3 AB2

REV AB7 AB6 AG7 AG6 AR7 AR6

REV AB9 AB8 AG9 AG8 AR9 AR8AR8 REV

AG4 AR7

AB5

AB0 AG5 AG4 AG3 AG2 AG1

AB4 AG7 AG6 AG5AG9 AG8

AR4 AR3 AR2 AR1 AR0

AR6 AR5 AR4AR9 AR8

AG0

AB1

DE

REV

AG4

AB5

AR 2P

AR 2N

AR 3P

AR 3N

AR 4P

AR 4N

AR0~AR9: First Pixel R Data (9; MSB, 0; LSB)

AG0~AG9: First Pixel G Data (9; MSB, 0; LSB)

AB0~AB9: First Pixel B Data (9; MSB, 0; LSB)

DE : Data enable signal

DCLK : Data clock signal

RSVD : Reserved

AB6

AR2

DE VS HS AB7 AB6AB9 AB8

REV AB3 AB2 AG3 AG2 AR3 AR2

REV AB1 AB0 AG1 AG0 AR1 AR0AR0 REV

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5.6 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 10-bit gray scale data input for the

color. The higher the binary input, the brighter the color. The table below provides the assignment of the color

versus data input.

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Data Signal

Basic

Colors

Gray

Scale

Of

Red

Color

Black

Red

Green

Blue

Cyan

Magenta

Yellow

White

Red (0) / Dark

Red (1)

Red (2)

:

Red (1021)

Red (1022)

Red Green Blue

R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 G9 G8 G7 G6 G5 G4 G3 G2 G1 G0 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

:

1

0

1

0

1

0

1

0

1

0

:

0

1

0

1

0

:

0

1

0

1

0

:

;

:

0

1

0

1

0

:

0

1

0

1

0

:

0

1

0

1

0

:

0

Gray

Scale

Of

Green

Gray

Scale

Of

Blue

Red (1023)

Green (0) / Dark

Green (1)

Green (2)

:

Green (1021)

Green (1022)

Green (1023)

Blue (0) / Dark

Blue (1)

Blue (2)

:

Blue (1021)

0

1

0

:

0

1

0

1

0

1

0

:

0

:

1

0

:

0

1

0

1

0

:

1

0

1

0

1

0

:

0

:

0

:

1

:

0

:

1

0

:

0

:

1

0

:

0

1

0

1

:

0

1

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Issued Date: Sep. 01, 2009

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Preliminary

Blue (1022)

Blue (1023)

Note (1) 0: Low Level Voltage, 1: High Level Voltage

0 0 0 0 0 0 0 0 0 0 0 0 0 000000000000000000000000001 1 1 1 1 1 1 1 1 1 111111110

10

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6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

(Ta = 25 ± 2 ºC)

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

LVDS

Receiver

Clock

LVDS

Receiver Data

Vertical

Frequency

Input cycle to

cycle jitter

Setup Time

Hold Time

Frame Rate

Total

1/Tc 60 74.25 80 MHz -

Trcl - - 200 ps -

Tlvsu 600 - - ps -

Tlvhd 600 - - ps -

- 120 - Hz

Tv 111 5 1125 1135 Th

Tv=Tvd+Tvb

Active Display

Term

Display

Blank

Horizontal

Active Display

Term

Note : Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low logic

Total

Display

Blank

Tvd 1080 1080 1080 Th -

Tvb 35 45 55 Th -

Th

Thd

Thb

525 550 575

480 480 480

45 70 95

Tc

Tc -

Th=Thd+Thb

level. Otherwise, this module would operate abnormally.

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INPUT SIGNAL TIMING DIAGRAM

Tvd Tvb

DE

Th

DCLK

Tc

DE

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Tv

Thb Thd

Data

Valid display data (960

LVDS INPUT INTERFACE TIMING DIAGRAM

RXCLK +

RXn +/-

Tlvsu Tlvhd

1T 14

3T 14

5T

14

Tc

7T 14

9T 14

11T

14

13T

14

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Љ

6.2 POWER ON/OFF SEQUENCE

(Ta = 25 ± 2 ºC)

To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the diagram

below.

0.5ЉT1Љ10ms

2

100ms

T

0 0 500ms

3

T

LVDS Signals

0ЉT7ЉT2

0

T

100ms

T

4

8

T3

0V

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T

2

Power On

T7

VA L I D

T

3T1

Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

0.1V

cc

T4

Power Off

T8

Option Signals

(SELLVDS,AGE ࿛)

Backlight (Recommended)

500ms

T

5

50%

5

T

6

T

Power ON/OFF Sequence

Note.

(1) The supply voltage of the external system for the module input should follow the definition of Vcc.

(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD operation

or the LCD turns off before the backlight turns off, the display may momentarily become abnormal screen.

(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance. If T2<0, that

maybe cause electrical overstress failures.

(4) T4 should be measured after the module has been fully discharged between power off and on period.

(5) Interface signal shall not be kept at high impedance when the power is on.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Ambient Temperature

Ambient Humidity

Supply Voltage

Input Signal

LED Current

Vertical Frame Rate

Ta

Ha

VCC 12 V

According to typical value in "3. ELECTRICAL CHARACTERISTICS"

IL 60 mA

Fr 120 Hz

25r2

50r10

oC

%RH

The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change

during measuring. In order to stabilize the luminance, the measurement should be executed after lighting

backlight for 1 hour in a windless room.

LCD Module

LCD Panel

CS-2000

Field of View = 1º

500 mm

Light Shield Room

(Ambient Luminance < 2 lu

25

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7.2 OPTICAL SPECIFICATIONS

The relative measurement methods of optical characteristics are shown in 7.2. The following items should be

measured under the test conditions described in 7.1 and stable environment shown in 7.1.

Item Symbol Condition Min. Typ. Max. Unit Note

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Contrast Ratio

Response Time

Center Luminance of White

White Variation

Cross Talk

Red

Green

Color

Chromaticit

y

Blue

White

CR 3000 4000 - - Note (2)

Gray to

gray

LC (400) 450 - cd/m2Note (4)

GW

CT - - (4) % Note (5)

Rx

Tx=0q, Ty =0q

Ry 0.344 -

Gx

Gy 0.615 -

Bx

By 0.050 -

Wx 0.280 -

Wy

Viewing angle

at normal direction

- 4.0 8.0 ms Note (3)

- - (1.3) - Note (6)

-

Typ. –

0.03

0.639

0.319

0.153

0.285

Typ+

0.03

-

Color Gamut

C.G

Tx+

68 72 - % NTSC

80 88 -

Horizontal

Viewing

Angle

Tx-

CRt20

TY+

80 88 -

Deg. Note (1)

80 88 -

Vertical

TY-

Note (1) Definition of Viewing Angle (Tx, Ty):

80 88 -

Viewing angles are measured by Conoscope Cono-80

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) =

CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (6).

pixels whiteall withLuminance Surface pixels black all withLuminance Surface

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(

)

A

(

)

(

)

A

Note (3) Definition of Gray-to-Gray Switching Time:

Optical Response

100 %

90 %

10 %

0 %

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Gray to Gray

Switching Time

Gray to Gray

Switching Time

Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

Time

The driving signal means the signal of gray level 0, 124, 252, 380, 508, 636, 764, 892 and 1023

Gray to gray average time means the average switching time of gray level 0, 124, 252, 380, 508, 636, 764,

892 and 1023 to each other .

Note (4) Definition of Luminance of White (L

Measure the luminance of gray level 255 at center point and 5 points

LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (6).

Note (5) Definition of Cross Talk (CT):

CT = | YB – YA | / YA u 100 (%)

Where:

YA = Luminance of measured location without gray level 0 pattern (cd/m2)

YB = Luminance of measured location with gray level 0 pattern (cd/m2)

Y

(D/8,W/2)

A, L

Y

(D/2,7W/8)

A, D

(0, 0)

ctive Area

Gray 128

Y

D,W

A, U

A, R

, L

):

C

AVE

(D/2,W/8)

(7D/8,W/2)

ʳ

ctive Area

Gray 0

Gray

0

Gray 128

Y

(D/2,W/8)

B, U

Y

(7D/8,W/2)

B, R

(3D/4,3W/4)

D,W

(D/4,W/4)

Y

(D/8,W/2)

B, L

(D/2,7W/8)

Y

B, D

0, 0

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Note (6) Definition of White Variation (GW):

Measure the luminance of gray level 255 at 5 points

GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]

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Preliminary

Horizontal Line

D

W

D

4

1 2

W

4

W

5

D

3D

2

4

X

Test point :

X = 1 ~ 5

2

Vertical Line

3 4

3W

4

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8. DEFINITION OF LABELS

8.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CHI MEI

OPTOELECTRONICS

V420H1 -LE1 Rev. XX

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

E207943

MADE IN TAIWAN

X X X X X X X Y M D L N N N N

(a) Model Name: V420H1-LE1

(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.

(c) Serial ID: X X X X X X X Y M D L N N N N

Serial ID includes the information as below:

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

Revision

CMO Internal Use

(a) Manufactured Date: Year: 0~9, for 2000~2009

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1

(b) Revision Code: Cover all the change

(c) Serial No.: Manufacturing sequence of product

(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.

st

to 31st, exclude I ,O, and U.

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9. PACKAGING

9.1 PACKING SPECIFICATIONS

(1) 5 LCD TV modules / 1 Box

(2) Box dimensions : 1085(L)x296(W)x653(H)mm

(3) Weight : Approx. 47.35Kg(5 modules per carton)

9.2 PACKING METHOD

Figures 9-1 and 9-2 are the packing method

LCD TV Module

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Model No.: V420H1 – LE1

Preliminary

Anti-Static Bag

Cushion(Bottom)

Carton

Cushion(Top)

PP Belt

Carton Label

Figure.9-1 packing method

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Sea / Land Transportation

(40ft Container)

Air Transportation

Figure.9-2 packing method

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Preliminary

10. PRECAUTIONS

10.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) Do not apply rough force such as bending or twisting to the module during assembly.

(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The

dust and oil may cause electrical short or worsen the polarizer.

(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and backlight.

(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the

damage and latch-up of the CMOS LSI chips.

(5) Do not plug in or pull out the I/F connector while the module is in operation.

(6) Do not disassemble the module.

(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and

easily scratched.

(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.

(9) High temperature or humidity may deteriorate the performance of LCD module. Please store LCD

modules in the specified storage conditions.

(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the

response time will become slow, and the starting voltage of LED light bar will be higher than that of room

temperature.

10.2 SAFETY PRECAUTIONS

(1) The startup voltage of a backlight is over 1000 Volts. It may cause an electrical shock while assembling

with the converter. Do not disassemble the module or insert anything into the backlight unit.

(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case

of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.

(3) After the module’s end of life, it is not harmful in case of normal operation and storage.

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11. MECHANICAL CHARACTERISTICS

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Issued Date: Sep. 01, 2009

Model No.: V420H1 – LE1

Preliminary

奇美電子股份有限公司

%*+/'+

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奇美電子股份有限公司

%*+/'+

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CMO V420H1-LE1 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual