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TFT LCD Approval Specification
MODEL NO.: V420H1 - L07
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Issue Date: Aug 05, 2008
Model No.:V420H1-L07
Approval
Customer: SONY
pproved by:
Note:
Approved By
Reviewed By
TV Head Division.
LY Chen
QA Dept. Product Development Div.
Tomy Chen WT Lin
Prepared By
One step solution for LCD / PDP / OLED panel application: Datasheet, inventory and accessory!
LCD TV Marketing and Product Management Div.
Wang-Yang Li Trina Lee
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Issue Date: Aug 05, 2008
Model No.:V420H1-L07
Approval
- CONTENTS -
1. GENERAL DESCRIPTION -------------------------------------------------------4
1.1 OVERVIEW
1.2 FEATURES
1.3 APPLICATION
1.4 GENERAL SPECIFICATIONS
1.5 MECHANICAL SPECIFICATIONS
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
2.2.2 BACKLIGHT INVERTER UNIT
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
3.2 BACKLIGHT UNIT
3.2.1 CCFL
3.2.2 INVERTER CHARACTERISTICS
3.2.3 INVERTER INTERFACE CHARACTERISTICS
(Cold Cathode Fluorescent Lamp) CHARACTERISTICS
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
5. V420H1-L07 LCD INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE INPUT
5.2 BACKLIGHT UNIT
5.3 INVERTER UNIT
5.4 BLOCK DIAGRAM OF INTERFACE
5.5 LVDS INTERFACE
5.6 COLOR DATA INPUT ASSIGNMENT
6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
6.2 POWER ON/OFF SEQUENCE
7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
7.2 OPTICAL SPECIFICATIONS
8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
8.2 SAFETY PRECAUTIONS
9.DEFINITION OF LABELS -------------------------------------------------------33
9.1 CMO MODULE LABEL
10. PACKAGING
10.1 PACKING SPECIFICATION.
10.2 PACKING METHOD
11.MECHANICAL CHARACTERISTICS --------------------------------------------------------36
------------------------------------------------------- 6
--------------------------------------------------------8
--------------------------------------------------------14
---------------------------------------------------------15
-------------------------------------------------------25
-------------------------------------------------------28
-------------------------------------------------------32
------------------------------------------------------34
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REVISION HISTORY
Version Date Page Section Description
Ver 0.0 July, 20,2006 All All Tentative Specification was first issued.
Ver.1.0 Sept.08, 2006 All All Preliminary. Spec. was first issued.
Ver.1.1 Nov,01, 2006 8 3.1 I
28 7.2 CRΙColor Chromaticity.
29 7.2 Note(2)
36 11 Mechanical Characteristics
Ver 2.0 Dec, 21, 2006 5 1.5 Weight
7 2.3 Note(3)
8 3.1 Power Supply Current(White)
10 3.2.2 Input Ripple Noise(Max.)=912 mV
12~13 3.2.3 INVERTER INTERFACE CHARACTERISTICS(Status Signal, VBL
14 4.1 TFT LCD MODULE (CN 23~ 27)
18 5.3 Inverter Unit (Pin 11~ 14) ;Note(1)~(3);
28 7.2 Color Chromaticity (R,G,B)
36~38 11 MECHANICAL CHARACTERISTICS
Ver 2.1 Mar, 27, 2007 8 3.1 I
34~35 10 PACKAGING
Ver 2.2 May, 17, 2007 4 1.2 contrast ratio 2000:1
28 7.2 contrast ratio 2000:1
Ver 2.3 June, 27, 2007 35 10.2 Figure 10-2
Ver 2.4 Dec, 27, 2007 5 1.5 Weight
25 6.1 INPUT SIGNAL TIMING SPECIFICATIONS
Ver 2.5 May, 06, 2008 35~37 11 MECHANICAL CHARACTERISTICS
Aug, 05, 2008 32 9.1 Modify Label from “MADE IN TAIWAN” to “MADE IN CHINA”
Aug, 05, 2008 33 10.1 Add “Desiccant”
ΙRush Current.
RUSH
P-P
Rising Time, VBL Falling Time ,PWM Delay Time, Note (1) )
(Max) 5.0 A
RUSH
Issue Date: Aug 05, 2008
Model No.:V420H1-L07
Approval
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V420H1-L07 is a 42” TFT Liquid Crystal Display module with 20-CCFL Backlight unit and 2ch-LVDS
interface. This module supports 1920 x 1080 HDTV format and can display true 16.7M colors (8-bit/color).
The inverter module for backlight is built-in.
1.2 FEATURES
- High brightness (500 nits)
- High contrast ratio (2000:1)
- Fast response time (˚˴ʳʳ˺˴ʳ˴˸˴˺˸ʳˉˁˈʳ)
- High color saturation (NTSC 72%)
- Full HDTV (1920 x 1080 pixels) resolution, true HDTV format
- DE (Data Enable) only mode
- LVDS (Low Voltage Differential Signaling) interface
- Optimized response time for 60 Hz frame rate
- Ultra wide viewing angle : Super MVA technology
- 180 degree rotation display option
- RoHS compliance
1.3 APPLICATION
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- Standard Living Room TVs.
- Public Display Application.
- Home Theater Application.
- MFM Application.
1.4 GENERAL SPECIFICATIONS
Item Specification Unit Note
Active Area 930.24(H) x 523.26 (V) (42.02” diagonal) mm
Bezel Opening Area 938.3 (H) x 531.3 (V) mm
Driver Element a-si TFT active matrix - Pixel Number 1920x R.G.B. x 1080 pixel Pixel Pitch(Sub Pixel) 0.1615 (H) x 0.4845 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors 16.7M color -
Display Operation Mode Transmissive mode / Normally black - -
Surface Treatment
Note (1) Please refer to the attached drawings in chapter 9 for more information about the front and
back outlines.
Note (2) The spec of the surface treatment is temporarily for this phase. CMO reserves the rights to
Anti-Glare coating (Haze 25%)
Hard coating (3H)
- (2)
(1)
change this feature.
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1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 982.3 983.0 984.0 mm
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Module Depth does not include connectors.
Vertical (V) 575.3 576.0 577.0 mm
Depth (D) 51.3 52.3 53.3 mm
Weight 12500 13000 13500 g -
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(1), (2)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
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Model No.:V420H1-L07
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Value
Min. Max.
- 50 G (3), (5)
NOP
- 1.0 G (4), (5)
NOP
Unit Note
display area from being over 65 ºC. The range of operating temperature may degrade in case of improper
thermal management in final product design.
Note (3) 11 ms, half sine wave, 1 time for ± X, ± Y, ± Z.
Note (4) 10 ~ 200 Hz, 10 min, 1 time each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough so that
the module would not be twisted or bent by the fixture.
2.2 ELECTRICAL ABSOLUTE RATINGS
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2.2.1 TFT LCD MODULE
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Issue Date: Aug 05, 2008
Model No.:V420H1-L07
Approval
Item Symbol
Min. Max.
Power Supply Voltage VCC -0.3 13.5 V
Logic Input Voltage VIN -0.3 3.6 V
Value
Unit Note
(1)
2.2.2 BACKLIGHT INVERTER UNIT
Item Symbol
Lamp Voltage VW
Power Supply Voltage VBL 0 30 V
Control Signal Level
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) No moisture condensation or freezing.
Note (3)The control signals include On/Off Control, Internal PWM Control, External PWM Control.
Ё
Value
Min. Max.
Ё
-0.3 7 V
3000 V
Unit Note
RMS
(1)
(1), (3)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE (Ta = 25 ± 2 ºC)
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Issue Date: Aug 05, 2008
Model No.:V420H1-L07
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Value
Parameter Symbol
Power Supply Voltage VCC 10.8 12 13.2 V (1)
Power Supply Ripple Voltage VRP - - 350 mV
Rush Current I
White 1.35 1.7 A
Power Supply Current
Differential Input High
Differential Input Low
LVDS
Interface
CMOS
interface
Common Input Voltage V
Terminating Resistor R
Input High Threshold Voltage VIH 2.7 - 3.3 V
Input Low Threshold Voltage V
Black 0.5 A
Vertical Stripe
Threshold Voltage V
Threshold Voltage V
RUSH
-
-
-
LVT H
LVT L
LVC
IL
Min. Typ. Max.
- - 5.0 A (2)
1.0 A
- - 100 mV
-100 - - mV
1.125 1.25 1.375 V
- 100 - ohm
T
0 - 0.7 V
Unit Note
(3)
Note (1) The module should be always operated within the above ranges.
Note (2) The duration of rush current is about 0.5mS and measurement condition is shown below:
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Note (3) The specified power supply current is under the conditions at Vcc = 12 V, Ta = 25 ± 2 ºC, f
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
whereas a power dissipation check pattern below is displayed.
a. White Pattern
b. Black Pattern
= 60 Hz,
v
c. Vertical Stripe Pattern
Active Area
Active Area
Active Area
G
R
R
B
G
R
B
G
R R
G
B
B
B
B
R
R
R
G
G
G
G
B
B
B
B
R
R
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3.2 BACKLIGHT UNIT
3.2.1 CCFL (Cold Cathode Fluorescent Lamp) CHARACTERISTICS (Ta = 25 ± 2 ºC)
Parameter Symbol
Lamp Input Voltage VL - 1520 - V
Lamp Current IL 5.3 5.8 6.3 mA
Lamp Turn On Voltage VS
Operating Frequency FL 40 - 70 KHz
Lamp Life Time LBL 50,000 60,000 - Hrs (2)
3.2.2 INVERTER CHARACTERISTICS (Ta = 25 ± 2 ºC)
Parameter Symbol
Power Consumption at
Gray level 255
Power Consumption at
Gray level 128
Power Consumption at
Gray level 0
Power Supply Voltage VBL 22.8 24 25.2 VDC
Power Supply Current IBL
Input Ripple Noise - - - 912 mV
Backlight Turn on
Voltage
Oscillating Frequency FW 47 50 53 kHz
Dimming frequency FB 150 160 170 Hz
Minimum Duty Ratio D
Note (1) Lamp current is measured by utilizing AC current probe and its value is average by measuring
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Model No.:V420H1-L07
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Value
Min. Typ. Max.
- -
- -
Value
2370
2160
Min. Typ. Max.
- 170 180 W (3)(4), IL =5.8mA
P
255
- 85 - W (5)
P
128
- 60 - W (5)
P
0
6.7 7.1 7.5 A Non Dimming
7.5 8.0 8.5 A Turn-on
V
BS
- 20 - %
MIN
2370
2160 - - V
- -
Unit Note
-
RMS
(1)
RMS
V
Ta = 0 ºC
RMS
Ta = 25 ºC
V
RMS
Unit Note
P-P
V
Ta = 0 ºC
RMS
Ta = 25 ºC
RMS
VBL=22.8V
master and slave board.
Note (2) The lamp starting voltage V
should be applied to the lamp for more than 1 second after startup.
S
Otherwise the lamp may not be turned on.
Note (3) The lamp frequency may produce interference with horizontal synchronous frequency of the
display input signals, and it may result in line flow on the display. In order to avoid interference, the
lamp frequency should be detached from the horizontal synchronous frequency and its harmonics
as far as possible.
Note (4) The life time of a lamp is defined as when the brightness is larger than 50% of its original value and
the effective discharge length is longer than 80% of its original length (Effective discharge length is
defined as an area that has equal to or more than 70% brightness compared to the brightness at the
center point of lamp.) as the time in which it continues to operate under the condition at Ta = 25 2
к and I
= 5.3~ 6.3mArms.
L
Note (6) The measurement condition of Max. value is based on 42" backlight unit under input voltage 24V,
average lamp current 6.1 mA and lighting 30 minutes later.
Note (7) The power consumption refers to the condition that Dynamic CR has been turned on.
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Model No.:V420H1-L07
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Inverter
(Master)
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
HV (White -)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink +)
2
HV (White -)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink +)
2
HV (White -)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink +)
2
HV (White -)
1
HV(Pink -)
2
HV (White +)
1
HV(Pink +)
2
LCD Module
HV (Pink +)
HV (White +)
HV (Pink -)
HV (White -)
HV (Pink +)
HV (White +)
HV (Pink -)
HV (White -)
HV (Pink +)
HV (White +)
HV (Pink -)
HV (White -)
HV (Pink +)
HV (White +)
HV (Pink -)
HV (White -)
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
A
1
2
A
Inverter
(Slavor)
A
A
A
A
HV(Blue -)
1
HV (Pink -)
2
HV(Blue +)
1
HV (Pink +)
2
HV (Pink +)
HV (White +)
HV (Pink -)
HV (White -)
A
1
2
A
A
1
2
A
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y
y
3.2.3 INVERTER INTERFACE CHARACTERISTICS
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Model No.:V420H1-L07
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Ё
0
0
0
1
Value
Ё
Ё
0
Ё
Ё
Ё
5.0 V
0.8 V
Ё
5.0 V duty on External PWM Control
0.8 V dut
0.8 V abnormal
100 ms
100 ms
50 us
50 us
ЁЁMӨ
Unit Note
V minimum dut
off
See as below
Parameter Symbol
On/Off Control Voltage
Voltage
Voltage
Status Signal
ON
OFF
MAX 2.85 3.0 3.15 V maximum duty ratioInternal PWM Control
MIN
HI 2.0
LO
HI 3.0 3.3 3.6 V normal
LO
V
BLON
V
IPWM
V
EPWM
Status
Condition
Te st
Ё
Ё
Ё
Ё
Ё
Min. Typ. Max.
2.0
VBL Rising Time Tr1 Ё 30 Ё Ё ms
VBL Falling Time Tf1 Ё 30 Ё Ё ms
Control Signal Rising Time Tr
Control Signal Falling Time Tf
PWM Signal Rising Time T
PWM Signal Falling Time T
PWMR
PWMF
Input impedance RIN
PWM Delay Time T
PWM
Ё 100 300 mS
ЁЁЁ
ЁЁЁ
ЁЁЁ
Ё Ё Ё
Ё
BLON Delay Time Ton Ё 300 Ё Ё ms
BLON Off Time T
Ё 300 Ё Ё ms
off
ratio
Note (1) The Dimming signal should be valid before backlight turns on by BLON signal. It is inhibited to
change the internal/external PWM signal during backlight turn on period.
Note (2) The power sequence and control signal timing are shown in the following figure.
Note (3) The power sequence and control signal timing must follow the figure below. For a certain reason,
the inverter has a possibility to be damaged with wrong power sequence and control signal timing.
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Model No.:V420H1-L07
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V
VBLON
V
EPWM
V
IPWM
Tr1
BL
2.0V
0.8V
2.0V
0.8V
3.0V
PWM
Ton
PWM
T
Backlight on duration
Tr
TPWMR
Tf
PWMF
T
External
PWM Duty
0
0
0
0
V
W
External
Period
Tf1
Toff
100%
Minimun
Duty
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)
4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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Model No.:V420H1-L07
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ERX0(+/-)
ERX1(+/-)
ERX2(+/-)
ERX3(+/-)
ECLK(+/-)
ORX0(+/-)
ORX1(+/-)
ORX2(+/-)
ORX3(+/-)
OCLK(+/-)
SELLVDS
RPF
ODSEL
DGMEN
DCREN
Vcc
GND
VBL
GND
Status
E_PWM
I_PWM
BLON
(FI-RE51S-HF (JAE))
INPUT CONNECTOR
CN27: 528520870 (Molex)
CN1.
CONNECTOR
CN1:S14B-PH-SM3-TB
(D)(LF) or equivalent
INVERTER
(Master)
FRAME
BUFFER
TIMING
CONTROLLER
DC/DC CONVERTER
& REFERENCE
VOLTAGE
GENERATOR
CN24,CN26: 528521070 (Molex)
CN3-CN22:SM02 (12.0)B-BHS-1-TB(LF)(JST)
or equivalent
BACKLIGHT
UNIT
SCAN DRIVER
DATA DRIVER (RSDS
CN2:S12B-PH-SM3-TB
(D)(LF) or equivalent
TFT LCD PANEL
(1920x3x1080)
INVERTER
CONNECTOR
(Slave)
CN2.
VBL
GND
CN23-CN25: 528521070 (Molex)
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
FI-RE51S-HF (JAE) or equivalent
Pin Name Description Note
1 N.C. No Connection
2 N.C. No Connection
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3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 SELLVDS LVDS data format Selection (2)
8 RPF Display Rotation (3)
9 ODSEL
10 DGMEN Dynamic Gamma Enable (5)
11 DCREN Dynamic Contrast Ratio Enable (6)
12 ORX0- Odd pixel Negative LVDS differential data input. Channel 0
13 ORX0+ Odd pixel Positive LVDS differential data input. Channel 0
14 ORX1- Odd pixel Negative LVDS differential data input. Channel 1
15 ORX1+ Odd pixel Positive LVDS differential data input. Channel 1
16 ORX2- Odd pixel Negative LVDS differential data input. Channel 2
17 ORX2+ Odd pixel Positive LVDS differential data input. Channel 2
18 GND Ground
Overdrive Lookup Table Selection
(1)
(4)
19 OCLK- Odd pixel Negative LVDS differential clock input.
20 OCLK+ Odd pixel Positive LVDS differential clock input.
21 GND Ground
22 ORX3- Odd pixel Negative LVDS differential data input. Channel 3
23 ORX3+ Odd pixel Positive LVDS differential data input. Channel 3
24 N.C. No Connection
25 N.C. No Connection
26 N.C. No Connection
27 N.C. No Connection
28 ERX0- Even pixel Negative LVDS differential data input. Channel 0
29 ERX0+ Even pixel Positive LVDS differential data input. Channel 0
30 ERX1- Even pixel Negative LVDS differential data input. Channel 1
31 ERX1+ Even pixel Positive LVDS differential data input. Channel 1
32 ERX2- Even pixel Negative LVDS differential data input. Channel 2
33 ERX2+ Even pixel Positive LVDS differential data input. Channel 2
34 GND Ground
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35 ECLK- Even pixel Negative LVDS differential clock input.
36 ECLK+ Even pixel Positive LVDS differential clock input.
37 GND Ground
38 ERX3- Even pixel Negative LVDS differential data input. Channel 3
39 ERX3+ Even pixel Positive LVDS differential data input. Channel 3
40 N.C. No Connection
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41 N.C. No Connection
(1)
42 N.C. No Connection
43 N.C. No Connection
44 GND Ground
45 GND Ground
46 GND Ground
47 GND Ground
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
Note (1) Reserved for internal use. Please leave it open.
Note (2)
Note (3) Low : normal display (default), High : display with 180 degree rotation
Note (4) Overdrive lookup table selection. The overdrive lookup table should be selected in accordance with the
Note (5) Low : function disable (default), High : Dynamic Gamma function enable.
Low : VESA LVDS Format (default), High : JEIDA Format.
frame rate to optimize image quality.
ODSEL Note
L Lookup table was optimized for 60 Hz frame rate.
H Lookup table was optimized for 50 Hz frame rate.
Note (6) Low : function disable (default), High :
Note (7) Low =Open or Connect to GND, High = Connect to +3.3V
Dynamic Contrast Ratio function enable.
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5.2 BACKLIGHT UNIT
The pin configuration for the housing and the leader wire is shown in the table below.
Pin Name Description Wire Color
1 HV High Voltage Pink
2 HV High Voltage White
Note (1) The backlight interface housing for high voltage side is a model BHR-04VS-1, manufactured by JST.
The mating header on inverter part number is SM02(12.0)B-BHS-1-TB(LF).
1 HV(White)
2 HV(Pink)
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CN3-CN22: BHR-04VS-1 (JST).
1 HV(Pink)
2 HV(White)
1 HV(White)
2 HV(Pink)
1 HV(White)
2 HV(Pink)
1 HV(Pink)
2 HV(White)
1 HV(Pink)
2 HV(White)
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5.3 INVERTER UNIT
CN1: S14B-PH-SM3-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
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3
4
5
6
7
8
9
10
11
12 E_PWM
13
14
VBL +24V
GND GND
Status
I_PWM Internal PWM Control Signal
BLON BL ON/OFF
Normal (3.3V)
Abnormal (GND)
External PWM Control Signal
Note (1) PIN 12:External PWM Control (Use Pin 12): Pin 13 must open.
Note (2) PIN 13:Intermal PWM Control (Use Pin 13): 0V~3.0V and Pin 12 must open.
Note (3) Pin 12(E_PWM) and Pin 13(I_PWM) can’t open in same period.
CN2: S12B-PH-SM3-TB(D)(LF)(JST) or equivalent
Pin Symbol Feature
1
2
3
4
5
6
7
8
9
10
11
12
CN3-CN22: SM02(12.0)B-BHS-1-TB(LF)(JST) or equivalent
Pin No. Symbol Description
1
2
CCFL HOT
CCFL HOT
VBL +24V
GND GND
NC NC
NC NC
CCFL high voltage
CCFL high voltage
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CN23-CN26: 528521070 (Molex)
Pin No. Symbol Description
1 Board to Board
2
3
4
5
6
7
8
9
10
528520870 (Molex)
CN27:
Pin No. Symbol Description
1 Board to Board
2
3
4
5
6
7
8
Note (1) Floating of any control signal is not allowed.
Control
Signal
Control
Signal
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
Board to Board
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G0-EG
0
G0-EG
0
r
0
p
ORx0
O
p
OG0
OB0
C
OG0
OB0
5.4 BLOCK DIAGRAM OF INTERFACE
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ERx0+
ER0-ER7
E
EB
7
-EB7
DE
OR0-OR7
-OG7
-OB7
D
LK
TxIN
PLL
ERx
ERx1+
ERx1-
ERx2+
ERx2-
ERx3+
ERx3-
ECLK+
Host
Graphics
Controller
ORx0+
ORx1+
ORx1-
51Ө
51Ө
51Ө
51Ө
51Ө
51Ө
51Ө
51Ө
100pF
100
100pF
100pF
F
-
RxOUT
ER0-ER7
E
EB
-EB7
DE
OR0-OR7
-OG7
7
-OB7
51Ө
-
100pF
51Ө
PLL
DCLK
Timing
51Ө
51Ө
51Ө
100pF
100
F
-
Controlle
LVDS Transmitter
THC63LVDM83A
(LVDF83A)
ER0~ER7 : Even pixel R data
PLL
ORx2+
Rx2-
ORx3+
ORx3-
OCLK+
51Ө
100pF
51Ө
51Ө
100pF
51Ө
51Ө
-
100pF
51Ө
LVDS Receiver
PLL
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EG0~EG7 : Even pixel G data
EB0~EB7 : Even pixel B data
OR0~OR7 : Odd pixel R data
OG0~OG7: Odd pixel G data
OB0~OB7 : Odd pixel B data
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) The system must have the transmitter to drive the module.
(2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when
it is used differentially.
(3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is even pixel
and the second pixel is odd pixel.
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5.5 LVDS INTERFACE
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Model No.:V420H1-L07
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24
bit
SIGNAL
LVDS_SEL
=L or OPEN
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
DE
R6
R7
G6
G7
B6
B7
RSVD 1
RSVD 2
RSVD 3
DCLK 31 TxCLK IN TxCLK OUT+
LVDS_SEL
=H
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
DE
R0
R1
G0
G1
B0
B1
RSVD 1
RSVD 2
RSVD 3
TRANSMITTER
THC63LVDM83
A
PIN INPUT Host TFT-LCD PIN OUTPUT
51
52
54
55
56
11
12
14
15
19
20
22
23
24
30
50
10
16
18
25
27
28
3
4
6
7
2
8
TxIN0
TxIN1
TxIN2
TxIN3
TxIN4
TxIN6
TxIN7
TxIN8
TxIN9
TxIN12
TxIN13
TxIN14
TxIN15
TxIN18
TxIN19
TxIN20
TxIN21
TxIN22
TxIN26
TxIN27
TxIN5
TxIN10
TxIN11
TxIN16
TxIN17
TxIN23
TxIN24
TxIN25
INTERFACE CONNECTOR
TA OUT0+
TA OUT0-
TA OUT1+
TA OUT1-
TA OUT2+
TA OUT2-
OUT3+
TA
TA OUT3-
TxCLK OUT-
Rx 0+
Rx 0-
Rx 1+
Rx 1-
Rx 2+
Rx 2-
Rx 3+
Rx 3-
RxCLK IN+
RxCLK IN-
RECEIVER
THC63LVDF84A
27
Rx OUT0
29
Rx OUT1
30
Rx OUT2
32
Rx OUT3
33
Rx OUT4
35
Rx OUT6
37
Rx OUT7
38
Rx OUT8
39
Rx OUT9
43
Rx OUT12
45
Rx OUT13
46
Rx OUT14
47
Rx OUT15
51
Rx OUT18
53
Rx OUT19
54
Rx OUT20
55
Rx OUT21
1
Rx OUT22
6
Rx OUT26
7
Rx OUT27
34
Rx OUT5
41
Rx OUT10
42
Rx OUT11
49
Rx OUT16
50
Rx OUT17
2
Rx OUT23
3
Rx OUT24
5
Rx OUT25
26 RxCLK
OUT
TFT CONTROL INPUT
LVDS_SEL
=L or OPEN
R0
R1
R2
R3
R4
R5
G0
G1
G2
G3
G4
G5
B0
B1
B2
B3
B4
B5
DE
R6
R7
G6
G7
B6
B7
NC
NC
NC
LVDS_SEL
=H
R2
R3
R4
R5
R6
R7
G2
G3
G4
G5
G6
G7
B2
B3
B4
B5
B6
B7
DE
R0
R1
G0
G1
B0
B1
NC
NC
NC
DCLK
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
DCLK : Data clock signal
Notes: (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
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5.6 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of the color
versus data input.
Color
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red (0) / Dark
Red (1)
Red (2)
:
:
Red (253)
Red (254)
Red (255)
Green (0) / Dark
Green (1)
Green (2)
:
:
Green (253)
Green (254)
Green (255)
Blue (0) / Dark
Blue (1)
Blue (2)
:
:
Blue (253)
Blue (254)
Blue (255)
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
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Data Signal
Red Green Blue
0
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
1
1
0
1
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
:
:
0
0
0
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
1
:
:
:
:
1
0
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1
1
1
0
1
0
0
0
:
:
0
0
0
0
0
0
:
:
0
0
0
0
0
0
:
:
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
:
:
:
:
:
:
1
0
1
1
1
0
1
1
1
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency 1/Tc 60 74.25 80 MHZ -
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LVDS Receiver Clock
LVDS Receiver Data
Vertical Active Display Term
Horizontal Active Display Term
Note (1) (ODSEL) = (H) , (L). Please refer to 5.1 for detail information.
Note (2) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (3) Total CLKmax(80MHz) > Htotal* Vtotal* frame frequency
Input cycle to
cycle jitter
Setup Time Tlvsu 400 - - ps -
Hold Time Tlvhd 400 - - ps -
Frame Rate
Total Tv 1115 1125 1450 Th Tv=Tvd+Tvb
Display Tvd 1080 1080 1080 Th -
Blank Tvb 35 45 370 Th -
Total Th 1050 1100 1200 Tc Th=Thd+Thb
Display Thd 960 960 960 Tc -
Blank Thb 90 140 240 Tc -
Trcl - - 200 ps -
Fr5 47 50 53 Hz (1)
Fr
6 57 60 63 Hz (1)
INPUT SIGNAL TIMING DIAGRAM
DE
Th
DCLK
Tc
DE
Tvd
Thb
Tv
Tvb
Thd
DATA
Valid display data ( 960 clocks)
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LVDS INPUT INTERFACE TIMING DIAGRAM
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RXCLK+
RXn+/-
Tlvsu
Tlvhd
1T‘
14
3T‘
14
5T‘
14
Tc
7T‘
14
9T‘
14
11T‘
14
13T‘
14
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Љ
Љ
Љ
Љ
Љ
Љ
6.2 POWER ON/OFF SEQUENCE
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should follow the
diagram below.
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Model No.:V420H1-L07
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Power Supply
V
0.5ЉT1Љ10ms
0
0
500ms
CC
0V
2
50ms
T
3
50ms
T
4
T
Signals
0V
Backlight (Recommended)
T
5
500ms
100msЉT6
0.9 VCC
0.1V
CC
Power On
CC
0.9 V
cc
0.1V
T
3 T1
T
2
T4
VALID
Power Off
50%
T
5
50%
T
6
Power ON/OFF Sequence
Note.
(1) The supply voltage of the external system for the module input should follow the definition of Vcc.
(2) Apply the lamp voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
(3) In case of VCC is in off level, please keep the level of input signals on the low or high impedance.
(4) T4 should be measured after the module has been fully discharged between power off and on
period.
(5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Lamp Current IL
Oscillating Frequency (Inverter) FW
Vertical Frame Rate Fr 60 Hz
7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown in 7.2. The following items should be
measured under the test conditions described in 7.1 and stable environment shown in Note (6).
Item Symbol Condition Min. Typ. Max. Unit Note
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25r2
50r10
5.8r0.5
50r3
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Model No.:V420H1-L07
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o
C
%RH
mA
KHz
CR 1800 2000 -
Contrast Ratio
Response Time
Center Luminance of White L
White Variation
Cross Talk CT - - 4 % Note (5)
Red
Green
Color
Chromaticity
Blue
White
Dynamic
CR
Gray to
gray
C
GW
T
=0q, TY =0q
x
Rx 0.632 -
Ry
Gx
Gy
Bx
By
Wx
Wy
Viewing angle at
normal direction.
- 6000 -
- 6.5 - ms Note (3)
400 500 - cd/m2 Note (4)
- - 1.3 - Note (7)
0.324
0.273
Typ.
-0.03
0.591
0.144
0.068
0.280
0.285
Typ.
+0.03
- Note (2)
-
-
-
-
-
-
-
Note (6)
Viewing
Angle
Color Gamut C.G
Horizontal
Vertical
Tx+
T
x
TY+
T
Y
-
-
CRt20
27
68 72 - % NTSC
80 88 -
80 88 -
Deg. Note (1)
80 88 -
80 88 -
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Note (1) Definition of Viewing Angle (Tx, Ty):
Viewing angles are measured by Eldim EZ-Contrast 160R
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TX- = 90º
x-
6 o’clock
T
y- = 90º
y-
Note (2) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Surface Luminance with all white pixels
Contrast Ratio (CR) =
Normal
Tx = Ty = 0º
Ty- Ty
Tx
Tx
y+
12 o’clock direction
T
y+ = 90º
x+
TX+ = 90º
Sruface Luminance with all black pixels
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note
(7).
The measurement value will be “Dynamic CR” only when the dynamic contrast ratio function is
enabled.
Note (3) Definition of Gray to Gray Switching Time :
100%
90%
Optical
Response
10%
0%
Gray to gray
switching time
Gray to gray
switching time
The driving signal means the signal of gray level 0, 63, 127, 191, and 255.
Time
Gray to gray average time means the average switching time of gray level 0, 63,127,191,255 to each
other.
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A
A
Note (4) Definition of Luminance of White (LC, L
Measure the luminance of gray level 255 at center point and 5 points
LC = L (5), where L (X) is corresponding to the luminance of the point X at the figure in Note (7).
Note (5) Definition of Cross Talk (CT):
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CT = | Y
Where:
Y
= Luminance of measured location without gray level 0 pattern (cd/m2)
A
Y
= Luminance of measured location with gray level 0 pattern (cd/m2)
B
(0, 0)
Y
(D/8,W/2)
A, L
Y
(D/2,7W/8)
A, D
Note (6) Measurement Setup:
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature
change during measuring. In order to stabilize the luminance, the measurement should be executed
after lighting backlight for 1 hour in a windless room.
– YA | / YA u 100 (%)
B
ctive Area
Gray 128
(D, W)
LCD Module
Y
(D/2,W/8)
A, U
Y
(7D/8,W/2)
A, R
(D/4,W/4)
Y
(D/8,W/2)
B, L
Y
(D/2,7W/8)
B, D
(0, 0)
ctive Area
Gray 0
Gray 0
Gray 128
Y
B, U
Y
B, R
(3D/4,3W/4)
(D, W)
(D/2,W/8)
(7D/8,W/2)
LCD Panel
Center of the Screen
Display Color Analyzer
(Minolta CA210)
Light Shield Room
(Ambient Luminance < 2 lux)
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Note (7) Definition of White Variation (GW):
Measure the luminance of gray level 255 at 5 points
GW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
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Horizontal Line
Vertical Line
W
W/4
W/2
3W/4
D/4 D/2 3D/4
12
34
D
5
Active Area
X
: Test Point
X=1 to 5
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8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
(1) Do not apply rough force such as bending or twisting to the module during assembly.
(2) It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
(3) Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
(4) Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
(5) Do not plug in or pull out the I/F connector while the module is in operation.
(6) Do not disassemble the module.
(7) Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and
easily scratched.
(8) Moisture can easily penetrate into LCD module and may cause the damage during operation.
(9) When storing modules as spares for a long time, the following precaution is necessary.
(a)Do not leave the module in high temperature, and high humidity for a long time. It is highly recommended to
store the module with temperature from 0 to 35кat normal humidity without condensation.
(b)The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
(10) When ambient temperature is lower than 10ºC, the display quality might be reduced. For example, the
response time will become slow, and the starting voltage of CCFL will be higher than that of room
temperature.
8.2 SAFETY PRECAUTIONS
(1) The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
(2) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case
of contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
(3) After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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CHI MEI
OPTOELECTRONICS
(a) Model Name: V420H1-L07
(b) Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
(c) Serial ID: X X
X X X X X Y M D L N N N N
V420H1 -L07 Rev. XX
X X X X X X X Y M D L N N N N
Serial No.
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
E207943
MADE IN TAIWAN
MADE IN CHINA
RoHS
Serial ID includes the information as below:
(a) Manufactured Date: Year: 0~9, for 2000~2009
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1
(b) Revision Code: Cover all the change
(c) Serial No.: Manufacturing sequence of product
(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.
CMO Internal Use
st
to 31st, exclude I ,O, and U.
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10. PACKAGING
10.1 packing specifications
(1) 3 LCD TV modules / 1 Box
(2) Box dimensions : 1080(L) X 282 (W) X 685(H)
(3) Weight : approximately 45Kg ( 3 modules per box)
(4) Desiccant ( Drier ) : Weight 30g / 1 piece, Quantity 3 pcs, Cobalt chloride free.
10.2 PACKING METHOD
Figures 10-1 and 10-2 are the packing method
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3pcs Drier
Cushion(Bottom)
LCD TV Module
Anti-static Bag
Carton
PP Belt
Carton Label
Figure.10-1 packing method
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Air Transportation & Sea / Land Transportation (40ft Container)
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(L1000*50*50mm)
Film
(L1150*W1085*H140mm)
(L1250*50*50mm)
Sea / Land Transportation (40ft HQ Container)
(L1000*50*50mm)
Film
(L1250*50*50mm)
Figure.10-2 Packing method
11. MECHANICAL CHARACTERISTICS
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