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V236H3-PS1
Specification
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CMO V236H3-PS1 Specification

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MODEL NO.: V236H3
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PRODUCT SPECIFICATION
□ Tentative Specification □ Preliminary Specification
■ Approval Specification
SUFFIX: PS1
Customer:
APPROVED BY SIGNATURE
Name / Title
Note
Please return 1 copy for your confirmation with your signature and comments.
Approved By Checked By Prepared By
Chao-Chun Chung Roger Huang CS Tsai
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PRODUCT SPECIFICATION
CONTENTS
1. GENERAL DESCRIPTION ......................................................................................................................................................... 5
1.1 OVERVIEW .......................................................................................................................................................... 5
1.2 FEATURES ..........................................................................................................................................................5
1.3 MECHANICAL SPECIFICATIONS....................................................................................................................... 5
2. ABSOLUTE MAXIMUM RATINGS .......................................................................................................................................... 6
2.1 ABSOLUTE RATINGS OF ENVIRONMENT........................................................................................................6
2.2 PACKAGE STORAGE.......................................................................................................................................... 7
2.3 ELECTRICAL ABSOLUTE RATINGS .................................................................................................................. 7
2.3.1 TFT LCD MODULE .................................................................................................................................... 7
3. ELECTRICAL CHARACTERISTICS ......................................................................................................................................... 8
3.1 TFT LCD MODULE ..............................................................................................................................................8
4. BLOCK DIAGRAM OF INTERFACE ...................................................................................................................................... 11
4.1 TFT LCD MODULE ............................................................................................................................................ 11
5. INTPUT TERMINAL PIN ASSIGNMENT ............................................................................................................................. 12
5.1 TFT LCD Module Input ....................................................................................................................................... 12
5.2 BLOCK DIAGRAM OF INTERFACE.................................................................................................................. 18
5.3 LVDS INTERFACE ............................................................................................................................................. 20
5.4 COLOR DATA INPUT ASSIGNMENT ................................................................................................................ 21
5.5 FLICKER (Vcom) ADJUSTMENT ...................................................................................................................... 23
6. INTERFACE TIMING................................................................................................................................................................ 24
6.1 INPUT SIGNAL TIMING SPECIFICATIONS...................................................................................................... 24
6.1.1 Timing spec for Frame Rate(F
6.1.2 Timing spec for Frame Rate(F
6.2 POWER ON/OFF SEQUENCE.......................................................................................................................... 28
= 100Hz) ...............................................................................................24
r5
= 120Hz) ...............................................................................................24
r6
6.2.1 POWER ON/OFF SEQUENCE(Ta = 25 ± 2 ºC) ......................................................................................28
6.2.2 2D to 3D SIGNAL SEQUENCE WITHOUT VCC TURN OFF AND TURN ON........................................ 29
7. OPTICAL CHARACTERISTICS............................................................................................................................................... 30
7.1 TEST CONDITIONS........................................................................................................................................... 30
7.2 OPTICAL SPECIFICATIONS .............................................................................................................................31
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PRODUCT SPECIFICATION
8. PRECAUTIONS .......................................................................................................................................................................... 36
8.1 ASSEMBLY AND HANDLING PRECAUTIONS ................................................................................................. 36
8.2 SAFETY PRECAUTIONS ..................................................................................................................................37
9. DEFINITION OF LABELS......................................................................................................................................................... 38
9.1 CMO MODULE LABEL ......................................................................................................................................38
10. PACKAGING............................................................................................................................................................................ 39
10.1 PACKAGING SPECIFICATIONS ..................................................................................................................... 39
10.2 PACKAGING METHOD.................................................................................................................................... 39
11. MECHANICAL CHARACTERISTIC .................................................................................................................................... 40
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Version Date Page(New) Section Description Ver. 2.0 Jan. 14, 2011 All All The approval specification was first issued.
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PRODUCT SPECIFICATION
REVISION HISTORY
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
V236H3-PS1 is a 23.6” TFT Liquid Crystal Display product with driver ICs and 4ch-LVDS interface. This product
supports 1920 x 1080 Full HDTV format and can display 16.7M colors (6 bit+FRC).
1.2 FEATURES
CHARACTERISTICS ITEMS SPECIFICATIONS
Screen Diagonal [in] 23.547
Pixels [lines] 1920 × 1080
Active Area [mm] 521.28(H) x 293.22(V) (23.547” diagonal)
Sub-Pixel Pitch [mm] 0.0905(H) x 0.2715(V)
Pixel Arrangement RGB vertical stripe
Weight [g] TYP. 685 g
Physical Size [mm] 534.56 (W) × 339.69 (H) ×2.9 (D) Typ.
Display Mode Transmissive mode / Normallly white
Contrast Ratio 1000:1 Typ.
Glass thickness (Array / CF) [mm] 0.7 / 0.7
Viewing Angle +85/-85(H), +80/-80(V) Typ. (CRЊ10)
Color Chromaticity R = (0.656, 0.328 )
Cell Transparency [%] 5.5%
Polarizer Surface Treatment Anti-Glare coating (Haze 25%), Hard coating (3H)
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PRODUCT SPECIFICATION
(Typical value measure at CMO’s module)
(Typical value measure at CMO’s module)
G = (0.272, 0.601 )
B = (0.147, 0.101 )
W= (0.323, 0.367 )
* Please refer to “color chromaticity” on p.31
1.3 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Weight 660 685 710 g -
I/F connector mounting position
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Note (2) Connector mounting position
The mounting inclination of the connector makes the screen center within ± 0.5mm as the horizontal.
(2)
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PRODUCT SPECIFICATION
2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Value
Item Symbol
Min. Max.
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 50 ºC (1), (2)
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The maximum operating temperature is based on the test condition that the surface temperature of
Unit Note
display area is less than or equal to 65 ºC with LCD module alone in a temperature controlled chamber.
Thermal management should be considered in final product design to prevent the surface temperature of
display area from being over 65 ºC. The range of operating temperature may degrade in case of
improper thermal management in final product design.
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2.2 PACKAGE STORAGE
When storing modules as spares for a long time, the following precaution is necessary.
(a) Do not leave the module in high temperature, and high humidity for a long time, It is highly recommended to
store the module with temperature from 0 to 35 к at normal humidity without condensation.
(b) The module shall be stroed in dark place. Do not store the TFT-LCD module in direct sunlight or fluorescent
light.
2.3 ELECTRICAL ABSOLUTE RATINGS
2.3.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 12.6 V
Logic Input Voltage VIN -0.3 3.6 V
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Max.
(1)
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3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE
(Ta = 25 ± 2 ºC)
Parameter Symbol
Power Supply Voltage VCC 10.8 12 12.6 V (1)
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PRODUCT SPECIFICATION
Value
Unit Note
Min. Typ. Max.
Rush Current I
White Pattern
Power Consumption
Horizontal Stripe
Black Pattern
White Pattern
Power Supply Current
Horizontal Stripe
Black Pattern
Differential Input High Threshold Voltage
Differential Input Low
Threshold Voltage LVDS interface
Common Input Voltage VCM 1.0 1.2 1.4 V
Differential input voltage
(single-end)
Terminating Resistor R
CMIS interface
Input High Threshold Voltage VIH 2.7
Input Low Threshold Voltage V
RUSH
ЁЁ
ЁЁ
ЁЁ
ЁЁ
ЁЁ
ЁЁ
ЁЁ
V
V
|V
LVTH
LVTL
ID
T
IL
+100
ЁЁ
| 200
Ё
0
3.8 A (2)
4.2 5.9 W
7.68 10.8 W
7.8 11 W
0.35 0.5 A
0.64 0.9 A
0.65 0.91 A
ЁЁ
mV
-100 mV
Ё
100
Ё
Ё
600 mV
Ё
ohm
3.3 V
0.7 V
(3)
(4)
Note (1) The module should be always operated within the above ranges.
Note (2) Measurement condition:
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PRODUCT SPECIFICATION
Vcc rising time is 470us
Vcc
0.9Vcc
0.1Vcc
GND
470us
Note (3) The specified power consumption and power supply current is under the conditions at Vcc = 12 V, Ta =
25 ± 2 ºC, f
= 120 Hz, whereas a power dissipation check pattern below is displayed.
v
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PRODUCT SPECIFICATION
a. White Pattern
Active Area
b. Black Pattern
Active Area
Note (4) The LVDS input characteristics are as follows:
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4. BLOCK DIAGRAM OF INTERFACE
4.1 TFT LCD MODULE
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PRODUCT SPECIFICATION
TFT LCD PANEL
(1920x3x1080)
INPUT CONNECTOR
(CNF2: FI-RE41S-HF JAE) or equivalent
CH3_0(+/-)
CH3_1(+/-)
CH3_2(+/-)
CH3_3(+/-)
CH3_CLK(+/-)
CH4_0(+/-)
CH4_1(+/-)
CH4_2(+/-)
CH4_3(+/-)
CH4_CLK(+/-)
X Board
C Board
CH1_0(+/-)
CH1_1(+/-)
CH1_2(+/-)
CH1_3(+/-)
CH1_CLK(+/-)
INPUT CONNECTOR
(CNF1: FI-RE51S-HF JAE) or equivalent
CH2_0(+/-)
CH2_1(+/-)
CH2_2(+/-)
CH2_3(+/-)
CH2_CLK(+/-)
SELLVDS
VCC
GND
L/R_O
B/L
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5. INTPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD Module Input
CNF1 Connector Pin Assignment: (FI-RE51S-HF(JAE) or equivalent)
Pin Name Description Note
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 L/R_O Output signal for Left Right Glasses control (7)
6 B/L
7 SELLVDS LVDS Data Format Selection (2)(6)
Output signal for backlight on/off control signal , H: B/L off, L: B/L on (3D only)
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PRODUCT SPECIFICATION
(1)
H: +3.3V
L: 0V
8 N.C. No Connection
9 N.C. No Connection
10 N.C. No Connection
11 GND Ground
12 CH1[0]- First pixel Negative LVDS differential data input. Pair 0
13 CH1[0]+ First pixel Positive LVDS differential data input. Pair 0
14 CH1[1]- First pixel Negative LVDS differential data input. Pair 1
15 CH1[1]+ First pixel Positive LVDS differential data input. Pair 1
16 CH1[2]- First pixel Negative LVDS differential data input. Pair 2
17 CH1[2]+ First pixel Positive LVDS differential data input. Pair 2
18 GND Ground
19 CH1CLK- First pixel Negative LVDS differential clock input.
20 CH1CLK+ First pixel Positive LVDS differential clock input.
21 GND Ground
(1)
22 CH1[3]- First pixel Negative LVDS differential data input. Pair 3
23 CH1[3]+ First pixel Positive LVDS differential data input. Pair 3
24 N.C. No Connection
25 N.C. No Connection
26 2D/3D Input signal for 2D/3D Mode Selection (3)(5)
27 LR Input signal for Left Right eye frame synchronous (4)(5)
28 CH2[0]- Second pixel Negative LVDS differential data input. Pair 0
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29 CH2[0]+ Second pixel Positive LVDS differential data input. Pair 0
30 CH2[1]- Second pixel Negative LVDS differential data input. Pair 1
31 CH2[1]+ Second pixel Positive LVDS differential data input. Pair 1
32 CH2[2]- Second pixel Negative LVDS differential data input. Pair 2
33 CH2[2]+ Second pixel Positive LVDS differential data input. Pair 2
34 GND Ground
35 CH2CLK- Second pixel Negative LVDS differential clock input.
36 CH2CLK+ Second pixel Positive LVDS differential clock input.
37 GND Ground
38 CH2[3]- Second pixel Negative LVDS differential data input. Pair 3
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PRODUCT SPECIFICATION
39 CH2[3]+ Second pixel Positive LVDS differential data input. Pair 3
40 N.C. No Connection
41 N.C. No Connection
42 NC No Connection
43 N.C. No Connection (1)
44 GND Ground
45 GND Ground
46 GND Ground
47 N.C. No Connection (1)
48 VCC +12V power supply
49 VCC +12V power supply
50 VCC +12V power supply
51 VCC +12V power supply
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PRODUCT SPECIFICATION
CNF2 Connector Pin Assignment (FI-RE41S-HF (JAE) or equivalent)
Pin Name Description Note
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 N.C. No Connection
5 N.C. No Connection
6 N.C. No Connection
7 N.C. No Connection
8 N.C. No Connection
(1)
9 GND Ground
10 CH3[0]- Third pixel Negative LVDS differential data input. Pair 0
11 CH3[0]+ Third pixel Positive LVDS differential data input. Pair 0
12 CH3[1]- Third pixel Negative LVDS differential data input. Pair 1
13 CH3[1]+ Third pixel Positive LVDS differential data input. Pair 1
14 CH3[2]- Third pixel Negative LVDS differential data input. Pair 2
15 CH3[2]+ Third pixel Positive LVDS differential data input. Pair 2
16 GND Ground
17 CH3CLK- Third pixel Negative LVDS differential clock input.
18 CH3CLK+ Third pixel Positive LVDS differential clock input.
19 GND Ground
20 CH3[3]- Third pixel Negative LVDS differential data input. Pair 3
21 CH3[3]+ Third pixel Positive LVDS differential data input. Pair 3
22 N.C. No Connection
23 N.C. No Connection
24 GND Ground
25 GND Ground
26 CH4[0]- Fourth pixel Negative LVDS differential data input. Pair 0
27 CH4[0]+ Fourth pixel Positive LVDS differential data input. Pair 0
28 CH4[1]- Fourth pixel Negative LVDS differential data input. Pair 1
29 CH4[1]+ Fourth pixel Positive LVDS differential data input. Pair 1
30 CH4[2]- Fourth pixel Negative LVDS differential data input. Pair 2
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31 CH4[2]+ Fourth pixel Positive LVDS differential data input. Pair 2
32 GND Ground
33 CH4CLK- Fourth pixel Negative LVDS differential clock input.
34 CH4CLK+ Fourth pixel Positive LVDS differential clock input.
35 GND Ground
36 CH4[3]- Fourth pixel Negative LVDS differential data input. Pair 3
37 CH4[3]+ Fourth pixel Positive LVDS differential data input. Pair 3
38 N.C. No Connection
39 N.C. No Connection
40 GND Ground
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PRODUCT SPECIFICATION
41 GND Ground
CN6 Connector Pin Assignment (LM123S-010-H-TF1-3 (UNE) or equivalent)
1 N.C. No Connection
2 N.C. No Connection
3 N.C. No Connection
4 GND Ground
5 B/L
6 L/R_O Output signal for Left Right Glasses control
7 N.C. No Connection
8 N.C. No Connection
9 N.C. No Connection
10 N.C. No Connection
Output signal for backlight on/off control signal , H: B/L off, L: B/L on (3D only)
H: +3.3V
L: 0V
(7)
Note (1) Reserved for internal use. Please leave it open.
Note (2) LVDS format selection.
L= Connect to GND , H=Connect to +3.3V or Open
SELLVDS Note
L JEDIA Format
H or Open VESA Format
Note (3) 2D/3D mode selection.
L= Connect to GND or Open, H=Connect to +3.3V
2D/3D Note
L or Open 2D Mode
H
3D Mode
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Note (4) Left Right synchronous signal for glasses.
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PRODUCT SPECIFICATION
V
Note (5) 2D/3D, and LR signal pin connected to the LCM side has the following diagram.
=0~0.8 V, VIH=2.0~3.3 V
IL
LR Note
L Right synchronous signal
H Left synchronous signal
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
Note (6) SELLVDS signal pin connected to the LCM side has the following diagram.
R1 in the system side should be less than 1K Ohm. (R1 < 1K Ohm)
Note (7) The definition of L/R_O signal as follows
L= 0V , H= +3.3V
L/R_O Note
L Right glass turn on
H Left glass turn on
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Note (8) LVDS 4-port Data Mapping
Port Channel of LVDS Data Stream
1st Port First Pixel 1, 5, 9, ……1913, 1917
2nd Port Second Pixel 2, 6, 10, ….1914, 1918
3rd Port Third Pixel 3, 7, 11, ….1915, 1919
4th Port Fourth Pixel 4, 8, 12, ….1916, 1920
Note (9) The screw hole which is distant from the connector is merged with Ground
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PRODUCT SPECIFICATION
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r
00
00
00
00
00
00
5.2 BLOCK DIAGRAM OF INTERFACE
TFT LCD Module Input
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PRODUCT SPECIFICATION
B_RXO0-
B_RXO0+
B_RXO1-
B_RXO1+
B_RXO2-
B_RXO2+
B_RXOC-
B_RXOC+
B_RXO3-
B_RXO3+
B_RXE0-
B_RXE0+
B_RXE1-
B_RXE1+
100Ω
100Ω
1
1
1
100Ω
100Ω
Timing
Controlle
Ω
Ω
Ω
PLL
B PATH
ER0-ER7
EG0-EG7
EB0-EB7
B_RXE2-
B_RXE2+
B_RXEC-
1
Ω
Ω
1
DE
OR0-OR7
OG0-OG7
B_RXEC+
OB0-OB7
B_RXE3-
B_RXE3+
Ω
1
PLL
DCLK
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G0-EG
00
00
00
00
00
00
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PRODUCT SPECIFICATION
F_RXO0-
F_RXO0+
F_RXO1-
F_RXO1+
F_RXO2-
F_RXO2+
F_RXOC-
F_RXOC+
F_RXO3-
F_RXO3+
F_RXE0-
F_RXE0+
F_RXE1-
F_RXE1+
100Ω
100Ω
1
1
1
100Ω
100Ω
F PATH
ER0-ER7
E
7
EB0-EB7
Ω
DE
Ω
OR0-OR7
OG0-OG7
Ω
PLL
OB0-OB7
DCLK
F_RXE2-
F_RXE2+
F_RXEC-
1
Ω
Ω
1
F_RXEC+
F_RXE3-
F_RXE3+
ER0~ER7 Even pixel R data OR0~OR7 Odd pixel R data EG0~EG7 Even pixel G data OG0~OG7 Odd pixel G data EB0~EB7 Even pixel B data OB0~OB7 Odd pixel B data
Note (1) The system must have the transmitter to drive the module.
Note (2) LVDS cable impedance shall be 50 ohms per signal line or about 100 ohms per twist-pair line when it is
Ω
1
PLL
DE Data enable signal DCLK Data clock signal
used differentially.
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PRODUCT SPECIFICATION
Note (3) Two pixel data send into the module for every clock cycle. The first pixel of the frame is odd pixel and the
second pixel is even pixel.
5.3 LVDS INTERFACE
JEIDA Format : SELLVDS = L
VESA Format : SELLVDS = H or Open
JEDIA Format
RXCLK
RXCLK
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
R7G2 R6 R5 R4 R3
R7G2 R6 R5 R4 R3
B2 G7B3
B2 G7B3
G5 G4G6
G5 G4G6
G5 G4G6
G5 G4G6
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
R2
R2
G3
G3
B4B6 B5B7VS HSDE
B4B6 B5B7VS HSDE
R0G0 R1G1B1 B0RSVD
R0G0 R1G1B1 B0RSVD
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VESA Format
RXCLK
RXCLK
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PRODUCT SPECIFICATION
Current F\FOH
Current F\FOH
ORX0
ORX0
ORX1
ORX1
ORX2
ORX2
ORX3
ORX3
ERX0
ERX0
ERX1
ERX1
ERX2
ERX2
ERX3
ERX3
R0~R7: Pixel R Data (7; MSB, 0; LSB)
G0~G7: Pixel G Data (7; MSB, 0; LSB)
B0~B7: Pixel B Data (7; MSB, 0; LSB)
DE : Data enable signal
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
R5G0 R4 R3 R2 R1
R5G0 R4 R3 R2 R1
B0 G5B1
B0 G5B1
G3 G2G4
G3 G2G4
G3 G2G4
G3 G2G4
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
R0
R0
G1
G1
B2B4 B3B5VS HSDE
B2B4 B3B5VS HSDE
R6G6 R7G7B7 B6RSVD
R6G6 R7G7B7 B6RSVD
DCLK : Data clock signal
Notes (1) RSVD (reserved) pins on the transmitter shall be “H” or “L”.
5.4 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 8-bit gray scale data input for the
color. The higher the binary input, the brighter the color. The table below provides the assignment of color
versus data input.
Data Signal
Basic Colors
Color
Black Red Green Blue Cyan Magenta Yel lo w White
R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4 B3 B2 B1 B0
0
0
1
1
0
0
0
0
0
0
1
1
1
1
1
1
Red Green Blue
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1 1 1 0 1
1
1
1
1
1
1
1
0
0
0
1
1
1
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0
Red(0) / Dark Red(1)
Red(2) Gray Scale Of Red
Gray Scale Of Green
Gray Scale Of Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Red(253)
Red(254)
Red(255)
Green(0) / Dark
Green(1)
Green(2)
Green(253)
Green(254)
Green(255)
Blue(0) / Dark
Blue(1)
Blue(2)
Blue(253)
Blue(254)
Blue(255)
: :
: :
: :
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
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PRODUCT SPECIFICATION
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
0
1
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
:
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
: :
: :
: :
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0 0
0
0
0
0
0
:
: :
:
1
1
1
1
1
1
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
:
:
:
:
:
:
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
:
:
:
:
:
:
1
0
1
0
1
1
1
1
1
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5.5 FLICKER (Vcom) ADJUSTMENT
(1) Adjustment Pattern:
2 line-inversion pattern was shown as below. If customer need below pattern, please directly contact with
Account FAE.
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PRODUCT SPECIFICATION
(2) Adjustment method: (Digital V-com)
Programmable memory IC is used for Digital V-com adjustment in this model. CMI provide Auto Vcom tools
to adjust Digital V-com.The detail connection and setting instruction, please directly contact with Account
FAE or refer CMI Auto V-com adjustment OI. Below items is suggested to be ready before Digital V-com
adjustment in customer LCM line.
a. USB Sensor Board.
b. Programmable software.
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
(Ta = 25 ± 2 ºC)
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item Symbol Min. Typ. Max. Unit Note
Frequency
Input cycle to
LVDS
Receiver
Clock
cycle jitter Spread spectrum
modulation range
Spread spectrum modulation frequency
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PRODUCT SPECIFICATION
F
clkin
(=1/TC)
T
- - 200 ps (3)
rcl
clkin_mo
F
d
F
- - 200 KHz
SSM
60 74.25 96.23 MHz
F
-2% - F
clkin
+2% MHz
clkin
(4)
LVDS
Setup Time Tlvsu 600 - - ps
Receiver
Data
Hold Time Tlvhd 600 - - ps
6.1.1 Timing spec for Frame Rate(Fr5 = 100Hz)
Total Tv 1115 1125 1135 Th
2D Mode
Ver t ical
Active
Display
Term
3D Mdoe
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Tv 1524 Th
Display Tvd 1080 Th
Blank Tvb 444 Th
Total Th 540 550 575 Tc
2D Mode
Horizontal
Active
Display
Term
Display Thd 480 480 480 Tc
Blank Thb 60 70 95 Tc
Total Th 525 Tc
(5)
Tv=Tvd+Tv
b
Ё
Ё
(6)
Th=Thd+T
hb
Ё
Ё
3D Mdoe
Display Thd 480 Tc
(7)
Blank Thb 45 Tc
6.1.2 Timing spec for Frame Rate(Fr6 = 120Hz)
Ver t ical
Active
Display
Term
2D Mode
3D Mdoe
Total Tv 1115 1125 1135 Th
Display Tvd 1080 1080 1080 Th
Blank Tvb 35 45 55 Th
Total Tv 1524 Th
Tv=Tvd+Tv
b
Ё
Ё
(6)
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Display Tvd 1080 Th
Blank Tvb 444 Th
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PRODUCT SPECIFICATION
Th=Thd+T
hb
Ё
Ё
(7)
Horizontal
Active
Display
Term
2D Mode
3D Mdoe
Total Th 540 550 575 Tc
Display Thd 480 480 480 Tc
Blank Thb 60 70 95 Tc
Total Th 525 Tc
Display Thd 480 Tc
Blank Thb 45 Tc
Note (1) Since the module is operated in DE only mode, Hsync and Vsync input signals should be set to low
logic level. Otherwise, this module would operate abnormally.
Note (2) Please make sure the range of pixel clock has follow the below equation:
F
clkin(max)
F
r
5
Tv Th FѼѼЊ
FЊ
r
6
Tv ThѼѼ
clkin(min)
INPUT SIGNAL TIMING DIAGRAM
DE
DCLK
DE
DATA
T
v
T
vd
T
h
T
c
T
hb
T
hd
T
vb
Valid display data ( 480 clocks)
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PRODUCT SPECIFICATION
Note (3) The input clock cycle-to-cycle jitter is defined as below figures. Trcl = I T1 – TI
Note (4) The SSCG (Spread spectrum clock generator) is defined as below figures.
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Note (5) The LVDS timing diagram and setup/hold time is defined and showing as the following figures.
LVDS RECEIVER INTERFACE TIMING DIAGRAM
RXCLK+/-
RXn+/-
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PRODUCT SPECIFICATION
Tc
Tlvsu
Tlvhd
1T
14
Note (6) Please fix the Vertical timing (Vertical Total =1524 / Display =1080 / Blank = 444) in 3D mode.
Note (7) Please fix the Horizontal timing (Horizontal Total =2100 / Display =1920 / Blank = 180) in 3D mode
3T
14
5T
14
7T
14
9T
14
11T
14
13T
14
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P
6.2 POWER ON/OFF SEQUENCE
6.2.1 POWER ON/OFF SEQUENCE(Ta = 25 ± 2 ºC)
To prevent a latch-up or DC operation of LCD module, the power on/off sequence should be as the diagram
below.
0V
0.5ЉЉЉЉT1ЉЉЉЉ10ms
0ЉЉЉЉT
500ms ЉЉЉЉT
0ЉЉЉЉT
2
ЉЉЉЉ50ms
3
ЉЉЉЉ50ms
4
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PRODUCT SPECIFICATION
0.1V
CC
T
1
T
2
0.1V
cc
T
3
T
4
LVDS Signals
0ЉЉЉЉT7ЉЉЉЉT
0ЉЉЉЉT8ЉЉЉЉT
0V
2
3
Option Signals
(SELLVDS,2D/3D, LR)
Backlight (Recommended)
500msЉЉЉЉT
100ms
5
ЉЉЉЉ
T6
Power On
T
7
50%
T
5
Power ON/OFF Sequence
50%
T
8
6
T
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ЉЉЉЉ
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PRODUCT SPECIFICATION
6.2.2 2D to 3D SIGNAL SEQUENCE WITHOUT VCC TURN OFF AND TURN ON
0.9V
0.1V
CC
CC
T
1
T
2
VCC
0.5ЉЉЉЉT1ЉЉЉЉ10ms
0ЉЉЉЉT
2
ЉЉЉЉ50ms
0V
LVDS Signals
0ЉЉЉЉT7ЉЉЉЉT2
10msЉЉЉЉT10
0ЉЉЉЉT9ЉЉЉЉ10ms
10ЉЉЉЉT12ЉЉЉЉ20ms
Scalar Black Pattern
Backlight ON/OFF 500msЉЉЉЉT 500ms
5
T11
0V
Power On
T
7
Scalar send
T
10
T
9
T
T
5
11
T
12
Note (1) The supply voltage of the external system for the module input should follow the definition of Vcc.
Note (2) Apply the LED voltage within the LCD operation range. When the backlight turns on before the LCD
operation or the LCD turns off before the backlight turns off, the display may momentarily become
abnormal screen.
Note (3) In case of Vcc is in off level, please keep the level of input signals on the low or high impedance. If
T2<0,that maybe cause electrical overstress failure.
Note (4) T4 should be measured after the module has been fully discharged between power off and on period.
Note (5) Interface signal shall not be kept at high impedance when the power is on.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
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PRODUCT SPECIFICATION
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 12 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
LED Current IL 60 ± 1.2 mA
Vertical Frame Rate Fr 120 Hz
The LCD module should be stabilized at given temperature for 1 hour to avoid abrupt temperature change during
measuring. In order to stabilize the luminance, the measurement should be executed after lighting backlight for 1
hour in a windless room.
LCD Module
LCD Panel
25±2
50±10
oC
%RH
500 mm
CS-2000
Light Shield Room
AmbientLuminance < 2lux)
(
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7.2 OPTICAL SPECIFICATIONS
The relative measurement methods of optical characteristics are shown as below. The following items
should be measured under the test conditions described in 7.1 and stable environment shown in 7.1.
Item Symbol Condition Min. Typ. Max. Unit Note
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PRODUCT SPECIFICATION
Red
Rcx 0.656 -
Rcy 0.328 -
Gcx 0.272 -
Color Chromaticity
Green
Gcy 0.601 -
Bcx 0.147 -
Blue
θ
=0°, θY =0°
x
Viewing Angle at Normal
Direction
Standard light source “C”
Typ-0.03
Typ+0.03
(0)
Bcy 0.107 -
Wcx 0.323 -
White
Wcy
Center Transmittance T% 4.9 5.5 - % (1),(6)
Contrast Ratio CR
T
R
Response Time
T
F
White Variation
δW
=0°, θY =0°
θ
x
with CMI module
θx=0°, θY =0°
with CMO Module
=0°, θY =0°
θ
x
with CMI module
1000
-
-
- - 1.33 - (1),(5)
0.367
- - (1),(3)
0.8 -
2.8 -
-
ms
(1),(4)
ms
2D - - - 4 % (7)
Cross Talk CT
3D-W - - 0.4 - % (8)
3D-D - - 12 - % (8)
θx+
-
85
-
Horizontal
Viewing Angle
θ
x
θY+
­CR≥10
With CMO module
-
-
85
80
­Deg. (1),(2)
-
Ver t ical
80
45
-
-
Deg. (9)
Absorption direction of the up polarizer
θ
-
Y
Φ
up
-
-
-
Note (0) Light source is the standard light source ”C” which is defined by CIE and driving voltage are based on
suitable gamma voltages. The calculating method is as following:
1. Measure Module’s and BLU’s spectrum at center point. White is without signal input and R,G,B are
with signal input. BLU is supplied by CMO.
2. Calculate cell’s spectrum.
3. Calculate cell’s chromaticity by using the spectrum of standard light source “C”.
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PRODUCT SPECIFICATION
Note (1) Light source is the BLU which supplied by CMI and driving voltage are based on suitable gamma
voltages.
Note (2) Definition of Viewing Angle (θx, θy):
Viewing angles are measured by Autronic Conoscope Cono-80 ( or Eldim EZ-Contrast 160R, 2 ᙇ 1 )
Normal
Γ x = Γ y = 0º
ΓX- = 90º
6 o’clock
Γ
y-
= 90º
x-
y-
Note (3) Definition of Contrast Ratio (CR):
The contrast ratio can be calculated by the following expression.
Contrast Ratio (CR) =
L255: Luminance of gray level 255
L 0: Luminance of gray level 0
CR = CR (5), where CR (X) is corresponding to the Contrast Ratio of the point X at the figure in Note (5).
Γ y- Γ
Γ x
y Γ
Γ x
12 o’clock direction
y+
Γ
y+
= 90º
ΓX+ = 90º
x+
L255 of Luminance Surface
L0 of Luminance Surface
Note (4) Definition of Response Time (T
100%
90%
Optical
Response
10%
0%
, TF):
R
Gray Level 255
Gray Level 255
Gray Level 0
T
R
T
F
Time
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A
(
)
A
(
)
(
)
Note (5) Definition of White Variation (δW):
Measure the luminance of gray level 255 at 5 points
δW = Maximum [L (1), L (2), L (3), L (4), L (5)] / Minimum [L (1), L (2), L (3), L (4), L (5)]
W
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PRODUCT SPECIFICATION
Vertical Line
Note (6) Definition of Transmittance (T%) :
Measure the luminance of gray level 255 at center point of LCD module.
Transmittance (T%) =
Note (7) Definition of Cross Talk (CT):
CT = | Y
Where:
Y
A
Y
B
(0, 0)
– YA | / YA× 100 (%)
B
= Luminance of measured location without gray level 0 pattern (cd/m2)
= Luminance of measured location with gray level 0 pattern (cd/m2)
ctive Area
Y
(D/2,W/8)
A, U
module LCD of Luminance
100%
×
unit backligh of Luminance
0, 0
(D/4,W/4
ctive Area
Y
(D/2,W/8)
B, U
Y
(D/8,W/2)
A, L
Gray 128
Y
Y
(D/2,7W/8)
A, D
(7D/8,W/2)
A, R
D, W
(D/8,W/2)
Y
B, L
Gray 0
Y
B, D
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Y
(7D/8,W/2)
B, R
(3D/4,3W/4)
(D/2,7W/8)
D, W
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J
J
J
Note(8) Definition of the 3D mode performance (measured under 3D mode):
a. Test pattern
Left eye image and right eye image are displayed alternated
WW
Left eye image: W255; Right eye image: W255
WB
Left eye image: W255; Right eye image: W0
BW
Left eye image: W0; Right eye image: W255
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PRODUCT SPECIFICATION
BB
Left eye image: W0; Right eye image: W0
b. Measurement setup
5LJKWH\H
5LJKWH\H
5LJKWH\H5LJKWH\H
VKXWWHU
VKXWWHU
VKXWWHU
Shutter glasses are well controlled under suitable timing, and measure the luminance of the center point
of the panel through the right eye glass. The transmittance of the glass should be larger than 40.0% under
3D mode operation.
ODVV
ODVV
ODVVVKXWWHUJODVV
The luminance of the test pattern “WW”, denoted L(WW); the luminance of the test pattern ”WB”, denoted
L(WB); the luminance of the test pattern “BW”, denoted L(BW); the luminance of the test pattern “BB”,
denoted “L(BB)
c. Definition of the Center Luminance of White, Lc (3D) : L(WW)
)()(
BBLWBL
d. Definition of the 3D mode white crosstalk, CT (3D-W) :
e. Definition of the 3D mode dark crosstalk, CT (3D-D) :
)3(
WDCT
≡−
)3(
DDCT
≡−
−
)()(
BBLWWL
−
)()(
BWLWWL
−
)()(
BBLWWL
−
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Note (9) This is a reference for designing the shutter glasses of 3D application. (TN case)
Definition of the absorption direction of the up polarizer:
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PRODUCT SPECIFICATION
x-
Φ
up
6 o’clock
The absorption axis of the front polarizer of the shutter glasses should be parallel to this panel absorption
direction to get a maximum 3D mode luminance.
y-
12 o’clock direction
y+
o
, x
Φ=0
+
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PRODUCT SPECIFICATION
8. PRECAUTIONS
8.1 ASSEMBLY AND HANDLING PRECAUTIONS
[ 1 ] Do not apply rough force such as bending or twisting to the module during assembly.
[ 2 ] It is recommended to assemble or to install a module into the user’s system in clean working areas. The
dust and oil may cause electrical short or worsen the polarizer.
[ 3 ] Do not apply pressure or impulse to the module to prevent the damage of LCD panel and Backlight.
[ 4 ] Always follow the correct power-on sequence when the LCD module is turned on. This can prevent the
damage and latch-up of the CMOS LSI chips.
[ 5 ] The distance between COF edge and rib of BLU must bigger than 5mm. This can prevent the damage of
COF when assemble the module.
[ 6 ] Do not design sharp-pointed structure / parting line / tooling gate on the COF position of plastic parts,
because the burr will scrape the COF.
[ 7 ] If COF would bended to assemble in the module. Do not put the IC location on the bending corner of COF.
[ 8 ] The gap between COF IC and any structure of BLU must bigger than 2mm. This can prevent the damage of
COF IC
[ 9 ] Bezel opening must have no burr. Burr will scrape the panel surface.
[ 10 ] Bezel of module and bezel of set can not press or touch the panel surface. It will make light leakage or
scrape. When module used FFC / FPC, but no FFC / FPC to be attached in the open cell. Customer can
refer the FFC / FPC drawing and buy it by self.
[ 11 ] The gap between Panel and any structure of Bezel must bigger than 2mm. This can prevent the damage of
Panel.
[ 12 ] Do not plug in or pull out the I/F connector while the module is in operation.
[ 13 ] Do not disassemble the module.
[ 14 ] Use a soft dry cloth without chemicals for cleaning, because the surface of polarizer is very soft and easily
scratched.
[ 15 ] Moisture can easily penetrate into LCD module and may cause the damage during operation.
[ 16 ] When storing modules as spares for a long time, the following precaution is necessary.
[ 16.1 ] Do not leave the module in high temperature, and high humidity for a long time. It is highly
recommended to store the module with temperature from 0 to 35кat normal humidity without
condensation.
[ 16.2 ] The module shall be stored in dark place. Do not store the TFT-LCD module in direct sunlight or
fluorescent light.
[ 17 ] When ambient temperature is lower than 10ºC, the display quality might be reduced.
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PRODUCT SPECIFICATION
8.2 SAFETY PRECAUTIONS
[ 1 ] The startup voltage of a Backlight is approximately 1000 Volts. It may cause an electrical shock while
assembling with the inverter. Do not disassemble the module or insert anything into the Backlight unit.
[ 2 ] If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In case of
contact with hands, skin or clothes, it has to be washed away thoroughly with soap.
[ 3 ] After the module’s end of life, it is not harmful in case of normal operation and storage.
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9. DEFINITION OF LABELS
9.1 CMO MODULE LABEL
The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.
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PRODUCT SPECIFICATION
CHI MEI
OPTOELECTRONICS
CHI MEI
OPTOELECTRONICS
Model Name: V236H3-PS1
Revision: Rev. XX, for example: A0, A1… B1, B2… or C1, C2…etc.
Serial ID: X X X X X X X Y M D L N N N N
V236H3 –PS1 Rev. XX
V236H3 –PS1 Rev. XX
Serial No.
E207943
MADE IN TAIWAN
MADE IN CHINA
LEOO(or CAPG or CANO)
RoHS
Product Line
Year, Month, Date
CMO Internal Use
CMO Internal Use
Revision
Serial ID includes the information as below:
Manufactured Date:
Year: 2010=0, 2011=1,2012=2…etc.
Month: 1~9, A~C, for Jan. ~ Dec.
Day: 1~9, A~Y, for 1st to 31st, exclude I ,O, and U.
Revision Code: Cover all the change
Serial No.: Manufacturing sequence of product
Product Line: 1 -> Line1, 2 -> Line 2, …etc.
CMO Internal Use
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10. PACKAGING
10.1 PACKAGING SPECIFICATIONS
(1) 24 open cells / 1 Box
(2) Box dimensions : 670(L)x575(W)x325(H)mm
(3) Weight : approximately 24Kg (24 open cells per box)
10.2 PACKAGING METHOD
Figures 10-1 and 10-2 are the packing method
Dvtijpo)Tqbdfs*!
!qbofm
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PRODUCT SPECIFICATION
Upq!mbzfs!gps!fnquz!usbz!
Ubqf
!!Usbz
!!!4!Qbofmt0Usbz
Dvtijpo)FQF!Cpbse*!
QQ!Cpbse!
!Cbh
Figure.10-1 packing method
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PRODUCT SPECIFICATION
11. MECHANICAL CHARACTERISTIC
Figure.10-2 packing method
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