CMO N156B3-L01 Specification

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TFT LCD Approval Specification

MODEL NO.: N156B3-L01

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Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

Customer : Dell

pproved by :

Note :

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2008-08-14

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PMMD III

Director

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Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

- CONTENTS -

REVISION HISTORY

1. GENERAL DESCRIPTION

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

2.2.2 BACKLIGHT UNIT

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

4. BLOCK DIAGRAM

4.1 TFT LCD MODULE

4.2 BACKLIGHT UNIT

5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT

5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL

5.4 COLOR DATA INPUT ASSIGNMENT

5.5 EDID DATA STRUCTURE

5.6 EDID SIGNAL SPECIFICATION

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

6.2 POWER ON/OFF SEQUENCE

7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

7.2 OPTICAL SPECIFICATIONS

8. PRECAUTIONS

8.1 HANDLING PRECAUTIONS

8.2 STORAGE PRECAUTIONS

8.3 OPERATION PRECAUTIONS

9. PACKING ------------------------------------------------------- 25

9.1 CARTON

9.2 PALLET

10. DEFINITION OF LABELS

10.1 DELL 2D LABEL

10.2 CMO MODULE LABEL

10.3 CARTON LABEL

------------------------------------------------------- 3

------------------------------------------------------- 4

------------------------------------------------------- 5

------------------------------------------------------- 7

------------------------------------------------------- 11

------------------------------------------------------- 12

------------------------------------------------------- 18

------------------------------------------------------- 20

------------------------------------------------------- 24

------------------------------------------------------- 27

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Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

REVISION HISTORY

Version Date

Ver. 3.0 Jul. 11, 2008

Page

(New)

All

Section Description

Approval Specification was first issued.

All

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1. GENERAL DESCRIPTION

1.1 OVERVIEW

N156B3-L01 is a 15.6” TFT Liquid Crystal Display module with single CCFL Backlight unit and 30 pins

LVDS interface. This module supports 1366 x 768 Wide-XGA mode and can display 262,144 colors. The

optimum viewing angle is at 6 o’clock direction. The inverter module for Backlight is not built in.

1.2 FEATURES

- Thin and light weight

- WXGA (1366 x 768 pixels) resolution

- 3.3V LVDS (Low Voltage Differential Signaling) interface with 1 pixel/clock

1.3 APPLICATION

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Model No.: N156B3-L01

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- TFT LCD Notebook

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note
Active Area 344.232(H) × 193.536(V) (15.6” diagonal) mm
Bezel Opening Area 348.43 (H) x 197.74 (V) mm
Driver Element a-si TFT active matrix - ­Pixel Number 1366 x R.G.B. x 768 pixel ­Pixel Pitch 0.252 (H) x 0.252 (V) mm ­Pixel Arrangement RGB vertical stripe - ­Display Colors 262,144 color ­Transmissive Mode Normally white - ­Surface Treatment Hard coating (3H), Anti-glare - -

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal(H) 358.8 359.3 359.8 mm

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Vertical(V) 209 209.5 210 mm
Thickness(T) --- 5.9 6.2 mm

Weight --- 500 515 g -

(1)

(1)

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A

2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V

Note (1) (a) 90 %RH Max. (Ta <= 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The temperature of panel surface should be 0 ºC min. and 50 ºC max.

Relative Humidity (%RH)

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Model No.: N156B3-L01

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Value

Min. Max.

- 220/2 G/ms (3), (5)

NOP

- 1.5 G (4), (5)

NOP

Unit Note

100

90

80

60

Operating Range

40

20
10

Storage Range

8060-20 400 20-40

Temperature (ºC)

Note (3) 1 time for ± X, ± Y, ± Z. for Condition (200G / 2ms) is half Sine Wave,.

Note (4) 10~500 Hz, 0.5hr/cycle 1cycle for X,Y,Z

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid

enough so that the module would not be twisted or bent by the fixture.

The fixing condition is shown as below:

t Room Temperature

Side Mount Fixing Screw

Gap=2mm

Bracket

LCD Module

Side Mount Fixing Screw

Stage

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

Item Symbol

Power Supply Voltage Vcc -0.3 +4.0 V
Logic Input Voltage VIN -0.3 Vcc+0.3 V

2.2.2 BACKLIGHT UNIT

Item Symbol

Lamp Voltage VL - 2.5K V
Lamp Current IL - 7.0 mA
Lamp Frequency FL 50 80 KHz

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

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Value

Min. Max.

Value

Min. Max.

Unit Note

Unit Note

Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

(1)

(1), (2), IL = 6.0 mA

RMS

RMS

(1), (2)

Note (2) Specified values are for lamp (Refer to Section 3.2 for further information).

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Model No.: N156B3-L01

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE Ta = 25 ± 2 ºC

Parameter Symbol

Min. Typ. Max.
Power Supply Voltage Vcc 3.0 3.3 3.6 V ­Ripple Voltage VRP - 50 mV ­Rush Current I

- - 1.5 A (2)

RUSH

Initial Stage Current IIS - - 1.0 A (2)

Power Supply Current

LVDS Differential Input High Threshold V

LVDS Differential Input Low Threshold V

White - 320 mA (3)a
Black

lcc

TH(LVDS)

-100 - - mV

TL(LVDS)

- 390 450 mA (3)b

- - +100 mV

LVDS Common Mode Voltage VCM 1.125 - 1.375 V (5)
LVDS Differential Input Voltage |VID| 100 - 600 mV (5)
Terminating Resistor RT - 100 - Ohm -

Power per EBL WG P

- 3.58 - W (4)

EBL

Note (1) The ambient temperature is Ta = 25 ± 2 ºC.

Value

Unit Note

Approval

(5),

=1.2V

V

CM

(5)

=1.2V

V

CM

Note (2) I

Measurement Conditions: Shown as the following figure. Test pattern: black.

: the maximum current when VCC is rising

RUSH

I

: the maximum current of the first 100ms after power-on

IS

+3.3V

R1

47K

Q1 2SK1475

FUSE

C3

1uF

(High to Low)

(Control Signal)

SW

+12V

C1

1uF

VR1

R2

1K

47K

0.01uF

Q2

2SK1470

C2

Vcc rising time is 470us

+3.3V

VCC

Vcc

(LCD Module Input)

0V

470us

0.1Vcc

I

RUSH

100ms

I

IS

ICC

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|

|

Note (3) The specified power supply current is under the conditions at Vcc = 3.3 V, Ta = 25 ± 2 ºC, DC

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Doc No.:

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Model No.: N156B3-L01

Approval

Current and f

Note (4) The specified power are the sum of LCD panel electronics input power and the inverter input

a. White Pattern

power. Test conditions are as follows.

(a) Vcc = 3.3 V, Ta = 25 ± 2 ºC, f

(b) The pattern used is a black and white 32 x 36 checkerboard, slide #100 from the VESA file

“Flat Panel Display Monitor Setup Patterns”, FPDMSU.ppt.

= 60 Hz, whereas a power dissipation check pattern below is displayed.

v

b. Black Pattern

Active Area

= 60 Hz,

v

Active Area

(c) Luminance: 60 nits.

(d) The inverter used is provided from Sumida

Note (5) The parameters of LVDS signals are defined as the following figures.

Single Ended

Differential

CM

V

0V

V

0V

V

.

VID|

VID|

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Approval

3.2 BACKLIGHT UNIT Ta = 25 ± 2 ºC

Parameter Symbol

Min. Typ. Max.

Lamp Input Voltage VL 650 730 820 V

Lamp Current IL

Lamp Turn On Voltage VS

2.0 (1),(2)

3.0

- - 1460(25

- - 1600(0
Operating Frequency FL 50 - 80 KHz (5)
Lamp Life Time LBL 15,000 - - Hrs (7)
Power Consumption PL - 4.38 - W (6), IL = 6.0 mA

Note (1) Lamp current is measured by utilizing a high frequency current meter as shown below:

Value

Unit Note

6.0 (7.0) mA

o

C) V

o

C) V

IL = 6.0 mA

RMS

RMS

(4)

RMS

(4)

RMS

(1),(3)

LCD

Module

HV (Pink)

LV (White)

1

2

Current Meter

Inverter

A

Note (2) for burst mode inverter design

Note (3) for continuous mode inverter design

Note (4) The voltage that must be larger than Vs should be applied to the lamp for more than 1 second

after startup. Otherwise, the lamp may not be turned on normally.

Note (5) The lamp frequency may generate interference with horizontal synchronous frequency from the

display, and this may cause line flow on the display. In order to avoid interference, the lamp

frequency should be detached from the horizontal synchronous frequency and its harmonics as far

as possible.

Note (6) P

= IL VL

L

Note (7) The lifetime of lamp is defined as the time when it continues to operate under the conditions at Ta

= 25 2

o

C and IL = 6.0 mA

until one of the following events occurs:

RMS

(a) When the brightness becomes Љ 50% of its original value.

(b) When the effective ignition length becomes Љ 80% of its original value. ʻ˧˻˸ʳ ˸˹˹˸˶˼˸ʳ ˼˺˼˼ʳ

˿˸˺˻ʳ˼ʳ˴ʳ˶˸ʳ˻˴ʳ˿˼˴˶˸ʳ˼ʳ˸ʳˊ˃ʸʳ˹ʳ˻˴ʳ˴ʳ˻˸ʳ˶˸˸ʳ˼ˁʼ

Note (8) The waveform of the voltage output of inverter must be area-symmetric and the design of the

inverter must have specifications for the modularized lamp. The performance of the Backlight,

such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for

the lamp. All the parameters of an inverter should be carefully designed to avoid generating too

much current leakage from high voltage output of the inverter. When designing or ordering the

inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the

inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module

should be operated in the same manners when it is installed in your instrument.

The output of the inverter must have symmetrical (negative and positive) voltage waveform and

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symmetrical current waveform.(Unsymmetrical ratio is less than 10%) Please do not use the inverter,

which has unsymmetrical voltage and unsymmetrical current and spike wave. Lamp frequency may

produce interface with horizontal synchronous frequency and as a result this may cause beat on the

display. Therefore lamp frequency shall be as away possible from the horizontal synchronous

frequency and from its harmonics in order to prevent interference.

Requirements for a system inverter design, which is intended to have a better display performance, a

better power efficiency and a more reliable lamp. It shall help increase the lamp lifetime and reduce its

leakage current.

a. The asymmetry rate of the inverter waveform should be 10% below;

b. The distortion rate of the waveform should be within Ѕ2 ± 10%;

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Model No.: N156B3-L01

Approval

c. The ideal sine wave form shall be symmetric in positive and negative polarities.

* Asymmetry rate:

I p

I -p

| I

* Distortion rate

I

– I –p | / I

p

(or I –p) / I

p

rms

rms

* 100%

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)

4. BLOCK DIAGRAM

4.1 TFT LCD MODULE

LVDS Display

Data & Clock

Vcc

INPUT CONNECTOR

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LVDS INPUT /

TIMING CONTROLLER

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Model No.: N156B3-L01

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SCAN DRIVER IC

TFT LCD PANEL

GND

Data

EDID

CLK

EDID

V

EDID

VL

LAMP CONNECTOR

4.2 BACKLIGHT UNIT

DC/DC CONVERTER &

REFERENCE VOLTAGE

GENERATOR

EDID

EEPROM

DATA DRIVER IC

BACKLIGHT UNIT

1 HV (Pink)

2 LV (White

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5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE

Pin Symbol Description Polarity Remark

1 Vss Ground
2 Vcc Power Supply +3.3 V (typical)
3 Vcc Power Supply +3.3 V (typical)
4 V
5 NC Non-Connection
6 CLK
7 DATA
8 Rxin0- LVDS Differential Data Input Negative

9 Rxin0+ LVDS Differential Data Input Positive

10 Vss Ground

11 Rxin1- LVDS Differential Data Input Negative

12 Rxin1+ LVDS Differential Data Input Positive

13 Vss Ground
14 Rxin2- LVDS Differential Data Input Negative B2~B5, DE, Hsync, Vsync

15 Rxin2+ LVDS Differential Data Input Positive
16 Vss Ground
17 CLK- LVDS Clock Data Input Negative
18 CLK+ LVDS Clock Data Input Positive
19 Vss Ground
20 NC Non-Connection
21 NC Non-Connection
22 Vss Ground
23 NC Non-Connection
24 NC Non-Connection
25 Vss Ground
26 NC Non-Connection
27 NC Non-Connection
28 Vss Ground
29 NC Non-Connection
30 NC Non-Connection

Note (1) Connector Part No.: JAE FI-XB30SL-HF10 or equivalent

DDC 3.3V Power DDC 3.3V Power

EDID

DDC Clock DDC Clock

EDID

DDC Data DDC Data

EDID

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R0~R5,G0

G1~G5, B0, B1

LVDS Level Clock

Note (2) User’s connector Part No: JAE-FI-X30M or equivalent

Note (3) The first pixel is odd as shown in the following figure.

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5.2 BACKLIGHT UNIT

Pin Symbol Description Color

1 HV High Voltage Pink
2 LV Ground White

Note (1) Connector Part No.: JST-BHSR-02VS-1 or equivalent

Note (2) User’s connector Part No.: JST-SM02B-BHSS-1-TB or equivalent.

5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL

CLK+

Rxin2

Rxin1

Rxin0

T/7

IN20 IN19 IN18 IN17 IN16 IN15 IN14

DE B5 B4 B3 B2 Vsync Hsync

IN13 IN12 IN11 IN10 IN9 IN8 IN7

B1 G4 G3 G2 G1 B0 G5

IN6 IN5 IN4 IN3 IN2 IN1 IN0

G0 R3 R2 R1 R0

R5

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R4

Signal for 1 DCLK Cycle (T)

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5.4 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for

the color. The higher the binary input the brighter the color. The table below provides the assignment of

color versus data input.

Color

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black
Red
Green

Basic
Colors

Gray
Scale
Of
Red

Gray
Scale
Of
Green

Gray
Scale
Of
Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Blue
Cyan
Magenta
Yellow
White
Red(0)/Dark
Red(1)
Red(2)

:

:
Red(61)
Red(62)
Red(63)
Green(0)/Dark
Green(1)
Green(2)

:

:
Green(61)
Green(62)
Green(63)
Blue(0)/Dark
Blue(1)
Blue(2)

:

:
Blue(61)
Blue(62)
Blue(63)

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

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Model No.: N156B3-L01

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Data Signal

Red Green Blue

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

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1

0

0

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0

0

0

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1

1

1

0

0

0

0

0

0

0

0

0

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0

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1

1

1

0

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0

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0

0

0

0

1

1

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1

1

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0

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0

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0

0

0

0

0

0

1

1

1

1

1

1

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5.5 EDID DATA STRUCTURE

The EDID (Extended Display Identification Data) data formats are to support displays as defined in the

VESA Plug & Display and FPDI standards.

Byte
#(decimal)

0 0 Header

1 1 Header

2 2 Header

3 3 Header

4 4 Header

5 5 Header

6 6 Header

7 7 Header

8 8 EISA ID manufacturer name (“CMO”)

9 9 EISA ID manufacturer name (Compressed ASCII)

10 0A ID product code (N156B3-L01) 57

11 0B ID product code (hex LSB first; N156B3-L01) 15

12 0C ID S/N (fixed “0”)

13 0D ID S/N (fixed “0”)

14 0E ID S/N (fixed “0”)

15 0F ID S/N (fixed “0”)

16 10 Week of manufacture (fixed “00H”)

17 11 Year of manufacture (fixed “00H”)

18 12 EDID structure version # (“1”)

19 13 EDID revision # (“3”)

20 14 Video I/P definition (“digital”)

21 15 Active area horizontal 34cm

22 16 Active area vertical 19cm

23 17 Display Gamma (Gamma = ”2.2”)

24 18 Feature support (“Active off, RGB Color”)

25 19

26 1A

27 1B

28 1C

29 1D

30 1E

31 1F

32 20

33 21

34 22

35 23 Established timings 1

36 24 Established timings 2 (1366*768@60Hz)

37 25 Manufacturer’s reserved timings

38 26 Standard timing ID # 1

39 27 Standard timing ID # 1

Byte
#(hex)Field Name and Comments Value(hex) Value(binary)

Sy2-!Sy1-!Sz2-!Sz1-!Hy2-!Hy1-!Hz2-!Hz1!
Cy2-!Cy1-!Cz2-!Cz1-!Xy2-!Xy1-!Xz2-!Xz1!
Sy>1/69!
Sz>1/45!
Hy>1/42!
Hz>1/66!
Cy>1/266!
Cz>1/266!
Xy>1/424!
Xz>1/43:!

Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

00 00000000

FF 11111111

FF 11111111

FF 11111111

FF 11111111

FF 11111111

FF 11111111

00 00000000

0D 00001101

AF 10101111

01010111

00010101

00 00000000

00 00000000

00 00000000

00 00000000

20 00100000

12 00010010

01 00000001

03 00000011

90 10010000

22 00100010

13 00010011

78 01111000

0A 00001010

87 10000111

F5 11110101

94 10010100

57 01010111

4F 01001111

8C 10001100

27 00100111

27 00100111

50 01010000

54 01010100

00 00000000

00 00000000

00 00000000

01 00000001

01 00000001

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40 28 Standard timing ID # 2

41 29 Standard timing ID # 2

42 2A Standard timing ID # 3

43 2B Standard timing ID # 3

44 2C Standard timing ID # 4

45 2D Standard timing ID # 4

46 2E Standard timing ID # 5

47 2F Standard timing ID # 5

48 30 Standard timing ID # 6

49 31 Standard timing ID # 6

50 32 Standard timing ID # 7

51 33 Standard timing ID # 7

52 34 Standard timing ID # 8

53 35 Standard timing ID # 8

Detailed timing description # 1 Pixel clock (“75.5MHz”, According to

54 36

55 37 # 1 Pixel clock (hex LSB first)

56 38 # 1 H active (“1366”)

57 39 # 1 H blank (“194”)

58 3A # 1 H active : H blank (“1366 : 194”)

59 3B # 1 V active (”768”)

60 3C # 1 V blank (”38”)

61 3D # 1 V active : V blank (”768 :38”)

62 3E # 1 H sync offset (”31”)

63 3F # 1 H sync pulse width ("65”)

64 40 # 1 V sync offset : V sync pulse width (”4 :12”)

65 41

66 42 # 1 H image size (”344 mm”)

67 43 # 1 V image size (”193 mm”)

68 44 # 1 H image size : V image size (”344 : 193”)

69 45 # 1 H boarder (”0”)

70 46 # 1 V boarder (”0”)

71 47

72 48

73 49 # 1 Pixel clock (hex LSB first)

74 4A # 1 H active (“1366”)

75 4B # 1 H blank (“194”)

76 4C # 1 H active : H blank (“1366 : 194”)

77 4D # 1 V active (”768”)

78 4E # 1 V blank (”38”)

79 4F # 1 V active : V blank (”768 :38”)

80 50 # 1 H sync offset (”31”)

81 51 # 1 H sync pulse width ("65”)

VESA CVT Rev1.1)

# 1 H sync offset : H sync pulse width : V sync offset : V sync width
(”31: 65 : 4 :12”)

# 1 Non-interlaced ; Normal display, no stereo ; Digital Separate ; V
sync POL is negative
; H sync POL is positive
Detailed timing description # 1 Pixel clock (“75.5MHz”, According to
VESA CVT Rev1.1)

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

01 00000001

7E 01111110

1D 00011101

56 01010110

C2 11000010

50 01010000

00 00000000

26 00100110

30 00110000

1F 00011111

41 01000001

4C 01001100

00 00000000

58 01011000

C1 11000001

10 00010000

00 00000000

00 00000000

1A 00011010

7E 01111110

1D 00011101

56 01010110

C2 11000010

50 01010000

00 00000000

26 00100110

30 00110000

1F 00011111

41 01000001

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Model No.: N156B3-L01

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82 52 # 1 V sync offset : V sync pulse width (”4 :12”)

# 1 H sync offset : H sync pulse width : V sync offset : V sync width

83 53

84 54 # 1 H image size (”344 mm”)

85 55 # 1 V image size (”193 mm”)

86 56 # 1 H image size : V image size (”344 : 193”)

87 57 # 1 H boarder (”0”)

88 58 # 1 V boarder (”0”)

89 59

90 5A Detailed timing description # 3

91 5B # 3 Flag

92 5C # 3 Reserved

93 5D # 3 FE (hex) defines ASCII string (Model Name “N156B3”, ASCII)

94 5E # 3 Flag

95 5F # Dell P/N " G732G" 1st character (“G”)

96 60 # Dell P/N " G732G" 1st character (“7”)

97 61 # Dell P/N " G732G" 1st character (“3”)

98 62 # Dell P/N " G732G" 1st character (“2”)

99 63 # Dell P/N " G732G" 1st character (“G”)

100 64

101 65 Manufacturer P/N ( "N")

102 66 Manufacturer P/N ( "1" )

103 67 Manufacturer P/N ( "5" )

104 68 Manufacturer P/N ( "6" )

105 69 Manufacturer P/N ( "B" )

106 6A Manufacturer P/N ( "3" )

107 6B

108 6C Flag

109 6D Flag

110 6E Flag

111 6F Data Type Tag:

112 70 Flag

113 71 SMBUS value @ 10nits = 0d 00

114 72 SMBUS value @ 17nits = 0d 00

115 73 SMBUS value @ 24nits = 0d 00

116 74 SMBUS value @ 30nits = 0d 00

117 75 SMBUS value @ 60nits = 0d 00

118 76 SMBUS value @ 100nits = 0d 00

119 77 SMBUS value @ 180nits = 0d 00

120 78 SMBUS value @ max nits = 0d 00

121 79

122 7A BIST Enable: Yes = '01' No = '00' ("Yes")

123 7B

(”31: 65 : 4 :12”)

# 1 Non-interlaced ; Normal display, no stereo ; Digital Separate ; V
sync POL is negative
; H sync POL is positive

LCD Supplier EEDID Revision #: "2" 0A 00001010

Manufacturer P/N (If <13 char, then terminate with ASCII code 0Ah,
set remaining char = 20h)

Bit[1:0] 00:reserved , 01: single LVDS, 10: dual LVDS, 11: reserved
Bit[2] 0: No RTC support , 1: RTC support
Bit[7:3] Reserved

If <13 char, then terminate with ASCII code 0Ah, set remaining char =

4C 01001100

00 00000000

58 01011000

C1 11000001

10 00010000

00 00000000

00 00000000

1A 00011010

00 00000000

00 00000000

00 00000000

FE 11111110

00 00000000

47 01000111

37 00110111

33 00110011

32 00110010

47 01000111

4E 01001110

31 00110001

35 00110101

36 00110110

42 01000010

33 00110011

0A 00001010

00 00000000

00 00000000

00 00000000

00 00000000

00 00000000

01 00000001

02 00000010

0A 00001010

00000000

00000000

00000000

00000000

00000000

00000000

00000000

00000000

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20h)

(If <13 char, then terminate with ASCII code 0Ah, set remaining char =

124 7C

125 7D

126 7E Extension flag

127 7F Checksum

20h)
(If <13 char, then terminate with ASCII code 0Ah, set remaining char =
20h)

6. INTERFACE TIMING

6.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

DCLK Frequency 1/Tc 50 75.5 80 MHz (2)

Vertical Total Time TV 778 806 888 TH -

Vertical Active Display Period TVD 768 768 768 TH -

DE

Vertical Active Blanking Period TVB TV-TVD 38 TV-TVD TH

Horizontal Total Time TH 1446 1560 1936 Tc (2)

Horizontal Active Display Period THD 1366 1366 1366 Tc (2)

Horizontal Active Blanking Period THB

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TH-THD

194

Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

20 00100000

20 00100000

00 00000000

A5 10100101

TH-THD

Tc (2)

INPUT SIGNAL TIMING DIAGRAM

DE

DCLK

DE

DATA

TC

HD

T

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6.2 POWER ON/OFF SEQUENCE

Power Supply

for LCD, Vcc

- Interface Signal

(LVDS Signal of
Transmitter), V

- Power for Lamp

0V

0V

I

10%

Power On

90%

t1

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Valid Data

ONOFF OFF

Power Off

90%

t3 t2

t6 t5

50%50%

t7

10%

Doc No.:

Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

Restart

10%

t4

Timing Specifications:

0.5< t1 <= 10 msec

0 < t2 <= 50 msec

0 < t3 <= 50 msec

t4 >= 500 msec

t5 >= 200 msec

t6 >= 200 msec

Note (1) Please follow the power on/off sequence described above. Otherwise, the LCD module might be

damaged.

Note (2) Please avoid floating state of interface signal at invalid period. When the interface signal is invalid, be

sure to pull down the power supply of LCD Vcc to 0 V.

Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the

interface signal is valid. The Backlight inverter power must be turned off before the power supply

for the logic and the interface signal is invalid.

Note (4) Sometimes some slight noise shows when LCD is turned off (even backlight is already off). To

avoid this phenomenon, we suggest that the Vcc falling time is better to follow 5msЉt7Љ300 ms.

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7. OPTICAL CHARACTERISTICS

7.1 TEST CONDITIONS

Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 3.3 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current IL 6.0 mA
Inverter Driving Frequency FL 61 KHz
Inverter Sumida-H05-4915

The measurement methods of optical characteristics are shown in Section 7.2. The following items

should be measured under the test conditions described in Section 7.1 and stable environment shown in

Note (6).

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25r2

50r10

Doc No.:

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Model No.: N156B3-L01

Approval

o

C

%RH

7.2 OPTICAL SPECIFICATIONS

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 280 400 - - (2), (5)

Response Time

Average Luminance of White

Red

Green
Color
Chromaticity

Blue

White

Color Gamut C.G.

Horizontal

Viewing Angle

Vertica l

White Variation of 5 Points GW5p

TR - 3 8 ms

- 7 12 ms

T

F

L

AVE

Rx

Ry
Gx
Gy

Bx

By

=0q, TY =0q

T

x

Viewing Normal Angle

175 220 - cd/m

0.629

0.333

0.292

TYP.

-0.03

0.580

0.160

TYP.

+0.03

0.096
Wx 0.313 ­Wy

0.329

54 60 - % (7)

Tx+

T

x

TY+

T

Y

40

-

40
15

-

40

T

=0q, TY =0q

x

40 45 ­40 45 ­15 20 -

Deg. (1),(5)

40 45 ­75 85 - % (5),(6)

(3)

2

(4), (6)

-

-

-

-

-

(1)

-

-

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.67 ms

Note (1) Definition of Viewing Angle (Tx, Ty):

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Model No.: N156B3-L01

Approval

TX- = 90º

x-

6 o’clock

T

y- = 90º

y-

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L63 / L0

Normal

Tx = Ty = 0º

Ty- Ty

Tx

Tx

y+

12 o’clock direction

T

y+ = 90º

x+

TX+ = 90º

L63: Luminance of gray level 63

L 0: Luminance of gray level 0

CR = CR (1)

CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6).

Note (3) Definition of Response Time (T

100%

90%

Optical

Response

10%

0%

T

R

66.67 ms

, TF):

R

66

Time

T

F

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500

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Model No.: N156B3-L01

Approval

Note (4) Definition of Average Luminance of White (L

Measure the luminance of gray level 63 at 5 points

L

= [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / 5

AVE

L (x) is corresponding to the luminance of the point X at Figure in Note (6)

Note (5) Measurement Setup:

The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting Backlight for 20 minutes in a windless room.

LCD Module

LCD Panel

USB2000

AVE

):

CS-1000T

Center of the Screen

mm

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (6) Definition of White Variation (GW):

Measure the luminance of gray level 63 at 5 points

GW

= Minimum [L (1)+ L (2)+ L (3)+ L (4)+ L (5)] / Maximum [L (1)+ L (2)+ L (3)+ L (4)+ L (5)]

5p

˄˃

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Issued Date: Jul. 11, 2008

Model No.: N156B3-L01

Approval

ˉ

˛˂ˇ

˅

˄˃

ˌ

ˇˈ

˄˄

˄˃ ˄˃

˪˂ˇ ˪˂ˇ ˪˂ˇ ˪˂ˇ

˛

˛˂ˇ ˛˂ˇ ˛˂ˇ

Note (7) Definition of color gamut (C.G%):

C.G%= ΓR G B /ΓR

R

R, G, B

ΓR

, G0, B0 : color coordinates of red, green, and blue defined by NTSC, respectively.

0

: color coordinates of module on 63 gray levels of red, green, and blue, respectively.

0 G0 B0

: area of triangle defined by R0, G0, B0

0 G0 B0

ˊ

˄

˄˅

˪

,*100%

ˋ

ˆ

X

: Test Point

˄˃

˄ˆ

X=1 to 13

Active area

ΓR G B: area of triangle defined by R, G, B

˖˜˘ʳ˄ˌˆ˄

˃ˁˌ

˃ˁˋ

˃ˁˊ

˃ˁˉ

˃ˁˈ

˃ˁˇ

˃ˁˆ

˃ˁ˅

˃ˁ˄

˃

˃ ˃ˁ˅ ˃ˁˇ ˃ˁˉ ˃ˁˋ

G

0

G

R

0

R

B

B

0

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8. PRECAUTIONS

8.1 HANDLING PRECAUTIONS

(1) The module should be assembled into the system firmly by using every mounting hole. Be careful not

to twist or bend the module.

(2) While assembling or installing modules, it can only be in the clean area. The dust and oil may cause

electrical short or damage the polarizer.

(3) Use fingerstalls or soft gloves in order to keep display clean during the incoming inspection and

assembly process.

(4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizer is

very soft and easily scratched.

(5) If the surface of the polarizer is dirty, please clean it by some absorbent cotton or soft cloth. Do not use

Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might

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permanently damage the polarizer due to chemical reaction.

(6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on panel for

a long time.

(7) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contacting with hands, legs or clothes, it must be washed away thoroughly with soap.

(8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC.

(9) Do not disassemble the module.

(10) Do not pull or fold the lamp wire.

(11) Pins of I/F connector should not be touched directly with bare hands.

8.2 STORAGE PRECAUTIONS

(1) High temperature or humidity may reduce the performance of module. Please store LCD module within

the specified storage conditions.

(2) It is dangerous that moisture come into or contacted the LCD module, because the moisture may

damage LCD module when it is operating.

(3) It may reduce the display quality if the ambient temperature is lower than 10 ºC. For example, the

response time will become slowly, and the starting voltage of lamp will be higher than the room

temperature.

8.3 OPERATION PRECAUTIONS

(1) Do not pull the I/F connector in or out while the module is operating.

(2) Always follow the correct power on/off sequence when LCD module is connecting and operating. This

can prevent the CMOS LSI chips from damage during latch-up.

(3) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock while

assembling with inverter. Do not disassemble the module or insert anything into the Backlight unit.

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9. PACKING

9.1 CARTON

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Figure. 9-1 Packing method

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9.2 3$//(7

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

Figure. 9-2 Packing method

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N

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10. DEFINITION OF LABELS

10.1 DELL 2D LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

CN-G732G-70896-

OOO-XXXX-A00

Made In China

DP/N G732G

DP/N G732G
Country of Origin CN
DELL P/N G732G
MFG ID 70896
Date Code OOO
Serial Number XXXX
Part-Number Revision
(Rev)

A00

10.2 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

156B3-L01 Rev. C1

(a) Model Name: N156B3 - L01

(b) Revision: Rev. XX, for example: C1, C2 …etc.

(c) Serial ID: X X

X X X X X Y M D L N N N N

-

Serial ID includes the information as below:

(a) Manufactured Date: Year: 1~9, for 2001~2009

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1

Rev. XX

xxxx

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

Revision

CMO Internal Use

st

to 31st, exclude I , O and U

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(b) Revision Code: cover all the change

(c) Serial No.: Manufacturing sequence of product

(d) Product Line: 1 -> Line1, 2 -> Line 2, …etc.

10.3 CARTON LABEL

z

0468870896YMDSSSSSS0G732G20

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A00

0G732G

Made in

XXXX

Lead Free

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