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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
REVISION HISTORY
Version Date
Ver 1.0
Ver 1.1
Mar. 17,’08
Apr. 23,’08
Page
(New)
All
21
26
Section Description
All
Preliminary Specification was first issued.
7.2
9.1
Modify Opt spec.
Modify package weight.
3 / 30
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1. GENERAL DESCRIPTION
1.1 OVERVIEW
N154Z3 - L02 is a 15.4” TFT Liquid Crystal Display module with single CCFL Backlight unit and 30 pins
LVDS interface. This module supports 1680 x 1050 Wide-SXGA+ mode and can display 262,144 colors.
The optimum viewing angle is at 6 o’clock direction. The inverter module for Backlight is not built in.
1.2 FEATURES
- Thin and High Brightness
- WSXGA+ (1680 x 1050 pixels) resolution
- DE only mode
- 3.3V LVDS (Low Voltage Differential Signaling) interface with 2 pixel/clock
- Meet RoHS requirement
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
1.3 APPLICATION
- TFT LCD Notebook
1.4 GENERAL SPECIFICATI0NS
Item Specification Unit Note
Active Area 331.2 (H) x 207.0 (V) (15.4 inch Diagonal) mm
Bezel Opening Area 334.7 (H) x 210.5 (V) mm
Driver Element a-si TFT active matrix - Pixel Number 1680 x 3 (RGB) x 1050 pixel Pixel Pitch 0.1971 x 0.1971 mm Pixel Arrangement RGB vertical stripe - Display Colors 262,144 color Transmissive Mode Normally white - Surface Treatment Hard coating (3H), Glare - -
1.5 MECHANICAL SPECIFICATIONS
Item Min. Typ. Max. Unit Note
Horizontal (H) 343.5 344 344.5 mm
Module Size
Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.
Vertical (V) 221.5 222 222.5 mm
Depth (D) --- 6.2 6.5 mm
Weight --- 515 530 g -
(1)
(1)
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2. ABSOLUTE MAXIMUM RATINGS
2.1 ABSOLUTE RATINGS OF ENVIRONMENT
Item Symbol
Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V
Note (1) Temperature and relative humidity range is shown in the figure below.
(a) 90 %RH Max. (Ta Љ 40 ºC).
(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).
(c) No condensation.
Note (2) The temperature of panel surface should be 0 ºC Min. and 50 ºC Max.
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Min. Max.
- 200/2 G/ms (3), (5)
NOP
- 1.5 G (4), (5)
NOP
Value
Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
Unit Note
Relative Humidity (%RH)
100
90
80
60
Operating Range
40
20
10
Storage Range
Temperature (ºC)
Note (3) 1 time for ± X, ± Y, ± Z. for Condition (200G / 2ms) is half Sine Wave,
8060-20400 20-40
Note (4) 10 ~ 200 Hz, 0.5 Hr / Cycle, 1 cycles for each X, Y, Z.
Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough
so that the module would not be twisted or bent by the fixture.
The fixing condition is shown as below:
LCD Module
Side Mount Fixing Screw
gap=2mm
Side Mount Fixing Screw
Stage
Bracket
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2.2 ELECTRICAL ABSOLUTE RATINGS
2.2.1 TFT LCD MODULE
Item Symbol
Power Supply Voltage VCC -0.3 +4.0 V
Logic Input Voltage VIN -0.3 VCC+0.3 V
2.2.2 BACKLIGHT UNIT
Item Symbol
Lamp Voltage VL -- 2.5K V
Lamp Current IL 3 7.0 mA
Lamp Frequency FL 40 80 KHz
Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation
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Value
Min. Max.
Value
Min. Max.
Unit Note
Unit Note
Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
(1)
(1), (2), IL = 6.0 mA
RMS
RMS
(1), (2)
should be restricted to the conditions described under Normal Operating Conditions.
Note (2) Specified values are for lamp (Refer to 3.2 for further information).
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
3. ELECTRICAL CHARACTERISTICS
3.1 TFT LCD MODULE Ta = 25 ± 2 ºC
Parameter Symbol
Min. Typ. Max.
Power Supply Voltage Vcc 3.0 3.3 3.6 V Ripple Voltage VRP 50 mV Rush Current I
1.5 A (2)
RUSH
Initial Stage Current IIS 1.0 A (2)
Power Supply Current
LVDS Differential Input High Threshold V
LVDS Differential Input Low Threshold V
White (380) (410) mA (3)a
Black
Lcc
TH(LVDS)
TL(LVDS)
(520) (550) mA (3)b
+100 mV
-100 mV
LVDS Common Mode Voltage VCM 1.125 1.375 V (5)
LVDS Differential Input Voltage |VID| 100 600 mV (5)
Terminating Resistor RT 100 Ohm
Power per EBL WG P
- TBD - W (4)
EBL
Note (1) The module should be always operated within above ranges.
Value
Unit Note
V
V
(5),
=1.2V
CM
(5)
=1.2V
CM
Note (2) Measurement Conditions:
+3.3V
R1
47K
(High to Low)
(Control Signal)
SW
+12V
C1
1uF
VR1
R2
1K
47K
Q1 2SK1475
C2
0.01uF
Q2
2SK1470
FUSE
C3
1uF
Vcc
(LCD Module Input)
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
Note (3) The specified power supply current is under the conditions at Vcc = 3.3 V, Ta = 25 ± 2 ºC, DC
0V
I
RUSH
Current and f
a. White Pattern
= 60 Hz, whereas a power dissipation check pattern below is displayed.
v
Vcc rising time is 470us
0.9Vcc
470us
0.1Vcc
+3.3V
100ms
b. Black Pattern
VCC
I
IS
ICC
Note (4) The specified power are the sum of LCD panel electronics input power and the inverter input
power. Test conditions are as follows.
(a) Vcc = 3.3 V, Ta = 25 ± 2 ºC, f
(b) The pattern used is a black and white 32 x 36 checkerboard, slide #100 from the VESA file
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|
|
Note (5) The parameters of LVDS signals are defined as the following figures.
CM
Single Ended
Differential
V
0V
V
0V
V
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
VID|
VID|
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
3.2 BACKLIGHT UNIT Ta = 25 ± 2 ºC
Parameter Symbol
Min. Typ. Max.
Lamp Input Voltage VL 675 730 945 V
Lamp Current IL
Lamp Turn On Voltage VS
2.0 (1),(2)
3.0
1140 (25
1580 (0
Operating Frequency FL 40 80 KHz (5)
Lamp Life Time LBL 15,000 Hrs (7)
Power Consumption PL 4.38 W (4), IL = 6.0 mA
Note (1) Lamp current is measured by utilizing a high frequency current meter as shown below:
Value
6.0 6.5 mA
o
C)V
o
C)V
Unit Note
I
RMS
RMS
RMS
RMS
L
(4)
(4)
= 6.0 mA
(1),(3)
LCD
Module
HV (Pink)
LV (White)
1
2
Current Meter
Inverter
A
Note (2) for burst mode inverter design
Note (3) for continuous mode inverter design
Note (4) The voltage that must be larger than Vs should be applied to the lamp for more than 1 second
after startup. Otherwise the lamp may not be turned on.
Note (5) The lamp frequency may produce interference with horizontal synchronous frequency from the
display, and this may cause line flow on the display. In order to avoid interference, the lamp
frequency should be detached from the horizontal synchronous frequency and its harmonics as far
as possible.
Note (6) P
= IL V
L
L
Note (7) The lifetime of lamp can be defined as the time in which it continues to operate under the condition
Ta = 25 2
o
C and IL = 6.0 mArms until one of the following events occurs:
(a) When the brightness becomes or lower than 50% of its original value.
(b) When the effective ignition length becomes or lower than 80% of its original value.
(The effective ignition length is a scope that luminance is over 70% of that at the center point.)
Note (8) The waveform of the voltage output of inverter must be area-symmetric and the design of the
inverter must have specifications for the modularized lamp. The performance of the Backlight,
such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for
10 / 30
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the lamp. All the parameters of an inverter should be carefully designed to avoid generating too
much current leakage from high voltage output of the inverter. When designing or ordering the
inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the
inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module
should be operated in the same manners when it is installed in your instrument.
The output of the inverter must have symmetrical (negative and positive) voltage waveform and
symmetrical current waveform.(Unsymmetrical ratio is less than 10%) Please do not use the inverter,
which has unsymmetrical voltage and unsymmetrical current and spike wave. Lamp frequency may
produce interface with horizontal synchronous frequency and as a result this may cause beat on the
display. Therefore lamp frequency shall be as away possible from the horizontal synchronous
frequency and from its harmonics in order to prevent interference.
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
Requirements for a system inverter design, which is intended to have a better display performance, a
better power efficiency and a more reliable lamp. It shall help increase the lamp lifetime and reduce its
leakage current.
a. The asymmetry rate of the inverter waveform should be 10% below;
b. The distortion rate of the waveform should be within Ѕ2 ± 10%;
c. The ideal sine wave form shall be symmetric in positive and negative polarities.
* Asymmetry rate:
I p
I -p
| I
* Distortion rate
I
– I –p | / I
p
(or I –p) / I
p
rms
rms
* 100%
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)
4. BLOCK DIAGRAM
4.1 TFT LCD MODULE
LVD S dis p lay
Data & Clock
INPUT CONNECTOR
Vcc
GND
Data
EDID
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LVDS INPUT /
TIMING CONTROLLER
DC/DC CONVERTER &
REFERENCE VOLTAGE
GENERATOR
Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
SCAN DRIVER IC
TFT LCD PANEL
DATA DRIVER IC
CLK
V
EDID
EDID
VL
LAMP CONNECTOR
4.2 BACKLIGHT UNIT
EDID
EEPROM
BACKLIGHT UNIT
1 HV (Pink)
2 LV (White
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5. INPUT TERMINAL PIN ASSIGNMENT
5.1 TFT LCD MODULE
Pin Symbol Description Polarity Remark
1 Vss Ground
2 VCC Power Supply +3.3 V (typical)
3 VCC Power Supply +3.3 V (typical)
4 V
5 NC Non-Connection
6 CLK
7 DATA
8 RXO0- LVDS Differential Data Input (Odd) Negative
9 RXO0+ LVDS Differential Data Input (Odd) Positive
10 Vss Ground
11 RXO1- LVDS Differential Data Input (Odd) Negative
12 RXO1+ LVDS Differential Data Input (Odd) Positive
13 Vss Ground
14 RXO2- LVDS Differential Data Input (Odd) Negative
15 RXO2+ LVDS Differential Data Input (Odd) Positive
16 Vss Ground
17 RXOC- LVDS Clock Data Input (Odd) Negative
18 RXOC+ LVDS Clock Data Input (Odd) Positive
19 Vss Ground
20 RXE0- LVDS Differential Data Input (Even) Negative
21 RXE0+ LVDS Differential Data Input (Even) Positive
22 Vss Ground
23 RXE1- LVDS Differential Data Input (Even) Negative
24 RXE1+ LVDS Differential Data Input (Even) Positive
25 Vss Ground
26 RXE2- LVDS Differential Data Input (Even) Negative
27 RXE2+ LVDS Differential Data Input (Even) Positive
28 Vss Ground
29 RXEC- LVDS Clock Data Input (Even) Negative
30 RXEC+ LVDS Clock Data Input (Even) Positive
Note (1) Connector Part No.: JAE-FI-XB30SL-HF10 or equivalent
DDC 3.3V Power
EDID
DDC Clock
EDID
DDC Data
EDID
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
Note (2) User’s connector Part No: FI-XB30C2L or equivalent
Note (3) The first pixel is odd as shown in the following figure.
13 / 30
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
5.2 BACKLIGHT UNIT
Pin Symbol Description Color
1 HV High Voltage Pink
2 LV Ground Black
Note (1) Connector Part No.: JST-BHSR-02VS-1 or equivalent
Note (2) User’s connector Part No.: JST-SM02B-BHSS-1-TB or equivalent
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5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL
RXOC+/-
RXO2+/-
RXO1+/-
T/7
IN20 IN19 IN18IN17IN16IN15 IN14
DE OB5OB4OB3 OB2 Vsync Hsync
IN13 IN12 IN11IN10IN9IN8 IN7
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Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
RXO0+/-
RXEC+/-
RXE2+/-
RXE1+/-
RXE0+/-
OB1 OG4OG3OG2 OG1 OB0 OG5
IN6 IN5 IN4IN3IN2IN1 IN0
OG0 OR3OR2OR1 OR0 OR5 OR4
Signal for 1 DCLK Cycle (T)
T/7
IN20 IN19 IN18IN17IN16IN15 IN14
DE EB5EB4EB3 EB2 Vsync Hsync
IN13 IN12 IN11IN10IN9IN8 IN7
EB1 EG4EG3EG2 EG1 EB0 EG5
IN6 IN5 IN4IN3IN2IN1 IN0
EG0 ER3ER2ER1 ER0 ER5 ER4
Signal for 1 DCLK Cycle (T)
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5.4 COLOR DATA INPUT ASSIGNMENT
The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for
the color. The higher the binary input, the brighter the color. The table below provides the assignment of
color versus data input.
Color
R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black
Red
Green
Basic
Colors
Gray
Scale
Of
Red
Gray
Scale
Of
Green
Gray
Scale
Of
Blue
Note (1) 0: Low Level Voltage, 1: High Level Voltage
Blue
Cyan
Magenta
Yellow
White
Red(0)/Dark
Red(1)
Red(2)
Header
Header
Header
Header
Header
Header
Header
Header
EISA ID manufacturer name (“CMO”)
EISA ID manufacturer name (Compressed ASCII)
ID product code (N154Z3-L02) 63
ID product code (hex LSB first; N154Z3-L02) 15
ID S/N (fixed “0”)
ID S/N (fixed “0”)
ID S/N (fixed “0”)
ID S/N (fixed “0”)
Week of manufacture (fixed week code)
Year of manufacture (fixed year code)
EDID structure version # (“1”)
EDID revision # (“3”)
Video I/P definition (“digital”)
Max H image size (“33.12 cm”)
Max V image size (“20.7 cm”)
Display Gamma (Gamma = ”2.2”)
Feature support (“Active off, RGB Color”)
Rx1, Rx0, Ry1, Ry0, Gx1, Gx0, Gy1, Gy0 47
Bx1, Bx0, By1, By0, Wx1, Wx0, Wy1, Wy0 F1
Rx=0.626 A0
Ry=0.355 5B
Gx=0.294 4B
Gy=0.589 96
Bx=0.144 24
By=0.097 18
Wx=0.309 4F
Wy=0.329 54
Established timings 1
Established timings 2
Manufacturer’s reserved timings
Standard timing ID # 1
Standard timing ID # 1
Standard timing ID # 2
Standard timing ID # 2
Standard timing ID # 3
Standard timing ID # 3
Standard timing ID # 4
Standard timing ID # 4
Standard timing ID # 5
Standard timing ID # 5
Standard timing ID # 6
Standard timing ID # 6
Standard timing ID # 7
Standard timing ID # 7
Standard timing ID # 8
Standard timing ID # 8
VESA CVT Rev1.1)
# 1 Pixel clock (hex LSB first)
# 1 H active (“1680”)
# 1 H blank (“160”)
# 1 H active : H blank (“1680 : 160”)
# 1 V active (”1050”)
# 1 V blank (”30”)
# 1 V active : V blank (”1050 : 30”)
# 1 H sync offset (”48”)
# 1 H sync pulse width ("32”)
# 1 V sync offset : V sync pulse width (”3 : 6”)
(”48: 32 : 3 : 6”)
# 1 H image size (”331.2 mm”) 4B
# 1 V image size (”207.0 mm”) CF
# 1 H image size : V image size (”331.2 : 207”)
# 1 H boarder (”0”)
# 1 V boarder (”0”)
ASCII)
# 2 Flag
# 2 1st character of name (“N”)
# 2 2nd character of name (“1”)
# 2 3rd character of name (“5”)
# 2 4th character of name (“4”)
# 2 5th character of name (“Z”)
# 2 6th character of name (“3”)
# 2 7th character of name (“-”)
# 2 9th character of name (“0”)
# 2 9th character of name (“2”)
# 2 New line character indicates end of ASCII string
# 2 Padding with “Blank” character
# 2 Padding with “Blank” character
Detailed timing description # 3
# 3 Flag
# 3 Reserved
# 3 FE (hex) defines ASCII string (Vendor “CMO”, ASCII)
# 3 Flag
# 3 1st character of string (“C”)
# 3 2nd character of string (“M”)
# 3 3rd character of string (“O”)
# 3 New line character indicates end of ASCII string
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
# 3 Padding with “Blank” character
Detailed timing description # 4
# 4 Flag
# 4 Reserved
ASCII)
# 4 Flag
# 4 1st character of name (“N”) 4E
# 4 2nd character of name (“1”) 31
# 4 3rd character of name (“5”) 35
# 4 4th character of name (“4”) 34
# 4 5th character of name (“Z”) 5A
# 4 6th character of name (“3”) 33
# 4 7th character of name (“-”) 2D
# 4 8th character of name (“L”) 4C
# 4 9th character of name (“0”)
# 4 9th character of name (“2”)
# 4 New line character indicates end of ASCII string
# 4 Padding with “Blank” character
# 4 Padding with “Blank” character
Extension flag
Checksum
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6. INTERFACE TIMING
6.1 INPUT SIGNAL TIMING SPECIFICATIONS
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item SymbolMin. Typ. Max. Unit Note
DCLK Frequency 1/Tc (50) 59.6 (67.5) MHz (2)
Vertical Total Time TV 105710801090 TH -
Vertical Active Display Period TVD 105010501050 TH -
DE
Note (1) Because of this module is operated by DE only mode, Hsync and Vsync are ignored.
(2) 2 channels LVDS input.
Vertical Active Blanking Period TVB TV-TVD30 TV-TVD TH -
Horizontal Total Time TH 890 920 1010 Tc (2)
Horizontal Active Display Period THD 840 840 840 Tc (2)
Horizontal Active Blanking Period THB
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TH-THD
80
Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
TH-THD
Tc (2)
INPUT SIGNAL TIMING DIAGRAM
DE
DCLK
DE
DATA
TC
HD
T
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6.2 POWER ON/OFF SEQUENCE
Power On
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Power Off
Doc. No.: 44082125
Issued Date: Apr.23, 2008
Model No.: N154Z3 - L02
Preliminary
Restart
Power Supply
for LCD, Vcc
- LVDS Interface
0V
0V
- Power for Lamp
Timing Specifications:
0.5 Љ t1 Љ 10 ms
0 Љ t2 Љ 50 ms
0 Љ t3 Љ 50 ms
t4 Њ 500 ms
10%
90%
t1
90%
Valid Data
t6 t5
50%50%
ONOFF OFF
t7
10%
t4
t3 t2
t5 Њ 200 ms
t6 Њ 200 ms
Note (1) Please follow the power on/off sequence described above. Otherwise, the LCD module might be
damaged.
Note (2) Please avoid floating state of interface signal at invalid period. When the interface signal is invalid, be
sure to pull down the power supply of LCD Vcc to 0 V.
Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the
interface signal is valid. The Backlight inverter power must be turned off before the power supply
for the logic and the interface signal is invalid.
Note (4) Sometimes some slight noise shows when LCD is turned off (even backlight is already off). To
avoid this phenomenon, we suggest that the Vcc falling time is better to follow 5Љt7Љ300 ms.
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7. OPTICAL CHARACTERISTICS
7.1 TEST CONDITIONS
Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 3.3 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current IL 6.0 mA
Inverter Driving Frequency FL 61 KHz
Inverter Sumida H05-4915
The relative measurement methods of optical characteristics are shown in 7.2. The
following items should be measured under the test conditions described in 7.1 and stable