CMO N141C3-L03 Specification

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TFT LCD Approval Specification

MODEL NO.: N141C3 - L03

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

Customer: Dell

Approved by:

Note:



2007-05-22 18:16:44 CST



Approve by Dept. Mgr.(QA RA)



yuan_chan(᎓ঊෘ /52760/54760)



Department Manager(QA RA)

Accept



2007-05-21 15:43:46 CST

2007-05-15 19:04:13 CST

2007-05-14 14:36:56 CST

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Approve by Director

jy_wu(ܦᔼԬ/56360/54952)

wy_li(ޕޫ/44701)

kf_huang(႓഼୽ /56620/54380/14906/25075)

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Director Accept

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

- CONTENTS -

REVISION HISTORY ------------------------------------------------------- 1

1. GENERAL DESCRIPTION

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

------------------------------------------------------- 5

2. ABSOLUTE MAXIMUM RATINGS ------------------------------------------------------- 6

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

2.2.2 BACKLIGHT UNIT

3. ELECTRICAL CHARACTERISTICS ------------------------------------------------------- 8

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

4. BLOCK DIAGRAM ------------------------------------------------------- 12

4.1 TFT LCD MODULE

4.2 BACKLIGHT UNIT

5. INPUT TERMINAL PIN ASSIGNMENT ------------------------------------------------------- 13

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT

5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL

5.4 COLOR DATA INPUT ASSIGNMENT

5.5 EDID DATA STRUCTURE

6. INVERTER SPECIFICATION ------------------------------------------------------- 19

6.1 INPUT CONNECTOR PIN ASSIGNMENT

6.2 INPUT CONNECTOR PIN ASSIGNMENT

6.3 OUTPUT CONNECTOR PIN ASSIGNMENT

6.4 GENERAL ELECTRICAL SPECIFICATION

7. INTERFACE TIMING ------------------------------------------------------- 23

7.1 INPUT SIGNAL TIMING SPECIFICATIONS

7.2 POWER ON/OFF SEQUENCE

8. OPTICAL CHARACTERISTICS ------------------------------------------------------- 25

8.1 TEST CONDITIONS

8.2 OPTICAL SPECIFICATIONS

9. PRECAUTIONS ------------------------------------------------------- 27

9.1 HANDLING PRECAUTIONS

9.2 STORAGE PRECAUTIONS

9.3 OPERATION PRECAUTIONS

10. PACKING ------------------------------------------------------- 33

10.1 CARTON

10.2 PALLET

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

11. DEFINITION OF LABELS ------------------------------------------------------- 33

11.1 CMO MODULE LABEL

11.2 CMO CARTON LABE

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

REVISION HISTORY

Version Date

3.0

3.1

Mar. 12,’07

May. 11,’07

May. 11, ‘07

Page

(New)

All

16,17, 18

21

Section Description

Approval specification was first issued.

All

5.5

6.4.2

Change EDID code .

Change SM-Bus Data Value.

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1 GENERAL DESCRIPTION

1.1 OVERVIEW

N141C3 - L03 is a 14.1” TFT Liquid Crystal Display module with single CCFL Backlight unit and 30 pins

LVDS interface. This module supports 1440 x (3 RGB) x 900 WXGA+ mode and can display 262,144 colors.

The optimum viewing angle is at 6 o’clock direction. The inverter module for Backlight is built in.

1.2 FEATURES

- Thin and Light Weight

- WXGA+ (1440 x 900 pixels) resolution

- DE only mode

- 3.3V LVDS (Low Voltage Differential Signaling) interface with 2 pixel/clock

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

1.3 APPLICATION

- TFT LCD Notebook

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note Active Area 303.48(H) X 189.675(V) (14.1 inch Diagonal) mm Bezel Opening Area 306.76 (H) x 193.0 (V) mm Driver Element a-si TFT active matrix - Pixel Number 1440 x R.G.B. x 900 pixel Pixel Pitch 0.21075 (H) x 0.21075 (V) mm Pixel Arrangement RGB vertical stripe - Display Colors 262,144 color Transmissive Mode Normally white - Surface Treatment Anti-glare and Hard Coat , Haze 41, (3H min.) - -

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal(H) 319 319.5 320 mm

Module Size

Vertical(V) 205 205.5 206 mm

Depth(D) -- 5.2 5.5 mm Weight -- 435 450 g (2) Weight -- 445 460 g (3)

(1)

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions

(2) Weight without inverter

(3) Weight with inverter.

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A

2 ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1) Operating Ambient Temperature TOP 0 +50 ºC (1), (2) Shock (Non-Operating) S Vibration (Non-Operating) V

Note (1) Temperature and relative humidity range is shown in the figure below.

(a) 90 %RH Max. (Ta Љ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation .

Note (2) The temperature of panel display surface area should be 0 ºC Min. and 60 ºC Max.

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Min. Max.

- 220 G (3), (5)

NOP

- 1.5 G (4), (5)

NOP

Value

Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

Unit Note

Relative Humidity (%RH)

100

90

80

60

Operating Range

40

20 10

Storage Range

Temperature (ºC)

Note (3) 1 time for ± X, ± Y, ± Z. for Condition (220G / 2ms) is half Sine Wave

8060-20 40020-40

Note (4) 10 ~ 200 Hz, 30 min / Cycle, 1 cycles for each X, Y, Z.:

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid enough

so that the module would not be twisted or bent by the fixture.

The fixing condition is shown as below:

t Room Temperature

Side Mount Fixing Screw

Gap=2mm

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Bracket

LCD Module

Side Mount Fixing Screw

Stage

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

Item Symbol

Power Supply Voltage VCC -0.3 +4.0 V Logic Input Voltage VIN -0.3 VCC+0.3 V

2.2.2 BACKLIGHT UNIT

Item Symbol

Lamp Voltage VL - 2.5K V Lamp Current IL 2.0 6.5 mA Lamp Frequency FL 45 80 KHz

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

should be restricted to the conditions described under Normal Operating Conditions.

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Value

Min. Max.

Value

Min. Max.

Unit Note

Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

(1)

(1), (2)

RMS

(1), (2)

Note (2) Specified values are for lamp (Refer to 3.2 for further information).

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

3 ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE Ta = 25 ± 2 ºC

Parameter Symbol

Min. Typ. Max. Power Supply Voltage Vcc 3.0 3.3 3.6 V Permissive Ripple Voltage VRP - 50 - mV Rush Current I

- - 1.5 A (2)

RUSH

Initial Stage Current IIS - - 1.0 A (2)

Power Supply Current

LVDS Differential Input High Threshold V

LVDS Differential Input Low Threshold V

White - 420 470 mA (3)a Black

Icc

TH(LVDS)

TL(LVDS)

- 500 580 mA (3)b

- - +100 mV

-100 - - mV

LVDS Common Mode Voltage VCM 1.125 - 1.375 V (5) LVDS Differential Input Voltage |VID| 100 - 600 mV (5) Terminating Resistor RT - 100 - Ohm Power per EBL WG P

- 3.9 - W (4)

EBL

Note (1) The ambient temperature is Ta = 25 ± 2 ºC.

Value

Unit Note

Approval

(5),

=1.2V

V

CM

(5)

=1.2V

V

CM

Note (2) I

: the maximum current when VCC is rising

RUSH

I

: the maximum current of the first 100ms after power-on

IS

Measurement Conditions: Shown as the following figure. Test pattern: black.

(High to Low)

(Control Signal)

SW

+12V

+3.3V

R1

47K

R2

1K

47K

VR1

C1

1uF

Q1 2SK1475

C2

0.01uF

Q2

2SK1470

FUSE

C3

1uF

Vcc

(LCD Module Input)

Vcc rising time is 470us

VCC

ICC

0V

I

RUSH

470us

0.1Vcc

+3.3V

100ms

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I

IS

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|

Note (3) The specified power supply current is under the conditions at Vcc = 3.3 V, Ta = 25 ± 2 ºC, fv = 60

Hz, whereas a power dissipation check pattern below is displayed.

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

a. White Pattern

Active Area

Note (4) The specified power are the sum of LCD panel electronics input power and the inverter input

power. Test conditions are as follows.

(a) Vcc = 3.3 V, Ta = 25 ± 2 ºC, f

(b) The pattern used is a black and white 32 x 36 checkerboard, slide #100 from the VESA file

“Flat Panel Display Monitor Setup Patterns”, FPDMSU.ppt.

(c) Luminance: 60 nits.

(d) The inverter used is provided from Sumida

= 60 Hz,

v

.

b. Black Pattern

Active Area

Note (5) The parameters of LVDS signals are defined as the following figures.

CM

V

Single Ended

0V

V

Differential

0V

V

VID

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Doc No.: 1406X180

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Model No.: N141C3 - L03

3.2 BACKLIGHT UNIT Ta = 25 ± 2 ºC

Parameter Symbol

Min. Typ. Max. Lamp Input Voltage VL 612 680 748 V Lamp Current IL 2.0 6.0 6.5 mA

Lamp Turn On Voltage V

S

- - 1370 (25

- - 1520 (0 Operating Frequency FL 45 - 80 KHz (3) Lamp Life Time LBL 15,000 - - Hrs (5) Power Consumption PL - 4.5 5.0 W (4)

Note (1) Lamp current is measured by utilizing a high frequency current meter as shown below:

Value

o

C) V

o

C) V

Unit Note

I

RMS

(1)

RMS

(2)

RMS

(2)

RMS

Approval

= 6.0 mA

L

HV (Pink)

LCD

LV (White)

Module

1

Inverter

2

A

Current Meter

Note (2) The voltage that must be larger than Vs should be applied to the lamp for more than 1 second

after startup. Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency from the

display, and this may cause line flow on the display. In order to avoid interference, the lamp

frequency should be detached from the horizontal synchronous frequency and its harmonics as far

as possible.

Note (4) P

= Inverter input power

BL

Inverter input power is measured at 8th step(the max brightness step) @Vin=12V

Note (5) The lifetime of lamp can be defined as the time in which it continues to operate under the condition

Ta = 25 2

(a) When the brightness becomes or lowers than 50% of its original value.

(b) When the effective ignition length becomes or lowers than 80% of its original value. (Effective

o

C and IL = 6 mArms until one of the following events occurs:

ignition length is defined as an area that has less than 70% brightness compared to the

brightness in the center point.)

Note (6) The waveform of the voltage output of inverter must be area-symmetric and the design of the

inverter must have specifications for the modularized lamp. The performance of the Backlight,

such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for

the lamp. All the parameters of an inverter should be carefully designed to avoid producing too

much current leakage from high voltage output of the inverter. When designing or ordering the

inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the

inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module

should be operated in the same manners when it is installed in your instrument.

The output of the inverter must have symmetrical (negative and positive) voltage waveform and

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symmetrical current waveform.(Unsymmetrical ratio is less than 10%) Please do not use the inverter

which has unsymmetrical voltage and unsymmetrical current and spike wave. Lamp frequency may

produce interface with horizontal synchronous frequency and as a result this may cause beat on the

display. Therefore lamp frequency shall be as away possible from the horizontal synchronous

frequency and from its harmonics in order to prevent interference.

Requirements for a system inverter design, which is intended to have a better display performance, a

better power efficiency and a more reliable lamp. It shall help increase the lamp lifetime and reduce its

leakage current.

a. The asymmetry rate of the inverter waveform should be 10% below.

b. The distortion rate of the waveform should be within Ѕ2 ± 10%.

c. The ideal sine wave form shall be symmetric in positive and negative polarities.

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

I p

I -p

* Asymmetry rate:

| I

* Distortion rate

I

– I –p | / I

p

(or I –p) / I

p

rms

* 100%

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)

4 BLOCK DIAGRAM

4.1 TFT LCD MODULE

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Doc No.: 1406X180

Issued Date: May,11, 2007

Model No.: N141C3 - L03

Approval

LVDS Display

Data & Clock

Vcc

GND

Data

EDID

CLK

EDID

V

EDID

VL

INPUT CONNECTOR

LAMP CONNECTOR

4.2 BACKLIGHT UNIT

LVDS INPUT /

TIMING CONTROLLER

DC/DC CONVERTER &

REFERENCE VOLTAGE

GENERATOR

EDID

EEPROM

SCAN DRIVER IC

TFT LCD PANEL

DATA DRIVER IC

BACKLIGHT UNIT

1 HV (Pink)

2 LV (White

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5 INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE

Pin Symbol Description Polarity Remark

1 Vss Ground 2 Vcc Power Supply +3.3 V (typical) 3 Vcc Power Supply +3.3 V (typical) 4 V 5 BIST Panel BIST enable 6 CLK 7 DATA

8 RXO0- LVDS Differential Data Input (Odd) Negative

9 RXO0+ LVDS Differential Data Input (Odd) Positive 10 Vss Ground 11 RXO1- LVDS Differential Data Input (Odd) Negative 12 RXO1+ LVDS Differential Data Input (Odd) Positive 13 Vss Ground 14 RXO2- LVDS Differential Data Input (Odd) Negative 15 RXO2+ LVDS Differential Data Input (Odd) Positive 16 Vss Ground 17 RXOC- LVDS Clock Data Input (Odd) Negative 18 RXOC+ LVDS Clock Data Input (Odd) Positive 19 Vss Ground

20 RxE0- LVDS Differential Data Input (Even) Negative 21 RxE0+ LVDS Differential Data Input (Even) Positive

22 Vss Ground 23 RxE1- LVDS Differential Data Input (Even) Negative 24 RxE1+ LVDS Differential Data Input (Even) Positive 25 Vss Ground 26 RxE2- LVDS Differential Data Input (Even) Negative 27 RxE2+ LVDS Differential Data Input (Even) Positive 28 Vss Ground 29 RXEC- LVDS Clock Data Input (Even) Negative 30 RXEC+ LVDS Clock Data Input (Even) Positive

Note (1) Connector Part No.: JAE-FI-XB30SRL-HF11 or equivalent

DDC 3.3V Power

EDID

DDC Clock

EDID

DDC Data -

EDID

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Doc No.: 1406X180

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Model No.: N141C3 - L03

Approval

Note (2) User’s connector Part No: JAE-FI-X30C2L or equivalent

Note (3) The first pixel is odd as shown in the following figure.

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5.2 BACKLIGHT UNIT

Pin Symbol Description Color

1 HV High Voltage Pink 2 LV Ground White

Note (1) Connector Part No.: JST- BHSR-02VS-1 or equivalent

Note (2) User’s connector Part No.: SM02B-BHSS-1-TB or equivalent

5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL

RXOC+

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Model No.: N141C3 - L03

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RXO2+/-

RXO1+/-

RXO0+/-

RXEC+

RXE2+/-

RXE1+/-

RXE0+/-

T/7

IN20 IN19 IN18 IN17 IN16 IN15 IN14

DE OB5 OB4 OB3 OB2 Vsync Hsync

IN13 IN12 IN11 IN10 IN9 IN8 IN7

OB1 OG4 OG3 OG2 OG1 OB0 OG5

IN6 IN5 IN4 IN3 IN2 IN1 IN0

OG0 OR3 OR2 OR1 OR0 OR5 OR4

Signal for 1 DCLK Cycle (T)

T/7

IN20 IN19 IN18 IN17 IN16 IN15 IN14

DE EB5 EB4 EB3 EB2 Vsync Hsync

IN13 IN12 IN11 IN10 IN9 IN8 IN7

EB1 EG4 EG3 EG2 EG1 EB0 EG5

IN6 IN5 IN4 IN3 IN2 IN1 IN0

EG0 ER3 ER2 ER1 ER0 ER5 ER4

Signal for 1 DCLK Cycle (T)

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5.4 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for

the color. The higher the binary input, the brighter the color. The table below provides the assignment of

color versus data input.

Color

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 Black Red Green

Basic Colors

Gray Scale Of Red

Gray Scale Of Green

Gray Scale Of Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Blue Cyan Magenta Yellow White Red(0)/Dark Red(1) Red(2)

:

: Red(61) Red(62) Red(63) Green(0)/Dark Green(1) Green(2)

:

: Green(61) Green(62) Green(63) Blue(0)/Dark Blue(1) Blue(2)

:

: Blue(61) Blue(62) Blue(63)

0

1

0

1

0

0 : :

1

0

0 : :

0

0 : :

0

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Data Signal

Red Green Blue

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

:

1

0

1

0

1

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

1

0

1

0

1

0

:

0

1

0

1

0

1

0

1

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5.5 EDID DATA STRUCTURE

The EDID (Extended Display Identification Data) data formats are to support displays as defined in the

VESA Plug & Display and FPDI standards.

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Model No.: N141C3 - L03

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Byte

ʳ

(hex)

0 0 Header 1 1 Header 2 2 Header 3 3 Header 4 4 Header 5 5 Header 6 6 Header 7 7 Header 8 8 EISA ID manufacturer name (“CMO”)

9 9 EISA ID manufacturer name (Compressed ASCII) 10 0A ID product code (N141C3-L03) 28 11 0B ID product code (hex LSB first; N141C3-L03) 14 12 0C ID S/N (fixed “0”) 13 0D ID S/N (fixed “0”) 14 0E ID S/N (fixed “0”) 15 0F ID S/N (fixed “0”) 16 10 Week of manufacture (fixed “00H”) 17 11 Year of manufacture (fixed “00H”) 18 12 EDID structure version # (“1”) 19 13 EDID revision # (“3”) 20 14 Video I/P definition (“digital”) 21 15 Active area horizontal 30.348cm 22 16 Active area vertical 18.9675cm 23 17 Display Gamma (Gamma = ”2.2”) 24 18 Feature support (“Active off, RGB Color”) 25 19 Rx1 Rx0 Ry1 Ry0 Gx1 Gx0 Gy1 Gy0 26 1A Bx1 Bx0 By1 By0 Wx1 Wx0 Wy1 Wy0 27 1B Rx=0.580 28 1C Ry=0.340 29 1D Gx=0.310

30 1E Gy=0.550 31 1F Bx=0.155 32 20 By=0.155 33 21 Wx=0.313 34 22 Wy=0.329 35 23 Established timings 1 36 24 Established timings 2 (1440*900@60Hz) 37 25 Manufacturer’s reserved timings 38 26 Standard timing ID # 1 39 27 Standard timing ID # 1 40 28 Standard timing ID # 2 41 29 Standard timing ID # 2 42 2A Standard timing ID # 3

Field Name and Comments

Value

(hex)

00 00000000 FF 11111111 FF 11111111 FF 11111111 FF 11111111 FF 11111111 FF 11111111

00 00000000 0D 00001101 AF 10101111

00 00000000

01 00000001

03 00000011

80 10000000 1E 00011110

13 00010011

78 01111000 0A 00001010

47 01000111 A0 10100000

94 10010100

57 01010111

4F 01001111

8C 10001100

27 00100111

50 01010000

54 01010100

00 00000000

01 00000001

Value

(binary)

00101000 00010100

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43 2B Standard timing ID # 3 44 2C Standard timing ID # 4 45 2D Standard timing ID # 4 46 2E Standard timing ID # 5 47 2F Standard timing ID # 5 48 30 Standard timing ID # 6 49 31 Standard timing ID # 6 50 32 Standard timing ID # 7 51 33 Standard timing ID # 7 52 34 Standard timing ID # 8 53 35 Standard timing ID # 8

Detailed timing description # 1 Pixel clock (“96.5MHz”, According to

54 36 55 37 # 1 Pixel clock (hex LSB first) 56 38 # 1 H active (“1440”) 57 39 # 1 H blank (“280”) 58 3A # 1 H active : H blank (“1440 : 280”) 59 3B # 1 V active (”900”) 60 3C # 1 V blank (”35”) 61 3D # 1 V active : V blank (”900 :35”) 62 3E # 1 H sync offset (”46”) 63 3F # 1 H sync pulse width ("70”) 64 40 # 1 V sync offset : V sync pulse width (”9 : 9”)

65 41 66 42 # 1 H image size (”303 mm”) 67 43 # 1 V image size (”190 mm”) 68 44 # 1 H image size : V image size (”303 : 190”) 69 45 # 1 H boarder (”0”) 70 46 # 1 V boarder (”0”)

71 47

72 48 73 49 # 2 Pixel clock (hex LSB first) 74 4A # 2 H active (“0”) 75 4B # 2 H blank (“0”) 76 4C # 2 H active : H blank (“0 : 0”) 77 4D # 2 V active (”0”) 78 4E # 2 V blank (”0”) 79 4F # 2 V active : V blank (”0 : 0”) 80 50 # 2 H sync offset (”0”) 81 51 # 2 H sync pulse width (”0”) 82 52 # 2 V sync offset : V sync pulse width (”0 : 0”)

83 53 84 54 # 2 H image size (”0 mm”) 85 55 # 2 V image size (”0 mm”) 86 56 # 2 H image size : V image size (”0 : 0”) 87 57 # 2 H boarder (”0”)

VESA CVT Rev1.1)

# 1 H sync offset : H sync pulse width : V sync offset : V sync width (”46: 70 : 9 : 9”)

# 1 Non-interlaced, Normal, no stereo, Separate sync, H/V pol Negatives

Detailed timing description # 2 Pixel clock (“0 MHz”, According to VESA CVT Rev1.1)

# 2 H sync offset : H sync pulse width : V sync offset : V sync width (”0 : 0 : 0 : 0”)

01 00000001

B1 10110001

25 00100101 A0 10100000

18 00011000

51 01010001

84 10000100

23 00100011

30 00110000 2E 00101110

46 01000110

99 10011001

00 00000000

2F 00101111 BE 10111110

10 00010000

00 00000000

19 00011001

00 00000000

17 / 36

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Model No.: N141C3 - L03

Approval

88 58 # 2 V boarder (”0”) 89 59 Module "A" Revision = Example: 00, 01, 02, 03, etc. 90 5A Detailed timing description # 3 91 5B # 3 Flag 92 5C # 3 Reserved

93 5D # 3 FE (hex) defines ASCII string (Model Name “N141C3”, ASCII) 94 5E # 3 Flag 95 5F # Dell P/N "MC196" 1st character (“P”) 96 60 # Dell P/N " MC196" 1st character (“Y”) 97 61 # Dell P/N " MC196" 1st character (“7”) 98 62 # Dell P/N " MC196" 1st character (“2”)

99 63 # Dell P/N " MC196" 1st character (“6”) 100 64 LCD Supplier EEDID Revision #: "7" 101 65 Manufacturer P/N ( "N") 102 66 Manufacturer P/N ( "1" ) 103 67 Manufacturer P/N ( "4" ) 104 68 Manufacturer P/N ( "1" ) 105 69 Manufacturer P/N ( "C" ) 106 6A Manufacturer P/N ( "3" )

Manufacturer P/N (If <13 char, then terminate with ASCII code 0Ah,

107 6B 108 6C Flag 109 6D Flag 110 6E Flag 111 6F Data Type Tag: 112 70 Flag 113 71 SMBUS value @ 10nits = 45d 2D 114 72 SMBUS value @ 17nits = 64d 40 115 73 SMBUS value @ 24nits = 78d 4E 116 74 SMBUS value @ 30nits = 86d 56 117 75 SMBUS value @ 60nits = 122d 7A 118 76 SMBUS value @ 100nits = 155d 9B 119 77 SMBUS value @ 160nits = 206d CE 120 78 SMBUS value @ 220 nits = 255d FF 121 79 Numbers of LVDS Recevier chip = 2 122 7A BIST Enable: Yes = '01' No = '00' ("Yes")

123 7B

124 7C

125 7D 126 7E Extension flag 127 7F Checksum

set remaining char = 20h)

(If <13 char, then terminate with ASCII code 0Ah, set remaining char = 20h)

00 00000000 00 00000000 00 00000000 00 00000000 00 00000000

FE 11111110

00 00000000 50 01010000 59 01011001 37 00110111 32 00110010 36 00110110 37 00110111

4E 01001110

31 00110001 34 00110100 31 00110001 43 01000011 33 00110011

0A 00001010

00 00000000 00 00000000 00 00000000

FE 11111110

00 00000000

02 00000010 01 00000001

0A 00001010

20 00100000

00 00000000 30 00110000

00101101 01000000

01001110

01010110

01111010 10011011 11001110

11111111

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6 INVERTER SPECIFICATION

6.1 Connector type

Input connector type: LVC-D20SFYG (HONDA)

Output connector: JST SM02B-BHSS-1-TB (JST)

6.2 Input connector pin assignment

6.2.1 Input Connector pin assignment:

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Input connector

HONDA LVC-D20SFYG

Pin Function

1 INV_SRC

2 INV_SRC

3 INV_SRC

4 INV_SRC

5 GND Ground 6 NC No Connection

7 5VALW

8 GND Ground

9 SMB_DAT

10 SMB_CLK

11 GND Ground

12 INV_PWM System side PWM input signal for brightness control

13 GND Ground

14 NC No Connection

15 DIAG_LOOP

16 GND Ground

17 5VALW

18 5VALW

19 NC No Connection

20 DIAG_LOOP

This power rail should be used as a power rail to drive the backlight DC-AC converter

This should be used as power source that stores the brightness/contrast values & the circuit that interfaces with SMB_CLK & SMB_DAT

SMBus interface for sending brightness & contrast information to the inverter/panel

Diag pin for Dell testing. Pin15 & 20 must be connected electrically on the inverter board.

This should be used as power source that stores the brightness/contrast values & the circuit that interfaces with SMB_CLK & SMB_DAT

Diag pin for Dell testing. Pin15 & 20 must be connected electrically on the inverter board.

Comments

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6.2.2 Absolute maximum ratings

Items Absolute max. ratings Unit

INV_SRC (Voltage) -1.0~23.5 V FPBACK/SMB_CLK/SMB_DAT (Voltage)

6.3 Output connector pin assignment

Pin Name Description

1 CFL-High High-voltage output to the CCFL 2 CFL-Low Low-voltage output to the CCFL

6.4 General electrical specification

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-1.0~5.5 V

6.4.1 Absolute maximum ratings

Items Absolute max. ratings Unit

INV_SRC (Voltage) -1.0~23.5 V FPBACK/SMB_CLK/SMB_DAT (Voltage)

-1.0~5.5 V

6.4.2 Electrical characteristics:

No. Item Symbol

1 Input Voltage INV_SRC 7.5 14.4 21 V

Input Signal Level for

2

Input Signal Level for

3

4 Input Power Pin(Max) 220nits@Vin=12V - - 5.5 W

Brightness Adjust (Lamp

5

5VSUS

5VALW

Current Control)

5VSUS - - - V

5VALW 4.75 5 5.2 V

SMB_DAT

Condition

Control by SMBus(256 steps dimming control)

Min. Typ. Max. Uint

00H - FFH -

6 Output Voltage Vout IL = 6.3mA(typ) 612 680 748 Vrms

Iout (Min)

Output Current

7

8 Operation Frequency Freq Vin=7.5V~21V 45 - 65 KHz

9 Burst mode frequency fB Vin=7.5V~21V 200 - 220 Hz

Iout (Max)

Vin=7.5V~21V SMB_DAT=00H Ta =2 5к, after running 30 min.

Vin=7.5V~21V SMB_DAT=FFH Ta =2 5к, after running 30 min.

20 / 36

1.5 1.8 2.1 mArms

6 6.3 6.6 mArms

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10 Open Lamp Voltage Vopen No Load 1400 -- 1800 Vrms

11 Striking Time Ts No Loadw 0.6 1 1.4 Sec

12

13 Start and Delay Time

14

zInput Voltage

zOn/Off control

zQuiescent current

zOpen lamp voltage

Efficiency K

Start –up time

(Turn on delay time)

The operating input voltage of inverter shall be defined.

The inverter shall ignite the CCFL lamp at minimum input voltage at any environment conditions.

Enable: At “ON” condition (FPBACK=Hi), enable the inverter.

Disable: At “OFF” condition (FPBACK=Lo), disable the inverter.

At the inverter “OFF” condition, input quiescent should be less than 0.1mA.

The inverter start-up output voltage will be above “Vopen” for “Ts” minimum at any condition under specify

until lamp to be ignited. The inverter should be shutdown if lamp ignition was failed in “Ts” maximum. The

inverter shall be capable of withstanding the output connections open without component over-stress / fire /

Vin=7.5V, SMB_DAT=FFH

(RES LOAD=100K ohm) Vin=14.4V, SMB_DAT=00H - 130 200 uS Vin=14.4V, SMB_DAT=FFH - - 0.1 Sec

80 - - %

smoke /arc.

zBurst mode frequency

The burst mode frequency should be in specification in any environment condition and electrical condition.

zBrightness control

SM-BUS values for panel luminance are to be included in the on LCD board EEDID ROM chip table. The

supplier will measure panel luminance in a system and define the SMBUS values for each of the 8 required

luminance levels. The panel luminance, for which SMBUS values will be provided in the EEDID from byte #

113(hex #71), to byte # 120, (hex # 78), is show in the table below. The inverter supplier should provide

these appropriate values to CMO.

Step Count Step 1 Step 2 Step3 Step 4 Step 5 Step 6 Step 7 Step 8

Address Byte

113

SM-Bus Data Value 2D 40 4E 56 7A 9B CE FF

Luminance (nits) 10 17 24 30 60 100 160 220

z Output ripple ratio

Ripple ratio = 2 * (Ipeak - Ivalley) / (Ipeak + Ivalley) * 100%

The Ripple ratio should be less than 5% and ripple frequency should be less than 200 Hz.

Byte

114

Byte

115

Byte

116

Byte

117

Byte

118

Byte

119

Byte

120

z Power up Overshoot & Undershoot

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Overshoot & Undershoot at power up should not exceed the following limits.

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Model No.: N141C3 - L03

Approval

Vin

0ШVin(min.)

0ШVin(typ.)

0ШVin(max.)

dI=Imax.-Io or dI=(Io-Imin.)/Io

z Output connections short protection

The inverter shall be capable of withstanding the output connections short without damage or over-stress.

And the inverter maximum input power shall be limited within 1W.

Output current

Io(rms)

Io(max.)

Io(min.)

Io(max.)

Io(min.)

Io(max.)

Io(min.)

Overshoot/Undershoot

150% / 50% 5 ms max.

6.4.3 Mechanical Drawing

Io (dI)

Settling time

(dT)

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7 INTERFACE TIMING

7.1 INPUT SIGNAL TIMING SPECIFICATIONS

The specifications of input signal timing are as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

DCLK Frequency 1/Tc 25 44.5 60 MHz (2)

Vertical Total Time TV 910 926 1500 TH -

Vertical Active Display Period TVD 900 900 900 TH -

DE

Note (1) Because this module is operated by DE only mode, Hsync and Vsync are ignored.

(2) 2 channels LVDS input.

Vertical Active Blanking Period TVB TV-TVD 26 TV-TVD TH

Horizontal Total Time TH 760 800 880 Tc (2)

Horizontal Active Display Period THD 720 720 720 Tc (2)

Horizontal Active Blanking Period THB

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TH-THD

80

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Approval

TH-THD

Tc (2)

INPUT SIGNAL TIMING DIAGRAM

DE

DCLK

TC

DE

DATA

7.2 POWER ON/OFF SEQUENCE

HD

T

Power Supply

for LCD, Vcc

- Interface Signal

(LVDS Signal of Transmitter), V

I

- Power for Lamp

0V

Power On

90%

10%

Power Off

t7

90%

t1

t3t2

Valid Data

t6t5

50%50%

ONOFF OFF

10%

Restart

10%

t4

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Timing Specifications:

0.5< t1 Љ 10 msec

0 < t2 Љ 50 msec

0 < t3 Љ 50 msec

t4 Њ 500 msec

t5 Њ 200 msec

t6 Њ 200 msec

Note (1) Please follow the power on/off sequence described above. Otherwise, the LCD module might be

damaged.

Note (2) Please avoid floating state of interface signal at invalid period. When the interface signal is invalid, be

sure to pull down the power supply of LCD Vcc to 0 V.

Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the

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interface signal is valid. The Backlight inverter power must be turned off before the power supply

for the logic and the interface signal is invalid.

Note (4) Sometimes some slight noise shows when LCD is turned off (even backlight is already off). To

avoid this phenomenon, we suggest that the Vcc falling time is better to follow 5Љt7Љ300 ms.

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8 OPTICAL CHARACTERISTICS

8.1 TEST CONDITIONS

Item Symbol Value Unit Ambient Temperature Ta Ambient Humidity Ha Supply Voltage VCC 3.3 V Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS" Inverter Current IL 6 mA Inverter Driving Frequency FL 61 KHz Inverter Sumida H05-4915

The relative measurement methods of optical characteristics are shown in 8.2. The following items

should be measured under the test conditions described in 8.1 and stable environment shown in Note (6).

8.2 OPTICAL SPECIFICATIONS

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 300 400 - - (2), (5)

Response Time

Average Luminance of White L5p 200 220 - cd/m2(4), (5)

Luminance Non-Uniformity

Color Gamut C.G 42 45 - % (5), (7)

Red

Color Chromaticity

Viewing Angle

Green

Blue

White

Horizontal

Vertica l

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o

25r2

50r10

TR - 5 10 ms

- 11 16 ms

T

F

GW

Rx Ry Gx Gy Bx By

5p

13p

=0q, TY =0q

T

x

Viewing Normal

Angle

- - 20 %

- - 35 %

0.580

0.340

0.310

TYP

-0.02

0.550

0.155

TYP

+0.02

0.155

Wx 0.313 -

Wy

Tx+

T

x

TY+

T

Y

CRt10

-

0.329

40 45 40 45 15 20 40 45 -

C

%RH

(3)

(5), (6)

-

(1), (5)

-

Deg.

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.67 ms

Note (1) Definition of Viewing Angle (Tx, Ty):

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Normal

Tx = Ty = 0º

Ty- Ty

TX- = 90º

6 o’clock

T

y- = 90º

x-

y-

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Contrast Ratio (CR) = L

/ L

63

0

L63: Luminance of gray level 63

L

: Luminance of gray level 0

0

CR = CR (5)

CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6).

Tx

Tx

y+

12 o’clock direction

T

y+ = 90º

x+

TX+ = 90º

Note (3) Definition of Response Time (T

100%

90%

Optical

Response

10%

0%

T

R

66.67 ms

, TF):

R

66

Time

T

F

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Note (4) Definition of Average Luminance of White (L5p):

Measure the luminance of gray level 63 at 5 points

L

= [L (5)+ L (10)+ L (11)+ L (12)+ L (13)] / 5

5p

L (x) is corresponding to the luminance of the point X at Figure in Note (6)

Note (5) Measurement Setup:

The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting Backlight for 20 minutes in a windless room.

LCD Module

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LCD Panel

Center of the Screen

500 mm

Photometer

(USB-2000, CS-1000T)

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (6) Definition of White Variation (GW5p, GW

Measure the luminance of gray level 63 at 5, 13 points

GW

={1-{ Minimum [L (5)+ L (10)+ L (11)+ L (12)+ L (13)] / Maximum [L (5)+ L (10)+ L (11)+ L (12)+

5p

L (13)]}} *100%

GW

={1-{ Minimum [L (1) ~ L (13)] / Maximum [L (1) ~ L (13)]}} *100%

13p

):

X

: Test Point

X=1 to 5

Note (7) Definition of color gamut (C.G):

C.G= 'R G B /'R

R

, G0, B0: color coordinates of red, green, and blue defined by NTSC, respectively.

0

0 G0 B0

,*100%

R, G, B : color coordinates of module on 63 gray levels of red, green, and blue, respectively.

'R

0 G0 B0

: area of triangle defined by R0, G0, B

0

'R G B: area of triangle defined by R, G, B

˖˜˘ ʳ˄ˌ ˆ˄

˃ˁˌ

˃ˁˋ

˃ˁˊ

˃ˁˉ

˃ˁˈ

˃ˁˇ

˃ˁˆ

˃ˁ˅

˃ˁ˄

˃

˃ ˃ˁ˅ ˃ˁˇ ˃ˁˉ ˃ˁˋ

G

0

G

R

0

R

B

0

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9 PRECAUTIONS

9.1 ASSEMBLY AND HANDLING PRECAUTIONS

(1) The module should be assembled into the system firmly by using every mounting hole. Be

careful not to twist or bend the module.

(2) While assembling or installing modules, it can only be in the clean area. The dust and oil may cause

electrical short or damage the polarizer.

(3) Use fingerstalls or soft gloves in order to keep display clean during the incoming inspection and

assembly process.

(4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizer is

very soft and easily scratched.

(5) If the surface of the polarizer is dirty, please clean it by some absorbent cotton or soft cloth. Do not use

Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might

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permanently damage the polarizer due to chemical reaction.

(6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on panel for

a long time.

(7) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contacting with hands, legs or clothes, it must be washed away thoroughly with soap.

(8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC.

(9) Do not disassemble the module.

(10) Do not pull or fold the lamp wire.

(11) Pins of I/F connector should not be touched directly with bare hands.

9.2 SAFETY PRECAUTIONS

(1) High temperature or humidity may reduce the performance of module. Please store LCD module within

the specified storage conditions.

(2) It is dangerous that moisture come into or contacted the LCD module, because the moisture may

damage LCD module when it is operating.

(3) It may reduce the display quality if the ambient temperature is lower than 10 ºC. For example, the

response time will become slowly, and the starting voltage of lamp will be higher than the room

temperature.

9.3 OPERATION PRECAUTIONS

(1) Do not pull the I/F connector in or out while the module is operating.

(2) Always follow the correct power on/off sequence when LCD module is connecting and operating. This

can prevent the CMOS LSI chips from damage during latch-up.

(3) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock while

assembling with inverter. Do not disassemble the module or insert anything into the Backlight unit.

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10 PACKAGING

10.1 CARTON

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Figure. 10-1 Packing method

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10.2 PALLET

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Figure. 10-2 Packing method

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11.DEFINITION OF LABELS

11.1 CMO MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following explanation.

N141C3 -L03

(a) Model Name: N141C3 - L03

(b) Revision: Rev. XX, for example: A1, …, C1, C2 …etc.

(c) Serial ID: X X

(d) Production Location: MADE IN XXXX. XXXX stands for production location.

(e) LEOO: UL compliance remarks for CMO NingBo site production. It won’t be available when production

location isn’t CMO NingBo.

Serial ID includes the information as below:

(a) Manufactured Date: Year: 1~9, for 2001~2009

(b) Revision Code: cover all the change

(c) Serial No.: Manufacturing sequence of product

X X X X X Y M D X N N N N

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1

Serial No.

CMO Internal Use

Year, Month, Date

CMO Internal Use

Revision

CMO Internal Use

st

to 31st, exclude I , O and U

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11.2 CMO CARTON LABEL

(a) Production location: Made In XXXX. XXXX stands for production location.

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11.3 CARTON LABEL

PKG ID (3S)124161241729112345609886C20

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REV.A06

DP/N 03J849

BOX Qty 20 Made in Taiwan

11.4 PALLET LABEL

FROM :CMO Corporation

Tainan, Taiwan 744 R.O.C

P.O.NUMBER

12345678

COUNTRY OF ORIGIN

TW

TO:DELL COMPUTER

2128 West Braker Austin TX

DELL P/N

12345

PACKING LIST# 1234567890123

Vendor ID Loc Id

12416 12416

Mfg Id 70896

PACKING LIST QTY 654321

DESTINATION MAS LOC

DESTINATION LOCATION

B4

12345678901234567890

PKG CNT 999 OF 999 12345

PART DESCRIPTION XXXXXXXXXXXXXXXXXXXXXXXXX

12345678901234567890123456789012345678901

BOX CNT REVISION

A00-00 Apr 29,2003

60

AIRBILL NUMBER

SHIP DATE

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CMO N141C3-L03 Specification

Specifications and Main Features

Frequently Asked Questions

User Manual