CMO N121I3-L04 Specification

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A

TFT LCD Approval Specification

MODEL NO.: N121I3 - L04

www.panelook.com

DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Dell P/N: JF295

Customer : Dell

pproved by :

Note :











2006-08-08 17:41:13
CST

2006-08-02 09:34:47
CST

Approve by Dept.
Mgr.(QA RA)

Approve by Director

tony_wang(׆஡࣑
/43171/54985)

teren_lin(ࣥ෌ո
/56910/36064)

Assignee Accept

Director Accept

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

- CONTENTS -

REVISION HISTORY

1. GENERAL DESCRIPTION

1.1 OVERVIEW

1.2 FEATURES

1.3 APPLICATION

1.4 GENERAL SPECIFICATIONS

1.5 MECHANICAL SPECIFICATIONS

2. ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

2.2.2 BACKLIGHT UNIT

3. ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE

3.2 BACKLIGHT UNIT

4. BLOCK DIAGRAM

4.1 TFT LCD MODULE

4.2 BACKLIGHT UNIT

5. INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE

5.2 BACKLIGHT UNIT

5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL

5.4 COLOR DATA INPUT ASSIGNMENT

5.5 EDID DATA STRUCTURE

5.6 EDID SIGNAL SPECIFICATION

6. INVERTER SPECIFICATION

6.1CONNECTOR TYPE

6.2 INPUT CONNECTOR PIN ASSIGNMENT

6.3 OUTPUT CONNECTOR PIN ASSIGNMENT

6.4 GENERAL ELECTRICAL SPECIFICATION

7.INTERFACE TIMING ------------------------------------------------------- 24

7.1 INPUT SIGNAL TIMING SPECIFICATIONS

7.2 POWER ON/OFF SEQUENCE

8. OPTICAL CHARACTERISTICS

8.1 TEST CONDITIONS

8.2 OPTICAL SPECIFICATIONS

9. PRECAUTIONS

9.1 HANDLING PRECAUTIONS

9.2 STORAGE PRECAUTIONS

9.3 OPERATION PRECAUTIONS

10. PACKING ------------------------------------------------------- 31

10.1 CARTON

10.2 PALLET

------------------------------------------------------- 4

------------------------------------------------------- 5

------------------------------------------------------- 6

------------------------------------------------------- 8

------------------------------------------------------- 12

------------------------------------------------------- 13

------------------------------------------------------- 20

------------------------------------------------------- 26

------------------------------------------------------- 30

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11. DEFINITION OF LABELS

11.1 MODULE LABEL

11.2 CARTON LABEL

11.3 CUSTOMER CARTON LABEL

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

------------------------------------------------------- 33

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

REVISION HISTORY

Version Date

Ver 3.0

Ver 3.1

Jul. 20,’06

Jul. 31, ‘06

Page

(New)

All

10

Section Description

All

Approval specification first issued.

3.2

Update backlight power consumption by customer definition

4 / 36

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1 GENERAL DESCRIPTION

1.1 OVERVIEW

N121I3 -L04 is a 12.1” TFT Liquid Crystal Display module with single CCFL Backlight unit and 20 pins

LVDS interface. This module supports 1280 x 800 Wide-XGA mode and can display 262,144 colors. The

optimum viewing angle is at 6 o’clock direction. The inverter module for Backlight is built in.

1.2 FEATURES

- Thin and light weight

- WXGA (1280 x 800 pixels) resolution

- 3.3V LVDS (Low Voltage Differential Signaling) interface with 1 pixel/clock

- RoHS compliance

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

1.3 APPLICATION

- TFT LCD Notebook

1.4 GENERAL SPECIFICATI0NS

Item Specification Unit Note
Active Area 261.12 (H) x 163.2 (V) (12.1” diagonal) mm
Bezel Opening Area 263.12 (H) x 165.2 (V) mm
Driver Element a-si TFT active matrix - ­Pixel Number 1280 x R.G.B. x 800 pixel ­Pixel Pitch 0.204 (H) x 0.204 (V) mm ­Pixel Arrangement RGB vertical stripe - ­Display Colors 262,144 color ­Transmissive Mode Normally white - ­Surface Treatment Hard coating (3H), Anti-glare type - -

1.5 MECHANICAL SPECIFICATIONS

Item Min. Typ. Max. Unit Note

Horizontal(H) 275.3 275.8 276.3 mm

Module Size

Note (1) Please refer to the attached drawings for more information of front and back outline dimensions.

Vertical(V) 177.4 178 178.6 mm
Depth(D) - 4.9 5.2 mm

Weight

- 260 275 g (2)

- 275 290 g (3)

(1)

(1)

Note (2) Weight without inverter & inverter bracket.

Note (3) Weight with inverter & inverter bracket.

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A

2 ABSOLUTE MAXIMUM RATINGS

2.1 ABSOLUTE RATINGS OF ENVIRONMENT

Item Symbol

Storage Temperature TST -20 +60 ºC (1)
Operating Ambient Temperature TOP 0 +50 ºC (1), (2)
Shock (Non-Operating) S
Vibration (Non-Operating) V

Note (1) (a) 90 %RH Max. (Ta Љ 40 ºC).

(b) Wet-bulb temperature should be 39 ºC Max. (Ta > 40 ºC).

(c) No condensation.

Note (2) The temperature of panel display surface area should be 0 ºC Min. and 60 ºC Max.

Relative Humidity (%RH)

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Value

Min. Max.

- 200/2 G/ms (3), (5)

NOP

- 1.5 G (4), (5)

NOP

Unit Note

100

90

80

60

Operating Range

40

20
10

Storage Range

Temperature (ºC)

Note (3) 1 time for ± X, ± Y, ± Z. for Condition (200G / 2ms) is half Sine Wave,.

Note (4) 10 ~ 500 Hz, 30 min/cycle,1cycles for each X, Y, Z axis.

8060-20 400 20-40

Note (5) At testing Vibration and Shock, the fixture in holding the module has to be hard and rigid

enough so that the module would not be twisted or bent by the fixture.

The fixing condition is shown as below:

t Room Temperature

Side Mount Fixing Screw

Gap=2mm

Bracket

LCD Module

Side Mount Fixing Screw

Stage

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2.2 ELECTRICAL ABSOLUTE RATINGS

2.2.1 TFT LCD MODULE

Item Symbol

Power Supply Voltage Vcc -0.3 +4.0 V
Logic Input Voltage VIN -0.3 Vcc+0.3 V

2.2.2 BACKLIGHT UNIT

Item Symbol

Lamp Voltage VL - 2.5K V
Lamp Current IL 2.0 6.5 mA
Lamp Frequency FL 50 80 KHz

Note (1) Permanent damage to the device may occur if maximum values are exceeded. Function operation

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Value

Min. Max.

Value

Min. Max.

Unit Note

Unit Note

DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

(1)

(1), (2), IL = 6.0 mA

RMS

RMS

(1), (2)

should be restricted to the conditions described under Normal Operating Conditions.

Note (2) Specified values are for lamp (Refer to Section 3.2 for further information

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

3 ELECTRICAL CHARACTERISTICS

3.1 TFT LCD MODULE Ta = 25 ± 2 ºC

Parameter Symbol

Min. Typ. Max.
Power Supply Voltage Vcc 3.0 3.3 3.6 V ­Ripple Voltage VRP - 100 mV ­Rush Current I

Power Supply Current

White - 270 300 mA (3)a
Black

LVDS Differential Input High Threshold V

LVDS Differential Input Low Threshold V

- 1.2 1.5 A (2)

RUSH

lcc

TH(LVDS)

TL(LVDS)

- 330 360 mA (3)b

+100 mV

-100 mV

LVDS Common Mode Voltage VCM 1.125 1.375 V (5)
LVDS Differential Input Voltage |VID| 100 600 mV (5)
Terminating Resistor RT - 100 - Ohm ­Power per EBL WG P

- 2.873 - W (4)

EBL

Note (1) The module should be always operated within above ranges.

Value

Unit Note

Approval

(5),

=1.2V

V

CM

(5)

=1.2V

V

CM

Note (2) Measurement Conditions:

+3.3V

R1

47K

(High to Low)

(Control Signal)

SW

+12V

C1

1uF

VR1

R2

1K

47K

Vcc rising time is 470us

Q1 2SK1475

C2

0.01uF

Q2

2SK1470

FUSE

C3

1uF

Vcc

(LCD Module Input)

+3.3V

0.9Vcc

0.1Vcc

GND

470us

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|

|

Note (3) The specified power supply current is under the conditions at Vcc = 3.3 V, Ta = 25 ± 2 ºC, DC

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Current and f

Note (4) The specified power are the sum of LCD panel electronics input power and the inverter input

a. White Pattern

power. Test conditions are as follows.

(a) Vcc = 3.3 V, Ta = 25 ± 2 ºC, f

(b) The pattern used is a black and white 32 x 36 checkerboard, slide #100 from the VESA file

= 60 Hz, whereas a power dissipation check pattern below is displayed.

v

b. Black Pattern

Active Area

= 60 Hz,

v

Active Area

“Flat Panel Display Monitor Setup Patterns”, FPDMSU.ppt.

(c) Luminance: 60 nits.

(d) The inverter used is provided from O2Micro(www.o2micro.com). CMO doesn’t provide the

inverter in this product.

Note (5) The parameters of LVDS signals are defined as the following figures.

Single Ended

Differential

CM

V

0V

V

0V

V

VID|

VID|

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

3.2 BACKLIGHT UNIT Ta = 25 ± 2 ºC

Parameter Symbol

Min. Typ. Max.
Lamp Input Voltage VL 540 600 660 V
Lamp Current IL 2.0 6.0 6.5 mA

Lamp Turn On Voltage VS

- - 1220 (25

- - 1400 (0
Operating Frequency FL 50 - 80 KHz (3)
Lamp Life Time LBL 15,000 - - Hrs (5)
Power Consumption PBL 3.6 4.0 4.4 W (4), IL = 6.0 mA

Note (1) Lamp current is measured by utilizing a high frequency current meter as shown below:

Value

o

C) V

o

C) V

Unit Note

I

RMS

RMS

(2)

RMS

(2)

RMS

= 6.0 mA

L

(1)

LCD

Module

HV (Pink)

LV (White)

1

2

Current Meter

Inverter

A

Note (2) The voltage that must be larger than Vs should be applied to the lamp for more than 1 second

after startup. Otherwise the lamp may not be turned on.

Note (3) The lamp frequency may produce interference with horizontal synchronous frequency from the

display, and this may cause line flow on the display. In order to avoid interference, the lamp

frequency should be detached from the horizontal synchronous frequency and its harmonics as far

as possible.

Note (4) P

= Inverter input power

BL

Inverter input power is measured at 8

th

step(the max brightness step) @ Vin=12V

Note (5) The lifetime of lamp can be defined as the time in which it continues to operate under the condition

Ta = 25 2

o

C and IL = 6 mArms until one of the following events occurs:

(a) When the brightness becomes or lower than 50% of its original value.

(b) When the effective ignition length becomes or lower than 80% of its original value. (Effective

ignition length is defined as an area that has less than 70% brightness compared to the

brightness in the center point.)

Note (6) The waveform of the voltage output of inverter must be area-symmetric and the design of the

inverter must have specifications for the modularized lamp. The performance of the Backlight,

such as lifetime or brightness, is greatly influenced by the characteristics of the DC-AC inverter for

the lamp. All the parameters of an inverter should be carefully designed to avoid generating too

much current leakage from high voltage output of the inverter. When designing or ordering the

inverter please make sure that a poor lighting caused by the mismatch of the Backlight and the

inverter (miss-lighting, flicker, etc.) never occurs. If the above situation is confirmed, the module

should be operated in the same manners when it is installed in your instrument.

The output of the inverter must have symmetrical (negative and positive) voltage waveform and

symmetrical current waveform.(Unsymmetrical ratio is less than 10%) Please do not use the inverter

which has unsymmetrical voltage and unsymmetrical current and spike wave. Lamp frequency may

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produce interface with horizontal synchronous frequency and as a result this may cause beat on the

display. Therefore lamp frequency shall be as away possible from the horizontal synchronous

frequency and from its harmonics in order to prevent interference.

Requirements for a system inverter design, which is intended to have a better display performance, a

better power efficiency and a more reliable lamp. It shall help increase the lamp lifetime and reduce its

leakage current.

a. The asymmetry rate of the inverter waveform should be 10% below;

b. The distortion rate of the waveform should be within Ѕ2 ± 10%;

c. The ideal sine wave form shall be symmetric in positive and negative polarities.

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

* Asymmetry rate:

I p

I -p

| I

* Distortion rate

I

– I –p | / I

p

(or I –p) / I

p

rms

rms

* 100%

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)

4 BLOCK DIAGRAM

4.1 TFT LCD MODULE

Rxin0(+/-)

Rxin1(+/-)

Rxin2(+/-)

CLK(+/-)

Vcc

( DF19KR-20P-1H or equivalent )

INPUT CONNECTOR

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LVDS INPUT /

TIMING CONTROLLER

DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

SCAN DRIVER IC

TFT LCD PANEL

(1280x3x800)

GND

Data

EDID

CLK

EDID

V

EDID

VL

LAMP CONNECTOR

(JST-BHSR-02VS-1)

4.2 BACKLIGHT UNIT

DC/DC CONVERTER &

REFERENCE VOLTAGE

GENERATOR

EDID

EEPROM

DATA DRIVER IC

BACKLIGHT UNIT

1 HV (Pink)

2 LV (White

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5 INPUT TERMINAL PIN ASSIGNMENT

5.1 TFT LCD MODULE

Pin Symbol Description Polarity Remark

1 VSS Ground ­2 VDD Power Supply +3.3 V ­3 VDD Power Supply +3.3 V ­4 V
5 TEST Panel Self Test
6 CLK
7 Data
8 Rxin0- LVDS Differential Data Input Negative
9 Rxin0+ LVDS Differential Data Input Positive

10 VSS Ground

11 Rxin1- LVDS Differential Data Input Negative
12 Rxin1+ LVDS Differential Data Input Positive
13 VSS Ground
14 Rxin2- LVDS Differential Data Input Negative
15 Rxin2+ LVDS Differential Data Input Positive
16 VSS Ground
17 CLK- LVDS Clock Data Input Negative
18 CLK+ LVDS Clock Data Input Positive
19 VSS Ground - ­20 VSS Ground - -

Note (1) Connector Part No.: DF19KR-20P-1H or equivalent

DDC +3.3 V

EDID

DDC Clock

EDID

DDC Data

EDID

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

R0~R5,G0-

G1~G5,B0,B1

-

B2~B5,Hsync,Vsync,DE

LVDS Level

Note (2) User’s connector Part No: DF19G-20S-1C or equivalent

5.2 BACKLIGHT UNIT

Pin Symbol Description Color

1 HV High Voltage Pink
2 LV Ground White

Note (1) Connector Part No.: JST-BHSR-02VS-1 or equivalent

Note (2) User’s connector Part No.: JST-SM02B-BHSS-1-TB or equivalent

5.3 TIMING DIAGRAM OF LVDS INPUT SIGNAL

CLK+

Rxin2

Rxin1

Rxin0

T/7

IN20 IN19 IN18 IN17 IN16 IN15 IN14

DE B5 B4 B3 B2 Vsync Hsync

IN13 IN12 IN11 IN10 IN9 IN8 IN7

B1 G4 G3 G2 G1 B0 G5

IN6 IN5 IN4 IN3 IN2 IN1 IN0

G0 R3 R2 R1 R0

R5

R4

Signal for 1 DCLK Cycle (T)

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5.4 COLOR DATA INPUT ASSIGNMENT

The brightness of each primary color (red, green and blue) is based on the 6-bit gray scale data input for

the color. The higher the binary input the brighter the color. The table below provides the assignment of

color versus data input.

Color

R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0
Black
Red
Green

Basic
Colors

Gray
Scale
Of
Red

Gray
Scale
Of
Green

Gray
Scale
Of
Blue

Note (1) 0: Low Level Voltage, 1: High Level Voltage

Blue
Cyan
Magenta
Yellow
White
Red(0)/Dark
Red(1)
Red(2)

:

:
Red(61)
Red(62)
Red(63)
Green(0)/Dark
Green(1)
Green(2)

:

:
Green(61)
Green(62)
Green(63)
Blue(0)/Dark
Blue(1)
Blue(2)

:

:
Blue(61)
Blue(62)
Blue(63)

0

0

1

1

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

1

1

1

1

1

1

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

0

0

0

0

0

0

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Data Signal

Red Green Blue

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

:

:

:

:

:

:

:

:

:

:

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:

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:

:

:

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1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

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0

1

1

1

1

1

0

0

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1

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1

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0

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0

0

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0

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0

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0

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

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5.5 EDID DATA STRUCTURE

The EDID (Extended Display Identification Data) data formats are to support displays as defined in the

VESA Plug & Display and FPDI standards.

Byte #
(decimal)

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37

38

39
40
41

Byte #
(hex)

Field Name and Comments

0 Header
1 Header
2 Header
3 Header
4 Header
5 Header
6 Header
7 Header
8 EISA ID manufacturer name (“CMO”)

9 EISA ID manufacturer name (Compressed ASCII)
0A ID product code (N121I3-L04) 15
0B ID product code (hex LSB first; N121I3-L04) 12

0C ID S/N (fixed “0”)
0D ID S/N (fixed “0”)

0E ID S/N (fixed “0”)
0F ID S/N (fixed “0”)
10 Week of manufacture (fixed “00H”)

11 Year of manufacture (fixed “00H”)
12 EDID structure version # (“1”)
13 EDID revision # (“5”)
14 Video I/P definition (“digital”)
15 Max H image size (“26cm”)
16 Max V image size (“16cm”)
17 Display Gamma (Gamma = ”2.2”)
18 Feature support (“Active off, RGB Color”)
19 Red/Green (Rx1, Rx0, Ry1, Ry0, Gx1, Gx0, Gy1, Gy0)
1A Blue/White (Bx1, Bx0, By1, By0, Wx1, Wx0, Wy1, Wy0)
1B Red-x (Rx = “0.572”)

1C Red-y (Ry = “0.336”)
1D Green-x (Gx = ”0.328”)

1E Green-y (Gy = ”0.570”)
1F Blue-x (Bx = ”0.154”)
20 Blue-y (By = ”0.139”)
21 White-x (Wx = ”0.313”)
22 White-y (Wy = ”0.329”)
23 Established timings 1
24 Established timings 2 (1280*800@60Hz)
25 Manufacturer’s reserved timings

26 Standard timing ID # 1
27 Standard timing ID # 1
28 Standard timing ID # 2
29 Standard timing ID # 2

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Value
(hex)

Value

(binary)
00 00000000
FF 11111111
FF 11111111
FF 11111111
FF 11111111
FF 11111111
FF 11111111
00 00000000
0D 00001101
AF 10101111

00010101

00010010
00 00000000
00 00000000
00 00000000
00 00000000
00 00000000
00 00000000
01 00000001
05 00000101
80 10000000
1A 00011010
10 00010000
78 01111000
0A 00001010
80 10000000
A5 10100101
92 10010010
56 01010110
54 01010100
92 10010010
27 00100111
23 00100011
50 01010000
54 01010100
00 00000000
00 00000000
00 00000000

01 00000001

01 00000001
01 00000001
01 00000001

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

42
43
44
45
46
47
48
49
50
51
52
53

54

55
56
57
58
59
60
61
62
63
64

65

66
67
68
69
70

71

72

73
74
75
76
77
78
79
80
81

82 52 # 2 V sync offset : V sync pulse width (”3 : 6”)

83

84

2A Standard timing ID # 3

2B Standard timing ID # 3
2C Standard timing ID # 4
2D Standard timing ID # 4

2E Standard timing ID # 5

2F Standard timing ID # 5

30 Standard timing ID # 6

31 Standard timing ID # 6

32 Standard timing ID # 7

33 Standard timing ID # 7

34 Standard timing ID # 8

35 Standard timing ID # 8

Detailed timing description # 1 Pixel clock (“67.65MHz”,

36

According to VESA CVT Rev1.1)
37 # 1 Pixel clock (hex LSB first)
38 # 1 H active (“1280”)
39 # 1 H blank (“90”)
3A # 1 H active : H blank (“1280 : 90”)
3B # 1 V active (”800”)

3C # 1 V blank (”23”)
3D # 1 V active : V blank (”800 :23”)

3E # 1 H sync offset (”18”)
3F # 1 H sync pulse width ("12”)
40 # 1 V sync offset : V sync pulse width (”3 : 6”)

# 1 H sync offset : H sync pulse width : V sync offset : V sync
41

width (”18:12 : 3 : 6”)
42 # 1 H image size (”261 mm”)
43 # 1 V image size (”163 mm”)
44 # 1 H image size : V image size (”261 : 163”)
45 # 1 H boarder (”0”)
46 # 1 V boarder (”0”)

# 1 Non-interlaced, Normal, no stereo, Separate sync, H/V pol

Negatives, DE only note: LSB is set to “1” if panel is DE-timing
47

only. H/V can be ignored.

Detailed timing description # 2 Pixel clock (“58.75 MHz”,
48

According to VESA CVT Rev1.1)
49 # 2 Pixel clock (hex LSB first)
4A # 2 H active (“1280”)
4B # 2 H blank (“160”)

4C # 2 H active : H blank (“1280 : 160”)
4D # 2 V active (”800”)

4E # 2 V blank (”19”)
4F # 2 V active : V blank (”800 : 19”)
50 # 2 H sync offset (”48”)
51 # 2 H sync pulse width (”32”)

# 2 H sync offset : H sync pulse width : V sync offset : V sync
53

width (”48 : 32 : 3 : 6”)
54 # 2 H image size (”261 mm”)

01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001
01 00000001

6D 01101101

1A 00011010
00 00000000
5A 01011010
50 01010000
20 00100000
17 00010111
30 00110000
12 00010010
0C 00001100
36 00110110

00 00000000

05 00000101
A3 10100011
10 00010000
00 00000000
00 00000000

18 00011000

F3 11110 0 11

16 00010110
00 00000000
A0 10100000
50 01010000
20 00100000
13 00010011
30 00110000
30 00110000
20 00100000
36 00110110

00 00000000

05 00000101

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

85
86
87
88

89

90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106

107

108
109
110
111
112
113
114
115
116
117
118
119
120
121
122

123

124

125

126
127

55 # 2 V image size (”163 mm”)
56 # 2 H image size : V image size (”261 : 163”)
57 # 2 H boarder (”0”)
58 # 2 V boarder (”0”)

Module "A" Revision =00 Example: 00, 01, 02, 03,
59

etc.
5A Detailed timing description # 3
5B # 3 Flag

5C # 3 Reserved
5D # 3 FE (hex) defines ASCII string (Model Name “N121I3”, ASCII)

5E # 3 Flag
5F # Dell P/N "N5015" 1st character (“J”)
60 # Dell P/N " N5015" 1st character (“F”)
61 # Dell P/N " N5015" 1st character (“2”)
62 # Dell P/N " N5015" 1st character (“9”)
63 # Dell P/N " N5015" 1st character (“5”)
64 LCD Supplier EEDID Revision #: "5"
65 Manufacturer P/N ( "N")
66 Manufacturer P/N ( "1" )
67 Manufacturer P/N ( "2" )
68 Manufacturer P/N ( "1" )
69 Manufacturer P/N ( "I" )
6A Manufacturer P/N ( "3" )

Manufacturer P/N (If <13 char, then terminate with ASCII code
6B

0Ah, set remaining char = 20h)

6C Flag
6D Flag

6E Flag
6F Data Type Tag:
70 Flag
71 SMBUS value @ 10 [cd/m2]=43 2B
72 SMBUS value @ 17 [cd/m2]=61 3D
73 SMBUS value @24 [cd/m2]=70 46
74 SMBUS value @ 30 [cd/m2]=79 4F
75 SMBUS value @ 60 [cd/m2]=114 72
76 SMBUS value @ 100 [cd/m2]=142 8E
77 SMBUS value @ 140[cd/m2]=175 AF
78 SMBUS value @ 180 [cd/m2]=214 D6
79 Numbers of LVDS Recevier chip = 1
7A BIST Enable: Yes = '01' No = '00' ("Yes")

(If <13 char, then terminate with ASCII code 0Ah, set remaining
7B

char = 20h)

(If <13 char, then terminate with ASCII code 0Ah, set remaining

7C

char = 20h)

(If <13 char, then terminate with ASCII code 0Ah, set remaining

7D

char = 20h)
7E Extension flag
7F Checksum

A3 10100011
10 00010000
00 00000000
00 00000000

00 00000000

00 00000000
00 00000000
00 00000000
FE 11111110
00 00000000
4A 01001010
46 01000110
32 00110010
39 00111001
35 00110101
35 00110101
4E 01001110
31 00110001
32 00110010
31 00110001
49 01001001
33 00110011

0A 00001010

00 00000000
00 00000000
00 00000000
FE 11111110
00 00000000

00101011

00111101

01000110

01001111
01110010
10001110
10101111

11010110
01 00000001
01 00000001

0A 00001010

20 00100000

20 00100000

00 00000000
13 00010011

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5.6 EDID SIGINAL SPECIFICATION

(1) EDID Power

Parameter Symbol Test Condition Min. Typ. Max. Unit

Power supply

voltage

Vcc — 1.8 — 5.5 V

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

(2) DC characteristics

Parameter Symbol Test Condition Min Typ Max Unit

Supply current Vcc=5.0V Icc READ at 100kHz — 0.4 1.0 mA

Supply current Vcc=5.0V Icc WRITE at 100kHz — 2.0 3.0 mA

Standby Current ISB Vin=Vcc or Vss — 1.6 4.0 μA

Input Leakage Current ILI Vin=Vcc or Vss — 0.1 10 μA

Onput Leakage Current ILO Vout=Vcc or Vss — 0.1 10 μA

Input Low Level VIL — -1.0 — Vcc x 0.3 V

Input High Level VIH — Vcc x 0.7 — Vcc+0.5 V

Output Low Level Vcc=3.0V VOL1 IOL=3mA — — 0.4 V

Output Low Level Vcc=1.8V VOL2 IOL=1.5mA — — 0.5 V

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(3) AC characteristics (VCC=1.8~5.5V standard operation mode)

Parameter Symbol Min Max Unit

Clock Frequency, SCL FSCL — 100 kHz

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Clock Pulse Width Low TLOW 4.7 —

Clock Pulse Width High THIGH 4.0 —

Noise Suppression Time TI — 100 ns

Clock Low to Data Out Valid TAA 0.1 4.5

Time the bus must be free

BUF 4.7 —

before a new transmission

can start

Start Hold Time THD.STA 4.7 —

Start Set-up Time TSU.STA 4.7 —

Data in Hold Time THD.DAT 0 —

Data in Set-up Time TSU.DAT 200 — ns

Inputs Rise Time TR — 1.0

T

Ӵs

Ӵs

Ӵs

Ӵs

Ӵs

Ӵs

Ӵs

Ӵs

Inputs Fall Time TF — 300 ns

Stop Set-up Time TSU.STO 4.7 —

Data Out Hold Time TDH 100 — ns

Write Cycle Time TWR — 10 ms

Ӵs

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6. INVERTER SPECIFICATION

6.1 CONNECTOR TYPE

Input connector type: LVC-D20SFYG (HONDA)

Output connector: JST SM02B-BHSS-1-TB (JST)

6.2 INPUT CONNECTOR PIN ASSIGNMENT

Input Connector pin assignment:

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

Input connector

HONDA LVC-D20SFYG

Pin Function

1 INV_SRC

2 INV_SRC

3 INV_SRC

4 INV_SRC

5 GND Ground
6 NC No Connection

7 5VALW

8 GND Ground

9 SMB_DAT

10 SMB_CLK

11 GND Ground

12 INV_PWM System side PWM input signal for brightness control

13 GND Ground

14 NC No Connection

15 ~ 20 NC No Connection

This power rail should be used as a power rail to drive the backlight
DC-AC converter

This power rail should be used as a power rail to drive the backlight
DC-AC converter

This power rail should be used as a power rail to drive the backlight
DC-AC converter

This power rail should be used as a power rail to drive the backlight
DC-AC converter

This should be used as power source that stores the brightness/contrast
values & the circuit that interfaces with SMB_CLK & SMB_DAT

SMBus interface for sending brightness & contrast information to the
inverter/panel

SMBus interface for sending brightness & contrast information to the
inverter/panel

Comments

Absolute maximum ratings

Items Absolute max. ratings Unit

INV_SRC (Voltage) -1.0~23.5 V
FPBACK/SMB_CLK/SMB_DAT
(Voltage)

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-1.0~5.5 V

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6.3 OUTPUT CONNECTOR PIN ASSIGNMENT

Pin Name Description

1 CFL-High High-voltage output to the CCFL
2 CFL-Low Low-voltage output to the CCFL

6.4 GENERAL ELECTRICAL SPECIFICATION

6.4.1Absolute maximum ratings

Items Absolute max. ratings Unit

INV_SRC (Voltage) -1.0~23.5 V
FPBACK/SMB_CLK/SMB_DAT
(Voltage)

6.4.2 Electrical characteristics:

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

-1.0~5.5 V

No. Item Symbol

1 Input Voltage INV_SRC 7.5 14.4 21 V

Input Signal Level for

2

Brightness Adjust (Lamp

3

4 Input Power Pin(Max) Vin=12V, SMBus=FFH - - 4.6 W

5 Output Voltage Vout IL = 6.0mA(typ) 540 600 660 Vrms

6 Output Current

5VALW

Current Control)

5VALW 4.75 5 5.2 V

SMB_DAT

Iout (Min)

Condition

Control by SMBus(256 steps
dimming control)

MAXIM solution:

Vin=7.5V~21V SMB_DAT=00H
Ta =2 5к, after running 30 min.

MPS solution:

Vin=7.5V~21V SMB_DAT=00H
Ta =2 5к, after running 30 min.

Min. Typ. Max. Uint

00H - FFH -

˄ˁˈʳ ˄ˁˋʳ ˅ˁ˄ʳ mArms

˄ˁ˅ʳ ˄ˁˈʳ ˄ˁˋʳ mArms

Iout (Max)

7 Operation Frequency Freq Vin=7.5V~21V 45 - 65 KHz

8 Burst mode frequency fB Vin=7.5V~21V 200 210 220 Hz

9 Open Lamp Voltage Vopen No Load 1400 -- 1800 Vrms

10 Striking Time Ts No Loadw 0.6 1 1.4 Sec

Vin=7.5V~21V SMB_DAT=FFH
Ta =2 5к, after running 30 min.

ˈˁˊʳ ˉˁ˃ʳ ˉˁˆʳ mArms

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

11

12 Start and Delay Time

13

zInput Voltage

zOn/Off control

zQuiescent current

zOpen lamp voltage

Efficiency K

Start –up time

(Turn on delay time)

The operating input voltage of inverter shall be defined.

The inverter shall ignite the CCFL lamp at minimum input voltage at any environment conditions.

Enable: At “ON” condition (FPBACK=Hi), enable the inverter.

Disable: At “OFF” condition (FPBACK=Lo), disable the inverter.

At the inverter “OFF” condition, input quiescent should be less than 0.1mA.

The inverter start-up output voltage will be above “Vopen” for “Ts” minimum at any condition under specify

until lamp to be ignited. The inverter should be shutdown if lamp ignition was failed in “Ts” maximum. The

inverter shall be capable of withstanding the output connections open without component over-stress / fire /

Vin=7.5V, SMB_DAT=FFH

(RES LOAD=100K ohm)
Vin=14.4V,
SMB_DAT=00H - 130 200 uS
Vin=14.4V,
SMB_DAT=FFH - - 0.1 Sec

80 - - %

smoke /arc.

zBurst mode frequency

The burst mode frequency should be in specification in any environment condition and electrical condition.

zBrightness control

SM-BUS values for panel luminance are to be included in the on LCD board EEDID ROM chip table. The

supplier will measure panel luminance in a system and define the SMBUS values for each of the 8 required

luminance levels. The panel luminance, for which SMBUS values will be provided in the EEDID from byte #

113(hex #71), to byte # 120, (hex # 78), is show in the table below. The inverter supplier should provide

these appropriate values to CMO.

Step Count Step 1 Step 2 Step3 Step 4 Step 5 Step 6 Step 7 Step 8

Address Byte

SM-Bus Data Value

(Hex)

Luminance (nits) 10 17 24 30 60 100 140 180

Byte

113

2B 3D 46 4F 72 8E AF D6

114

Byte

115

Byte

116

Byte

117

Byte

118

Byte

119

Byte

120

z Output ripple ratio

Ripple ratio = 2 * (Ipeak - Ivalley) / (Ipeak + Ivalley) * 100%

The Ripple ratio should be less than 5% and ripple frequency should be less than 200 Hz.

z Power up Overshoot & Undershoot

Overshoot & Undershoot at power up should not exceed the following limits.

Vin Output current Io (dI) Settling time

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0ШVin(min.)

0ШVin(typ.)

0ШVin(max.)

dI=Imax.-Io or dI=(Io-Imin.)/Io

z Output connections short protection

The inverter shall be capable of withstanding the output connections short without damage or over-stress.

And the inverter maximum input power shall be limited within 1W.

6.4.3 Other Information

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Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Io(rms) Overshoot/Undershoot (dT)

Io(max.)

Io(min.)

Io(max.)

Io(min.)

Io(max.)

Io(min.)

150% / 50% 5 ms max.

150% / 50% 5 ms max.

150% / 50% 5 ms max.

DOC No.: 14067654

Approval

z Safety

x The inverter shall meet the requirement of “Limited current circuits” in paragraphs 2.4.1 in IEC60950.

There is no fire/smoke while simulating the component of the inverter open/short test.

x The Inverter AND panel must be UL certified with CB certificate and LCC (Limited Current Circuit) test

and test reports from UL. Inverter panel combo must pass Dell Safety requirements.

z EMI

The inverter must meet the radiated limitation requirement of CISPR22 class B, FCC-B and VCCI level II

with 6dB margin minimum while the inverter operating in the complete system.

z Environment Regulation

x Follow the RoHS requirement.

x Fill in CMO’s official document <<Environmentally Conscious Products Questionnaire for Suppliers of

Materials, Parts, and Products>> and turn in to CMO before CMO’s specification approval process.

z Dell’s other requirements

1. The inverter must not emit any audible noise.

2. Please refer to CMO’s official document. “General Inverter Specification for LCD Module” for other

general information such as reliability test, safety and etc..

3. Please also refer to DELL’s official document about inverter:

z LCD Backlight Design Spec X00-04

z DELL’s LCD Inverter Qualification Plan, Rev. A00

z Prohibited Components
z “Holy Stone(كعഘ)”’s products are prohibited.

Confidential Notice

Remind that all the information described in this document is confidential. Please don’t reveal to other people else

before getting CMO’s agreement.

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7 INTERFACE TIMING

7.1 INPUT SIGNAL TIMING SPECIFICATIONS

The input signal timing specifications are shown as the following table and timing diagram.

Signal Item Symbol Min. Typ. Max. Unit Note

DCLK Frequency 1/Tc - 71 73 MHz -

Vertical Total Time TV 802 823 840 TH -

DE

Vertical Addressing Time TVD 800 800 800 TH -

Horizontal Total Time TH 1380 1440 1450 Tc -

Horizontal Addressing Time THD 1280 1280 1280 Tc -

INPUT SIGNAL TIMING DIAGRAM

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DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

DE

DCLK

TC

DE

DATA

7.2 POWER ON/OFF SEQUENCE

Power On

90%

Power Supply

for LCD, Vcc

- Interface Signal

(LVDS Signal of
Transmitter), V

- Power for Lamp

0V

0V

I

10%

t1

HD

T

Restart

t7

10%

10%

t4

Valid Data

ONOFF OFF

Power Off

90%

t3 t2

t6 t5

50%50%

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Timing Specifications:

0.5ms <t1Љ10 msec

0 < t2 Љ 50 msec

0 < t3 Љ 50 msec

t4 Њ 500 msec

t5 Њ 200 msec

t6 Њ 200 msec

Note (1) Please avoid floating state of interface signal at invalid period.

Note (2) When the interface signal is invalid, be sure to pull down the power supply of LCD Vcc to 0 V.

Note (3) The Backlight inverter power must be turned on after the power supply for the logic and the

interface signal is valid. The Backlight inverter power must be turned off before the power supply

for the logic and the interface signal is invalid.

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DOC No.: 14067654

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Model No.: N121I3 -L04

Approval

Note (4) Sometimes some slight noise shows when LCD is turned off (even backlight is already off). To

avoid this phenomenon, we suggest that the Vcc falling time had better to follow

t7 Њ 5 msec

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8 OPTICAL CHARACTERISTICS

8.1 TEST CONDITIONS

Item Symbol Value Unit
Ambient Temperature Ta
Ambient Humidity Ha
Supply Voltage VCC 3.3 V
Input Signal According to typical value in "3. ELECTRICAL CHARACTERISTICS"
Inverter Current IL 6.0 mA
Inverter Driving Frequency FL 61 KHz
Inverter Sumida-H05-4915

The measurement methods of optical characteristics are shown in Section 8.2. The following items

should be measured under the test conditions described in Section 8.1 and stable environment shown in

Note (6).

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25r2

50r10

DOC No.: 14067654

Issued Date: Jul. 31, 2006

Model No.: N121I3 -L04

Approval

o

C

%RH

8.2 OPTICAL SPECIFICATIONS

Item Symbol Condition Min. Typ. Max. Unit Note

Contrast Ratio CR 300 500 - - (2), (5)

Response Time

Average Luminance of White L5p 150 180 - cd/m2(4), (5)

Luminance Non-Uniformity

Color Gamut C.G 42 45 - % (5), (7)

Red

Color
Chromaticity

Green

Blue

White

Horizontal

Viewing Angle

Vertical

TR - 5 10 ms

- 11 16 ms

T

F

GW5p

GW

13p

Rx
Ry
Gx
Gy
Bx
By

T

Viewing Normal

=0q, TY =0q

x

Angle

- - 20 %

- - 35 %

0.590

0.340

0.319

TYP

-0.02

0.541

0.152

TYP

+0.02

0.125

Wx 0.315 -

Wy

Tx+

T

x

TY+
T

Y

­CRt10

-

0.330

40 45 ­40 45 ­15 20 ­40 45 -

Deg.

(3)

(5), (6)

-

-

-

-

-

­(1), (5)

-

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Note (1) Definition of Viewing Angle (Tx, Ty):

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DOC No.: 14067654

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Model No.: N121I3 -L04

Approval

TX- = 90º

x-

6 o’clock

T

y- = 90º

y-

Note (2) Definition of Contrast Ratio (CR):

The contrast ratio can be calculated by the following expression.

Normal

Tx = Ty = 0º

Ty- Ty

Tx-

Tx+

y+

12 o’clock direction

T

y+ = 90º

x+

TX+ = 90º

Contrast Ratio (CR) = L63 / L0

L63: Luminance of gray level 63

L 0: Luminance of gray level 0

CR = CR (5)

CR (X) is corresponding to the Contrast Ratio of the point X at Figure in Note (6).

Note (3) Definition of Response Time (T

100%

90%

Optical

Response

Gray Level 63

10%

0%

R

T

R

, TF):

Gray Level 0

Gray Level 63

Time

T

F

66.67ms

66.67m

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Note (4) Definition of Average Luminance of White (L

Measure the luminance of gray level 63 at 5 points

L

= [L (10)+ L (11)+ L (12)+ L (13)+ L (5)] / 5

AVE

L (x) is corresponding to the luminance of the point X at Figure in Note (6).

Note (5) Measurement Setup:

The LCD module should be stabilized at given temperature for 20 minutes to avoid abrupt

temperature change during measuring. In order to stabilize the luminance, the measurement

should be executed after lighting Backlight for 20 minutes in a windless room.

LCD Module

LCD Panel

Center of the Screen

):

AVE

Field of View = 2º

CA210

CS-1000T

500 mm

Light Shield Room

(Ambient Luminance < 2 lux)

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Note (6) Definition of White Variation (GW5p, GW

Measure the luminance of gray level 63 at 5, 13 points

GW

={1-{ Minimum [L (5)+ L (10)+ L (11)+ L (12)+ L (13)] / Maximum [L (5)+ L (10)+ L (11)+ L (12)+

5p

L (13)]}} *100%

GW

={1-{ Minimum [L (1) ~ L (13)] / Maximum [L (1) ~ L (13)]}} *100%

13p

]

13p

):

X

: Test Point

X=1 to 13

Note (7) Definition of color gamut (C.G):

C.G= ΓR G B /ΓR

R

R, G, B

'R

, G0, B0 : color coordinates of red, green, and blue defined by NTSC, respectively.

0

: color coordinates of module on 63 gray levels of red, green, and blue, respectively.

0 G0 B0

0 G0 B0

: area of triangle defined by R0, G0, B

,*100%

Γ 'R G B: area of triangle defined by R, G, B

˖˜˘ ʳ˄ˌ ˆ˄

˃ˁˌ

˃ˁˋ

˃ˁˊ

˃ˁˉ

˃ˁˈ

˃ˁˇ

˃ˁˆ

˃ˁ˅

˃ˁ˄

˃

˃ ˃ˁ˅ ˃ˁˇ ˃ˁˉ ˃ˁˋ

G

0

G

B

B

0

Active Area

0

R

0

R

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9 PRECAUTIONS

9.1 HANDLING PRECAUTIONS

(1) The module should be assembled into the system firmly by using every mounting hole. Be careful not

to twist or bend the module.

(2) While assembling or installing modules, it can only be in the clean area. The dust and oil may cause

electrical short or damage the polarizer.

(3) Use fingerstalls or soft gloves in order to keep display clean during the incoming inspection and

assembly process.

(4) Do not press or scratch the surface harder than a HB pencil lead on the panel because the polarizer is

very soft and easily scratched.

(5) If the surface of the polarizer is dirty, please clean it by some absorbent cotton or soft cloth. Do not use

Ketone type materials (ex. Acetone), Ethyl alcohol, Toluene, Ethyl acid or Methyl chloride. It might

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permanently damage the polarizer due to chemical reaction.

(6) Wipe off water droplets or oil immediately. Staining and discoloration may occur if they left on panel for

a long time.

(7) If the liquid crystal material leaks from the panel, it should be kept away from the eyes or mouth. In

case of contacting with hands, legs or clothes, it must be washed away thoroughly with soap.

(8) Protect the module from static electricity, it may cause damage to the C-MOS Gate Array IC.

(9) Do not disassemble the module.

(10) Do not pull or fold the lamp wire.

(11) Pins of I/F connector should not be touched directly with bare hands.

9.2 STORAGE PRECAUTIONS

(1) High temperature or humidity may reduce the performance of module. Please store LCD module within

the specified storage conditions.

(2) It is dangerous that moisture come into or contacted the LCD module, because the moisture may

damage LCD module when it is operating.

(3) It may reduce the display quality if the ambient temperature is lower than 10 ºC. For example, the

response time will become slowly, and the starting voltage of lamp will be higher than the room

temperature.

9.3 OPERATION PRECAUTIONS

(1) Do not pull the I/F connector in or out while the module is operating.

(2) Always follow the correct power on/off sequence when LCD module is connecting and operating. This

can prevent the CMOS LSI chips from damage during latch-up.

(3) The startup voltage of Backlight is approximately 1000 Volts. It may cause electrical shock while

assembling with inverter. Do not disassemble the module or insert anything into the Backlight unit.

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10 PACKING

10.1 CARTON

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10.2 PALLET

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11 DEFINITION OF LABELS

11.1 MODULE LABEL

The barcode nameplate is pasted on each module as illustration, and its definitions are as following

explanation.

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N121I3 -L04

N141X5 - L03 Rev.XX

01A

X X X X X X X Y M D L N N N N

C P 1 3 5 4 4 8 - 0 1

(a) Model Name: N121I3 - L04

(b) Revision: Rev. XX, for example: C1, C2 …etc.

(c) Serial ID: X X

X X X X X Y M D L N N N N

E207943

MADE IN TAIWAN

Serial No.

Product Line

Year, Month, Date

CMO Internal Use

Revision

CMO Internal Use

Serial ID includes the information as below:

(a) Manufactured Date: Year: 1~9, for 2001~2009

Month: 1~9, A~C, for Jan. ~ Dec.

Day: 1~9, A~Y, for 1

(b) Revision Code: cover all the change

(c) Serial No.: Manufacturing sequence of product

st

to 31st, exclude I , O and U

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Dell PPID label contains information as below:

(a) Serial ID: TW-0SSSSS-70896-YMD-XXXX

(b) Production location: Made in XXXX.

(d) Revision code: X00, X10, X20, A00..etc.

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Serial Numbers

Production Year, Month, Date
Manufacturing ID

Part Number

11.2 CARTON LABEL

(a) Production location: Made In XXXX. XXXX stands for production location.

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11.3 CUSTOMER CARTON LABEL

PKG ID (3S)124161241729112345609886C20

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REV.A06

DP/N 03J849

BOX Qty 20 Made in Taiwan

Vendor ID Loc Id

12416 12416

Mfg Id
70896

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