CML Microcircuits CMX7143 Fl Series, CMX7143FI-2.1.2.0, CMX7143FI-1.0.4.0, CMX7143FI-3.0.3.0 Configuration Manual

CML Microcircuits

Application Note

CMX7143_FI-x

COMMUNICATION SEMICONDUCTORS

Publication: AN/WData/7143/Config/5 November 2009

Configuration Guide

1 Introduction

This document is intended to identify and illustrate the associated routing through the CMX7143 when
using the 4FSK, GMSK and FFSK Function Images
registers will also be shown to provide easier understanding and control of the device.

Specific to Function Image
Images

This Configuration Guide is not intended to cover all of the hardware, functions or possible set-up modes.
It is a virtual representation of the device and is provided for illustrative purposes to simplify and aid
product development.

Default settings are given in red and control paths are shown in blue. The Configuration Guide is best
printed on an A3 colour printer.

TM

:

• 7143FI-1.0.4.0

• 7143FI-2.1.2.0

• 7143FI-3.0.3.0

TM

7143FI-1, 7143FI-2 and 7143FI-3, this Configuration Guide covers Function

TM

. In addition references to the C-BUS accessible

2 History

Version Changes Date

1.0 New Issue 8-1-09

2.0 Correction to illustrations, $CD Fine Gain Descriptions Corrected 13-1-09

3.0 Addition of SoftBit Rx mode (FI-2.x). Images split into 3 separate illustrations 12-3-09

4.0 Further correction to Mod1 $CD Fine Gain Description 2-6-09

5.0 Addition of Mod Fine Gain and additions to $C1 (FI-2) 24-11-09

© 2009 CML Microsystems Plc

1 of 5

Application Note CMX7143_FI-x Configuration Guide

CMX7143_FI1 GMSK /GFSK M ulti-mode Packet-data Modem

CH3 /

RSSI3

CH2 /

RSSI2

VBIAS

$C0

b14=0 Powersaved

b14=1 Enabled

VBIAS

RSSI Signal

00

01
10
11

$B1 b3,2

Routing

RSSI Gain
$B1, b15-13

000=0dB

001=3.2dB
010=6.4dB
011=9.6dB
100=12.8dB
101=16dB
110=19.2dB
111=22.4dB

RSSI Enable
$C0, b2

0=Disabled

1=Enabled

RSSI Fine
Input Gain
P 4.1
0-> -3.5dB
Default:

$8000 =0dB

Transmit Mode
$C1, b1-0 = 10

Tx Data Buffer

Formatted Data

Carrier Sense Mode

$C1, b1-0 = 11

4

2

Data M odulator

Raw Data

Channel Encoding

RSSI

Detection

AFSD

GMSK/

GFSK

Modulator

Carrier
Sense

Frame

Sync

OR

GMSK/GFSK

Filter

False for

CS period

True

Tx

Modulator

Mode

Tx Mode

Test

Mode

Mod1 S ig nal Enab le
$C0, b11

0=Disabled

1=Enabled

VBIAS

MOD1 Source
$B1, b9

0

1

MOD1 Enable
$C0, b9

0=Disabled

1=Enabled

MOD1 Coarse Attenuation
$CD, b13-11 (dB)

100=6

000=>40

101=4

001=12

110=2

010=10

111=0

011=8

MOD1 Fine Attenuation
$CD, b10-7 (dB)

0000=0

0001=0.2
0010=0.4
0011=0.6
0100=0.8
0101=1.0
0110=1.2
0111=1.4
1000=1.6
1001=1.8

See

6.2

CH1 /

RSSI1

VBIAS

VBIAS

$C0

b15=0 Powersaved

b15=1 Enabled

$C0

b13=0 Powersaved

b13=1 Enabled

VBIAS

00

01
10
11

Rx Signal

Signal

Routing

$B1 b5,4

Rx Signal Gain
$B1, b12-10

000=0dB

001=3.2dB
010=6.4dB
011=9.6dB
100=12.8dB
101=16dB
110=19.2dB
111=22.4dB

Rx Signal
Enable
$C0, b12

0=Disabled

1=Enabled

Rx Signal
Fine Input
Gain
P 4.0
0-> -3.5dB
Default:

$8000 = 0dB

Receive Mode

$C1, b1-0 = 01

$C1, b1-0 = 00

Modem Mode and Control Register $C1

Levels tracking behaviour
$C1, b15-14

00 = Locked: no tracking

01 = Track levels on, slow response
10 = Track levels on, fast response
11 = Auto-tracking response
dynamically selected .

Symbol timing PLL behaviour
$C1, b13-12

00 = Locked: no tracking

01 = Narrow PLL
10 = Medium PLL
11 = Auto-PLL bandwidth
dynamically selected

3

Data Demodulator

GMSK/GFSK

Filter

Idle Mode

RSSI

Detection

VBIAS

MOD2
Source
$B1, b7

0

See

6.1

GPIO1
GPIO2
GPIO3

GPIO4

1

MOD2 Enable
$C0, b8

0=Disabled

1=Enabled

MOD2 Course
Attenuation
$CD, b6-4 (dB)

100=6

000=>40

101=4

001=12

110=2

010=10

111=0

011=8
MOD2 Fine Attenuation

$CD, b3-0 (dB)

0000=0

0001=0.2
0010=0.4
0011=0.6
0100=0.8
0101=1.0
0110=1.2
0111=1.4
1000=1.6
1001=1.8

See

6.2

Rx Eye

AFSD

GMSK/GFSK
Demodulator

Formatted

Data

1

Channel

Decoding

Raw Data

Rx Data B u ffer

Mod2 Enable
$C0, b10

0=Disabled

1=Enabled

5

Internal

Bias

Block

VBIAS

GPIO

b0
b1
b2

BIAS Enable

$C0, b6

0=Disabled

1=Enabled

b3

GPIO Sw itche s

$CD, b15-14 and b3-0

0=Disabled

1=Enabled

1

Programming Register $C8

Burst Data Configuration

$C8, Block 0
P0.0 - P0.10

6.0

Burst Tx Sequence + GPIO Configuration

$C8, Block 1
P1.0 – P 1 .1 3

6.1

6.2

Gain and Offset Setup

$C8, Block 4
P4.0 – P4.10

Tx Bytewise Formatted Data Transmit

1514131211109876543210

bit
$B5 TxData0
$B6 TxData1
$B7 TxData2
$CA TxData3
$CB TxData4
$C2 TxData5
$C7 TxData6

Rx Bytewise Formatted Data Rece ive

$B8 RxData0
$B9 RxData1
$BA RxData2
$BB RxData3
$C5 RxData4
$C9 RxData5
$CC RxData6

TxData_Byte 0
Tx

Data_Byte 1

TxData

_Byte 3
Data_Byte 5
Data_Byte 7
Data_Byte 9

Data_Byte 11

bit

1514131211109876543210

RxData_Byte 0

Data_Byte 1
Data_Byte 3

RxData_Byte 5

Data_Byte 9

RxData_Byte 11

© 2009 CML Microsys

Block Specif ier (Note 1)

Trans Count

TxData_Byte 2
TxData_Byte 4
TxData_Byte 6Tx

Data_Byte 8Tx

Tx
TxData_Byte 10Tx
Tx

Data_Byte 12Tx

Block Specif ier (Note 1)

CRC

Trans Count

RxData_Byte 2Rx

RxData_Byte 4Rx

Rx

Data

_Byte 6

RxData_Byte 8RxData_Byte 7
RxData_Byte 10Rx
RxData_Byte 12

tems Plc

Tx/Rx Data R eg isters

Tx Bytewise Raw Data Transmit

bit

1514131211109876543210
$B5 TxData0 1
$B6 TxData1
$B7 TxData2
$CA TxData3
$CB TxData4
$C2 TxData5
$C7 TxData6

Rx Bytewise Raw Data Receive

$B8 RxD ata0 1
$B9 RxD ata1
$BA RxData2
$BB RxData3
$C5 RxData4
$C9 RxData5
$CC RxData6

TxData

Data_Byte 1

Tx

TxData_Byte 5

Data_Byte 7
Data_Byte 9

Data_Byte 11

bit

1514131211109876543210

RxData_Byte 0
RxData_Byte 1 R
RxData_Byte 3 R
RxData_Byte 5 R
RxData_Byte 7 RxData_Byte 8
RxData_Byte 9 R

RxData_Byte 11 R

Trans Count

_Byte 0 Byte Counter

Trans Count

TxData

_Byte 2
TxData_Byte 4TxData_Byte 3
TxData_Byte 6
Tx

Data_Byte 8Tx
TxData_Byte 10Tx
Tx

Data_Byte 12Tx

B

yte Counter
xData_Byte 2
xData_Byte 4
xData_Byte 6

xData_Byte 10
xData_Byte 12

Tx Bitwise Raw Data Transmit

bit
$B5 TxData0 b0 b1 b2 b3 b4 b5 b6 b7 0
$B6 TxData1 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23
$B7 TxData2 b24 b25 b26 b27 b28 b29 b30 b31

Rx Bitwise Raw Data Receive

$B8 RxData0 b0 b1 b2 b3 b4 b5 b6 b7 0
$B9 RxData1 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23
$BA RxData2 b24 b25 b26 b27 b28 b29 b30 b31

Note 1: CMX7143 – FI1.
When transmitting two part data blocks part 1, then part 2 must be loaded in
consecutive transactions before any data is sent. This is necessary due to
interleaving.

1514131211109876543210

bit

1514131211109876543210

Trans Count

Trans Count

Bit Counter

Bit Counter

5

Modem Mode an d C ontrol Register $C1

Tx Modem and CS Modem Control
$C1, b7-4

0000 = Idle

0001 = Reserved
0010 = Tx Raw Data Only
0011 = Tx PRBS
0100 = Tx Preamble, Sync1, Raw Data
0101 = Tx Preamble, Sync2, Raw Data
0110 = Test – Deviation
0111 = Reset / Abort
1000 = Test – Preamble
1001 = Reserved
1010 = Tx Preamble, Sync1, Formatted Data
1011 = Tx Preamble, Sync2, Formatted Data

2 of 5

Rx Modem Control

2 3 4

$C1, b11-8

0000 = Idle

0001 = Reserved
0010 = Rx search for Syn c1 or 2, then Rx Raw Data
0011 = Rx eye
0100 = Rx search for Syn c1, then Rx R aw Data
0101 = Rx search for Syn c2, then Rx R aw Data
0110 = Reserved
0111 = Reset / Abort
1000 = Reserved
1001 = Rx s earch for Sync 1 and 2, then Rx Forma tte d Data
1010 = Rx s earch for Sync 1, then Rx Formatted Data
1011 = Rx s earch for Sync 2, then Rx Formatted Data

CS Modem Control
$C1, b7-4

0000 = Idle

0001 = Reserved
0010 = Tx Raw Data Only
0011 = Tx PRBS
0100 = Tx Preamble, Sync1, Raw Data
0101 = Tx Preamble, Sync2, Raw Data
0110 = Test – Deviation
0111 = Reset / Abort
1000 = Test – Preamble
1001 = Reserved
1010 = Tx Preamble, Sync1, Formatted Data
1011 = Tx Preamble, Sync2, Formatted Data

AN/WData/7143/Config/5 November 2009

Application Note CMX7143_FI-x Configuration Guide

CM X7143_FI2 4-Level FSK P acket-data M odem

CH3 /

RSSI3

CH2 /

RSSI2

CH1 /

RSSI1

VBIAS

VBIAS

VBIAS

$C0

b14=0 Powersaved

b14=1 Enabled

$C0

b15=0 Powersaved

b15=1 Enabled

$C0

b13=0 Powersaved

b13=1 Enabled

VBIAS

VBIAS

RSSI Signal

00

01
10
11

$B1 b3,2

Rx Signal

00

01
10
11

$B1 b5,4

Routing

Signal

Routing

RSSI Gain
$B1, b15-13

000=0dB

001=3.2dB
010=6.4dB
011=9.6dB
100=12.8dB
101=16dB
110=19.2dB
111=22.4dB

RSSI Enable
$C0, b2

0=Disabled

1=Enabled

Rx Signal Gain
$B1, b12-10

000=0dB

001=3.2dB
010=6.4dB
011=9.6dB
100=12.8dB
101=16dB
110=19.2dB
111=22.4dB

Rx Signal
Enable
$C0, b12

0=Disabled

1=Enabled

RSSI Fine
Input Gain
P 4.1
0-> -3.5dB
Default:

$8000 =0dB

Rx Signal
Fine In put
Gain
P 4.0
0-> -3.5dB
Default:

$8000 = 0dB

Transmit M ode
$C1, b1-0 = 10

2

Data Modulator

Raw Data

Tx D a ta Buffer

Formatted Data

Carrie r S e n s e M o d e

$C1, b1-0 = 11

Channel Encoding

RSSI

Detection

4

AFSD

Receive Mode

$C1, b1-0 = 01

3

Data Demodulator

RRC
Filter

Idle M o de

$C1, b1-0 = 00

Modem M ode and Control Register $C1

Levels tracking behaviour
$C1, b15-14

00 = Locked: no tracking

01 = Track levels on, slow response
10 = Track levels on, fast respo n se
11 = Auto-tracking response
dynamically selected.

RSSI

Detection

Rx Eye

AFSD

4FSK

Demodulator

Symbol timing PLL behaviour
$C1, b13-12

00 = Locked: no tracking

01 = Narrow PLL
10 = Medium PLL
11 = Auto-PLL bandwidth
dynamically selected

Formatted

Data

1

4FSK

Modulator

Carrier

Sense

Frame

Raw Data

1

Sync

Channel

Decoding

RRC
Filter

False fo r

CS period

OR

True

Rx Data Buffer

5

Programming Register $C8

Burst Data Configuration

$C8, Block 0
P0.0 - P 0 .1 0

Tx

Modulator

Mode

6.0

Tx Mode

Test

Mode

Intern al

Bias

Block

BIAS Enable

$C0, b6

0=Disabled

1=Enabled

VBIAS

Burst Tx Sequence + GPIO

Configuration

$C8, Block 1
P1.0 – P 1 .13

Mod1 Signal Enable
$C0, b11

0=Disabled

1=Enabled

Mod2 Enable
$C0, b10

0=Disabled

1=Enabled

GPIO

GP IO Switches

$CD, b15-14 and b3-0

0=Disabled

1=Enabled

b0
b1
b2
b3

VBIAS

MOD1 Source
$B1, b9

VBIAS

See

6.1

6.1

GPIO1
GPIO2
GPIO3

GPIO4

MOD1 Enable
$C0, b9

0=Disabled

1=Enabled

0

1

MOD2
Source
$B1, b7

0

1

MOD2 Enable
$C0, b8

0=Disabled

1=Enabled

Gain and Offset Setup

$C8, Block 4
P4.0 – P 4 .10

MOD1 Coarse Attenuation
$CD, b13-11 (dB)

100=6

000=>40

101=4

001=12

110=2

010=10

111=0

011=8

MOD1 Fine Attenuation
$CD , b1 0-7 (d B )

0000=0

0001=0.2
0010=0.4
0011=0.6
0100=0.8
0101=1.0
0110=1.2
0111=1.4
1000=1.6
1001=1.8

MOD2 Course
Attenuation
$CD, b6-4 (dB)

000=>40

001=12
010=10
011=8

MOD2 Fine Attenuation
$CD, b3-0 (dB)

0000=0

0001=0.2
0010=0.4
0011=0.6
0100=0.8
0101=1.0
0110=1.2
0111=1.4
1000=1.6
1001=1.8

100=6
101=4
110=2
111=0

See

6.2

See

6.2

6.2

Tx Byte wise For matted Data Transmit

15141312111098765432 1 0

bit
$B5 TxData0
$B6 TxData1
$B7 TxData2
$CA TxData3
$CB TxData4
$C2 TxData5
$C7 TxData6

Rx Bytewise Formatted Data Receive

$B8 RxData0
$B9 RxData1
$BA RxData2
$BB RxData3
$C5 RxData4
$C9 RxData5
$CC RxData6

TxData_Byte 0

Data_Byte 1

Tx
TxData

Data_Byte 5
Data_Byte 7
Data_Byte 9

Data_Byte 11

bit

15141312111098765432 1 0

RxData_Byte 0

Data_Byte 1
Data_Byte 3

RxData_Byte 5

Data_Byte 9

RxData_Byte 11

© 2009 CML Microsys

Modem M ode and Control Register $C1

Tx Modem and CS M odem C ontrol
$C1, b7-4

0000 = Idle

0001 = Reserved
0010 = Tx Raw Data Only
0011 = Tx PRBS
0100 = Tx Preamble, Sync1, Raw D ata
0101 = Tx Preamble, Sync2, Raw D ata
0110 = Test – Deviation
0111 = Reset / Abort
1000 = Test – Preamble
1001 = Reserved
1010 = Tx Preamble, Sync1, Formatted Data
1011 = Tx Preamble, Sync2, Formatted Data
1100 = Tx Formatted Data Only

Rx Modem Control

2

$C1, b11-8

0000 = Idle

0001 = Reserved
0010 = Rx search for Sync1 or 2, then Rx Raw Data
0011 = Rx eye
0100 = Rx search for Sync1, then Rx Raw Data
0101 = Rx search for Sync2, then Rx Raw Data
0110 = Reserved
0111 = Reset / Abort
1000 = Reserved
1001 = Rx search for Sync1 and 2, then Rx Formatted Data
1010 = Rx search for Sync1, then Rx Formatted Data
1011 = Rx search for Sync2, then Rx Formatted Data

CS Modem Control

3 4

$C1, b7-4

0000 = Idle

0001 = Reserved
0010 = Tx Raw Data Only
0011 = Tx PRBS
0100 = Tx Prea mble, Sync 1 , Raw Data
0101 = Tx Prea mble, Sync 2 , Raw Data
0110 = Test – Deviation
0111 = Reset / Abort
1000 = Test – Preamble
1001 = Reserved
1010 = Tx Prea mble, Sync 1 , F ormatted Data
1011 = Tx Prea mble, Sync 2 , F ormatted Data
1100 = Tx Form atted Data Only

_Byte 3

Trans Count

Trans Count

Block Specifier (Not e 1)

TxData_Byte 2
TxData_Byte 4
TxData_Byte 6Tx

Data_Byte 8Tx

Tx
TxData_Byte 10Tx
Tx

Data_Byte 12Tx

CRC

Block Specifier (Not e 1)

RxData_Byte 2Rx

RxData_Byte 4Rx

Rx

Data_Byte 6

RxData_Byte 8RxData_Byte 7
RxData_Byte 10Rx

_Byte 12

RxData

Tx Bytewise Raw Data Transmit

1514131211109876543210

bit
$B5 TxData0 1
$B6 TxData1
$B7 TxData2
$CA TxData3
$CB TxData4
$C2 TxData5
$C7 TxData6

Rx Bytewise Raw Data Receive

$B8 RxData0 1
$B9 RxData1
$BA RxData2
$BB RxData3
$C5 RxData4
$C9 RxData5
$CC RxData6

TxData_Byte 0 Byte Counter
Tx

Data_Byte 1

TxData_Byte 5

Data_Byte 7
Data_Byte 9

Data_Byte 11

1514131211109876543210

bit

RxData_Byte 0
RxData
RxData_Byte 3 R
RxData_Byte 5 R
RxData_Byte 7 RxData_Byte 8
RxData
RxData_Byte 11 R

Trans Cou nt

Trans Cou nt

_Byte 1 R

_Byte 9 R

Tx/Rx Data Registers

Tx Bitwise R aw Data Transmit

TxData

_Byte 2
TxData_Byte 4TxData_Byte 3
TxData_Byte 6
Tx

Data_Byte 8Tx
TxData_Byte 10Tx
Tx

Data_Byte 12Tx

B

yte Counter
xData_Byte 2
xData_Byte 4
xData_Byte 6

xData_Byte 10
xData_Byte 12

$B5 TxData0 b0 b1 b2 b3 b4 b5 b6 b7 0
$B6 TxData1 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23
$B7 TxData2 b24 b25 b26 b27 b28 b29 b30 b31

Rx Soft Decision Raw Data Receive

$B8 RxData0 0
$B9 RxData1
$BA RxData2
$BB RxData3
$C5 RxD ata4
$C9 RxD ata5
$CC RxData6
Note:

bit

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

bi

t

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RxData_Bit 2

_Bit 6

Rx

Data

_Bit 10

Rx

Data

R

xData_Bit 14

RxData_Bit 18

_Bit 22

Data

Rx

Programming Register $C8, P4.1, SoftBitsOut bit = 1

Rx

Data
Data

Rx
Rx

Data

R

xData_Bit 15

Rx

Data_Bit 19
Data

Rx

_Bit 3
_Bit 7

_Bit 11

_Bit 23

Trans C ount

Trans C ount

Rx

Data
Data

Rx
RxData
R

xData_Bit 16

RxData_Bit 20

Data

Rx

_Bit 4
_Bit 8

_Bit 12

_Bit 24

Bit Counter

B

it CounterRxData_Bit 0 RxData_Bit 1
Rx

Data
Data

Rx

Rx

Data

Rx

Data_Bit 17
RxData
Rx

Data

Rx Bitwi se Raw Data Receive

1514131211109876543210

bit
$B8 RxData0 b0 b1 b2 b3 b4 b5 b6 b7 0
$B9 RxData1 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23
$BA RxData2 b24 b25 b26 b27 b28 b29 b30 b31

_Bit 5
_Bit 9

_Bit 13

_Bit 21
_Bit 25

Trans Co un t

5

Bit Counter

tems Plc 3 of 5 AN/WData/7143/Config/5 November 2009

Application Note CMX7143_FI-x Configuration Guide

CMX7143_FI3 FFSK/MSK Modem

CH3 /

RSSI3

CH2 /

RSSI2

VBIAS

$C0

b14=0 Powersaved

b14=1 Enabled

VBIAS

RSSI Signal

00

01
10
11

$B1 b3,2

Routing

RSSI Gain
$B1, b15-13

000=0dB

001=3.2dB
010=6.4dB
011=9.6dB
100=12.8dB
101=16dB
110=19.2dB
111=22.4dB

RSSI Enable
$C0, b2

0=Disabled

1=Enabled

RSSI Fine
Input Gain
P 4.1
0-> -3.5dB
Default:

$8000=0dB

Transmit Mode
$C1, b1-0 = 10

Tx Data Buffer

Formatted Data

Carrier Sense Mode

$C1, b1-0 = 11

4

2

Data Modulator

Raw Data

Channel Encoding

RSSI

Detection

Sync Detect

FFSK

Modulator

Carrier
Sense

Sync

Detect

OR

Optional

Pre-emphasis

Filter

False for

CS Period

True

Tx

Modulator

Mode

Tx Mode

Test

Mode

Mod1 Signal Enable
$C0, b11

0=Disabled

1=Enabled

VBIAS

MOD1 Source
$B1, b9

0

1

MOD1 Enable
$C0, b9

0=Disabled

1=Enabled

MOD1 Coarse Attenuation
$CD, b13-11 (dB)

100=6

000=>40

101=4

001=12

110=2

010=10

111=0

011=8

MOD1 Fine Attenuation
$CD, b10-7 (dB)

0000=0

0001=0.2
0010=0.4
0011=0.6
0100=0.8
0101=1.0
0110=1.2
0111=1.4
1000=1.6
1001=1.8

See

6.2

CH1 /

RSSI1

VBIAS

VBIAS

$C0

b15=0 Powersaved

b15=1 Enabled

$C0

b13=0 Powersaved

b13=1 Enabled

VBIAS

00

01
10
11

Rx Signal

Routing

$B1 b5,4

Signal

Rx Signal Gain
$B1, b12-10

000=0dB

001=3.2dB
010=6.4dB
011=9.6dB
100=12.8dB
101=16dB
110=19.2dB
111=22.4dB

Rx Signal
Enable
$C0, b12

0=Disabled

1=Enabled

Receive Mode

$C1, b1-0 = 01

3

Rx Signal
Fine Input
Gain
P 4.0
0-> -3.5dB
Default:

$8000=0dB

Modem Mode and Control Register $C1

Scrambler see d select
$C1, b15-12

0000 = $FFFF: Standard seed

0001 = Scramble seed 1 (See program block 0)
0010 = Scramble seed 2 (See program block 0)
0011 = $0000: Scrambler off

Data Demodulator

Receive

Filter

Idle Mode

$C1, b1-0 = 00

RSSI

Detection

VBIAS

MOD2
Source
$B1, b7

0

GPIO1
GPIO2
GPIO3

GPIO4

1

MOD2 Enable
$C0, b8

0=Disabled

1=Enabled

MOD2 Course
Attenuation
$CD, b6-4 (dB)

000=>40

001=12
010=10
011=8

MOD2 Fine Attenuation
$CD, b3-0 (dB)

0000=0

0001=0.2
0010=0.4
0011=0.6
0100=0.8
0101=1.0
0110=1.2
0111=1.4
1000=1.6
1001=1.8

6.26.16.0

100=6
101=4
110=2
111=0

See

6.1

Rx Eye

Mod2 Enable

VBIAS

$C0, b10

0=Disabled

1=Enabled

GPIO

b0
b1

Sync Detect

FFSK

Demodulator

1

Formatted

Data

Channel

Decoding

Raw Data

Rx Data B uffer

5

Internal

Bias

Block

b2

BIAS Enable

$C0, b6

0=Disabled

1=Enabled

1

Programming Register $C8

Burst Data Configuration

$C8, Block 0
P0.0 - P0.15

Burst Tx Sequence + GP IO Con figuration

$C8, Block 1
P1.0 – P1.13

b3

GPIO Switches

$CD, b15-14 & b3-0

0=Disabled

1=Enabled

Gain and Offset Setup

$C8, Block 4
P4.0 – P4.10

Tx Bytewise Formatted Data T ransmit

1514131211109876543 2 10

bit
$B5 TxData0
$B6 TxData1
$B7 TxData2

$CA TxData3
$CB TxData4

$C2 TxData5
$C7 TxData6

Rx Bytewise Formatted Data Re ceive

bit

1514131211109876543 2 10
$B8 RxData0
$B9 RxData1
$BA RxData2

$BB RxData3

$C5 RxData4
$C9 RxData5

$CC RxData6 RxData

© 2009 CML Microsys

Modem Mode and Control Register $C1

5

5

Tx Modem and CS Modem Control
$C1, b7-4

0000 = Idle

0001 = Reserved
0010 = Tx Raw Data Only
0011 = Tx PRBS
0100 = Tx Preamble, Sync1, Raw Data
0101 = Tx Preamble, Sync2+Raw Data
0110 = Test – Deviation
0111 = Reset / Abort
1000 = Test – Preamble
1001 = Tx Preamble, Sync3 + Raw Data
1010 = Tx Preamble, Sync1, Formatted Data
1011 = Tx Preamble, Sync2, Formatted Data
1100 = Tx Preamble, Sync3, Formatted Data

Rx Modem Control

2 3 4

$C1, b11-8

0000 = Idle

0001 = Reserved
0010 = Rx search for Sync and modulation as defined by P4.1,
then Rx Raw Data
0011 = Rx eye
0100 = Reserved
0101 = Reserved
0110 = Reserved
0111 = Reset / Abort
1000 = Reserved
1001 = Rx search for Sync and modulation as defined by P4.1,
then Rx Formatted Data

CS Modem Control
$C1, b7-4

0000 = Idle

0001 = Reserved
0010 = Tx Raw Data Only
0011 = Tx PRBS
0100 = Tx Preamble, Sync1, Raw Data
0101 = Tx Preamble, Sync2, Raw Data
0110 = Test – Deviation
0111 = Reset / Abort
1000 = Test – Preamble
1001 = Tx Preamble, Sync3 + Raw Data
1010 = Tx Preamble, Sync1, Formatted Data
1011 = Tx Preamble, Sync2, Formatted Data
1100 = Tx Preamble, Sync3, Formatted Data

TxData_Byte 0
TxData_Byte 1 TxData_Byte 2

_Byte 3 T

TxData

_Byte 5 T

TxData

_Byte 7 T

TxData
TxData_Byte 9 T

Data_Byte 11 T

Tx

RxData

_Byte 0
RxData_Byte 1 R
RxData_Byte 3 R
RxData

_Byte 5 R
R

xData_Byte 7 RxData_Byte 8

RxData

_Byte 9 R

_Byte 11 R

Trans Count

Trans Count

Block S

xData_Byte 4
xData_Byte 6

xData_Byte 8
xData_Byte 10
xData_Byte 12

Block S
xData_Byte 2
xData_Byte 4
xData_Byte 6

xData_Byte 10
xData_Byte 12

Tx/Rx Da ta R e g is te rs

Tx Byt ewise Raw Data Transmit

bit

1514131211109876543210

$B5 TxData0 1

pecifier

$B6 TxData1
$B7 TxData2
$CA TxData3
$CB TxData4
$C2 TxData5
$C7 TxData6 TxData

Rx Bytewise Raw Data Receive

1514131211109876543210

pecifier

bit
$B8 RxData0 1
$B9 RxData1
$BA RxData2
$BB RxData3
$C5 RxData4
$C9 RxData5
$CC RxData6

RxData

TxData
TxData_Byte 1 TxData_Byte 2
TxData
TxData
TxData_Byte 7 T
TxData

RxData
RxData
RxData
RxData_Byte 5 RxData_Byte 6
RxData_Byte 7 RxData_Byte 8
RxData_Byte 9 R

Trans Count Byte Counter

_Byte 0

_Byte 3 T
_Byte 5 T

_Byte 9 T

_Byte 11 T

Trans Count Byte Counter

_Byte 0
_Byte 1 R
_Byte 3 R

_Byte 11 Rx

xData_Byte 4
xData_Byte 6

xData_Byte 8
xData_Byte 10
xData_Byte 12

xData_Byte 2

xData_Byte 4

xData_Byte 10

Data_Byte 12

Tx Bitwise Raw Data Transmit

1514131211109876543210

bit
$B5 TxData0 b0 b1 b2 b3 b4 b5 b6 b7 0
$B6 TxData1 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23
$B7 TxData2 b24 b25 b26 b27 b28 b29 b30 b31

Rx Bitwise Raw Data Receive

1514131211109876543210

bit
$B8 RxData0 b0 b1 b2 b3 b4 b5 b6 b7 0
$B9 RxData1 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23
$BA RxData2 b24 b25 b26 b27 b28 b29 b30 b31

Trans Count

Trans Count

Bit Counter

Bit Counter

tems Plc 4 of 5 AN/WData/7143/Config/5 November 2009

CML does not assume any responsibility for the use of any algorithms, methods or circuitry

described. No IPR or circuit patent licenses are implied. CML reserves the right at any time without

notice to change the said algorithms, methods and circuitry and this product specification. CML has

a policy of testing every product shipped using calibrated test equipment to ensure compliance with

this product specification. Specific testing of all circuit parameters is not necessarily performed.