Climax Technology Co ZBH SA Users manual

The 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core.

It has three different memory-access buses (SFR, DATA and CODE/XDATA) with single-cycle access

to SFR, DATA, and the main SRAM.

It also includes a debug interface and an 18-input extended interrupt unit.

The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each

of which is associated with one of four interrupt priorities.

Any interrupt service request is serviced also when the device is in idle mode by going back to active

mode.

Some interrupts can also wake up the device from sleep mode (power modes 1–3).

The memory arbiter is at the heart of the system, as it connects the CPU and DMA controller with the

physical memories and all peripherals through the SFR bus.

The memory arbiter has four memory access points, access of which can map to one of three physical

memories: an 8-KB SRAM, flash memory, and XREG/SFR registers.

It is responsible for performing arbitration and sequencing between simultaneous memory accesses to

the same physical memory.

The 8-KB SRAM maps to the DATA memory space and to parts of the XDATA memory spaces.

The 8-KB SRAM is an ultralow-power SRAM that retains its contents even when the digital part is

powered off (power modes 2 and 3).

This is an important feature for low-power applications.

The 32/64/128/256 KB flash block provides in-circuit programmable non-volatile program memory for

the device, and maps into the CODE and XDATA memory spaces.

In addition to holding program code and constants, the non-volatile memory allows the application to

save data that must be preserved such that it is available after restarting the device.

Using this feature one can, e.g., use saved network-specific data to avoid the need for a full start-up

and network find-and-join process .

The digital core and peripherals are powered by a 1.8-V low-dropout voltage regulator. It provides

power management functionality that enables low power operation for long battery life using different

power modes.

Five different reset sources exist to reset the device.

The CC2530 includes many different peripherals that allow the application designer to develop

advanced applications.

The debug interface implements a proprietary two-wire serial interface that is used for in-circuit

debugging.

Through this debug interface, it is possible to perform an erasure of the entire flash memory, control

which oscillators are enabled, stop and start execution of the user program, execute supplied

instructions on the 8051 core, set code breakpoints, and single-step through instructions in the code.

Using these techniques, it is possible to perform in-circuit debugging and external flash programming

elegantly.

The device contains flash memory for storage of program code.

The flash memory is programmable from the user software and through the debug interface.

The flash controller handles writing and erasing the embedded flash memory.

The flash controller allows page-wise erasure and 4-bytewise programming.

The I/O controller is responsible for all general-purpose I/O pins.

The CPU can configure whether peripheral modules control certain pins or whether they are under

software control, and if so, whether each pin is configured as an input or output and if a pullup or

pulldown resistor in the pad is connected. CPU interrupts can be enabled on each pin individually.

Each peripheral that connects to the I/O pins can choose between two different I/O pin locations to

ensure flexibility in various applications.

A versatile five-channel DMA controller is available in the system, accesses memory using the

XDATA memory space, and thus has access to all physical memories.

Each channel (trigger, priority, transfer mode, addressing mode, source and destination pointers, and

transfer count) is configured with DMA descriptors anywhere in memory.

Many of the hardware peripherals (AES core, flash controller, USARTs, timers, ADC interface) achieve

highly efficient operation by using the DMA controller for data transfers between SFR or XREG

addresses and flash/SRAM.

Timer 1 is a 16-bit timer with timer/counter/PWM functionality.

It has a programmable prescaler, a 16-bit period value, and five individually programmable

counter/capture channels, each with a 16-bit compare value.

Each of the counter/capture channels can be used as a PWM output or to capture the timing of edges

on input signals.

It can also be configured in IR Generation Mode where it counts Timer 3 periods and the output is

ANDed with the output of Timer 3 to generate modulated consumer IR signals with minimal CPU

interaction.

The MAC timer (Timer 2) is specially designed for supporting an IEEE 802.15.4 MAC or other

time-slotted protocol in software.

The timer has a configurable timer period and an 8-bit overflow counter that can be used to keep track

of the number of periods that have transpired.

A 16-bit capture register is also used to record the exact time at which a start-of-frame delimiter is

received/transmitted or the exact time at which transmission ends, as well as a 16-bit output compare

register that can produce various command strobes (start RX, start TX, etc.) at specific times to the

radio modules.

Timer 3 and Timer 4 are 8-bit timers with timer/counter/PWM functionality. They have a

programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit

compare value.

Each of the counter channels can be used as a PWM output.

The sleep timer is an ultralow-power timer that counts 32-kHz crystal oscillator or 32-kHz RC oscillator