C278
*0.1u_1 6V_ Y5V _0 4
H_PRO CH OT#
C31 5
0.047u_10V_X7R_04
R51 8 *1.5K _ 1%_0 4
R517
*750_1% _04
H_CPU PW R GD _R
S3 circuit:- DRAM PW R GO OD log ic
R17 4 13 0 _ 1%_ 0 4
CAD Note: Capacitor need to be placed
close to buffer output pin
R512
75_04
R529 200_1%_04
R531 140_1%_04
R52 8 25 .5 _ 1 %_0 4
R498 *10mil_short
R11 0 62 _ 0 4
R515 43.2_1%_04
R499 10K_04
1.05VS_VTT
TRACE WIDTH 10MIL, LENGTH <500MILS
H_CPUPWRGD_R
Processor Pul lu ps /P ul l do wn s
H_PROCHOT#
R10 9 56 _ 1 % _04
1.05VS_VTT
3.3VS
1.05V S_V TT2,5,23 ,24,25,35,39
3.3V2,8,11,12,16,18,19,20,22,23,24,25,27,28,29,30,33,35, 37,38,39
CLK_EXP_N 19
CLK_EXP_P 1 9
1.5VS_C PU6,35,38
CLK_DP_P 19
CLK _ DP _ N 19
H_PROCHOT#39
H_THRMTRIP#23
H_P ECI23,34
H_PM_SYNC20
H_CP UPW R GD23
BUF_CPU_RST#
XDP _DBR_R
S
D
G
Q37A
MTD N7002ZH S6R
2
61
S
D
G
Q37B
MTDN7002ZHS6R
5
34
H _ SNB_IVB#23
SM _RCO MP _2
SM _RCO MP _1
SM _RCO MP _0
XDP _TRST#
XDP _TCLK
VDD PWRGOOD_R
H_PRO CH OT# _ D
XDP _TMS
H_PR OC HO T#
CPUDRAMRST#
XDP _PREQ#
XDP _TDI_R
XDP _TDO_R
R524
100K_04
If PROCHOT# is not us ed,
th en it must b e t erminate d
with a 56-O +-5% pull-up
resistor to 1.05VS_VTT .
D DR 3 Co mp ens at io n Sign al s
BUF_ C PU_RS T#
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U49B
PZ98827-364B-01F
SM _ RC OM P[1]
A5
SM _ RC OM P[2]
A4
SM_DR AMRST #
R8
SM _ RC OM P[0]
AK1
BC L K#
A27
BC LK
A28
DPLL_REF_SSCLK#
A15
DPLL _R EF _ SSC LK
A16
CA TER R#
AL33
PEC I
AN33
PR OC HOT#
AL32
THER MTR IP#
AN32
SM _D RAMPW R OK
V8
RE S ET#
AR33
PR DY #
AP29
PREQ #
AP27
TCK
AR26
TMS
AR27
TR S T #
AP30
TDI
AR28
TDO
AP26
DBR #
AL35
BPM #[0]
AT28
BPM #[1]
AR29
BPM #[2]
AR30
BPM #[3]
AT30
BPM #[4]
AP32
BPM #[5]
AR31
BPM #[6]
AT31
BPM #[7]
AR32
PM _SY NC
AM34
SKTOC C#
AN34
PR OC _SE LEC T #
C26
UN CO REP W RG OO D
AP33
C621
68p_50V_NPO _04
PLT_RST#12,22,28
XDP _BPM0_ R
XDP _BPM1_ R
XDP _BPM2_ R
R658
10K _04
1.5V6,8,9,10,25,29,35,37,38
XDP _BPM4_ R
XDP _BPM3_ R
XDP _BPM5_ R
XDP _BPM6_ R
XDP _BPM7_ R
XDP _PRDY #
PM SYS _PW RG D_BUF
C62 2
47 p _ 50 V _ N P O _ 0 4
R186 0_04
H_PR OCH OT# _ EC34
R203
100K_04
Sandy Bridge Processor 2/7 ( CLK,MISC,JTAG )
3.3VS9,10,11,12, 18,19,20,21,22, 23,24,25,27,28,29,30,31,32,33,34,35,39
Q1 6
MTN7002ZHS3
G
DS
Bu ff er ed re se t to C PU
Q1 7
MTN7002ZHS3
G
DS
R225
4.99K_1% _04
CPU DR AMR ST#
R23 1 * 0 _04
R230
1K_04
1.5V
S3 circuit:- DRAM_ RS T# to me mo ry
should be high during S3
DRAMRST_CNTRL 8,19
R23 5 1K_ 04
DD R3 _ DR AMR ST # 9,1 0
R51 351_0 4
R50 651_0 4
R51 051_0 4
R51 151_0 4
R50 551_0 4
R50 8*51_04
3.3V S
1. 0 5 V S _ V T T
R494 1K_04
XD P _ TD O _ R
XD P_DBR _R
H_CATERR#
PU/PD for J TA G si gn al s
XD P_ TR ST#
XD P _ TM S
H _SNB_ IVB#
XD P_ PREQ #
XD P _ TD I _ R
XD P _ TC L K
U14
* MC 7 4V H C 1 G 08 D F T 1G
1
2
5
4
3
1.8VS_PWRGD20,37
PM _D RA M_PWR GD20
3.3V
R187
*200_04
P MSY S_ PW RG D_ BU F
R18 8
*100K_04
1.5VS_CPU
R175
200_1%_04
R168
*39_04
Q13
*MTN7002ZH S3
G
DS
SU SB35,37, 38
3.3V