M-982-02
www.clare.com
3
Rev. 4
Call Progress Tones
Frequency (HZ) Use
12
350 440 Dial Tone
400 Off Special
440 Off Alert Tone
440 480 Audible Ring
440 620 Pre-empt
480 Off Bell High Tone
480 620 Reorder (Bell Low)
350 Off Special
620 Off Special
941 1209 DTMF “*”
425 Off European
Specifications (continued)
Parameter Conditions Min Max Units Notes
SIGIN pin Voltage range - -6.5 VDD V
Input impedance f=500 Hz 80 - kΩ
Input spectrum - - 28 kHz
Clock External clock VIL XOUT open - 0.2 V
connected to XIN pin VIH XOUT open VDD-0.2 - V
Duty cycle XOUT open 40 60 %
XIN, XOUT with crystal Capacitance - - 10 pF
osc. active Internal resistance - 20 - MW
Power up (TPU) PD hi to lo - 30 ms
X358 pin VOL CL = 20 pF, - 0.2 V
ISINK = -1mA
VOH CL = 20 pF,
ISOURCE =1mA VDD - 0.2 - V
Duty cycle CL = 20 pF 40 60 %
Tri-state tEN,(High Z to Low Z) CL = 50 pF, - 250 ns
Operation tDE,(Low Z to High )Z RL = 100 kW - 250 ns
Unless otherwise noted, VDD- VSS= 5V, Ta = 25°C, PD at logical low state, and XRANGE at a logical high state.
Power levels are in dBm referenced to 600 ohm. DC voltages are referenced to V
SS
.
Notes:
1. Per tone.
Pin Functions
Pin Funtion
DET 1 Active high tri-state output, detect for 350 Hz.
DET 2 Active high tir-state ooutput, detect for 400/620 Hz.
(See Note.)
DET 3 Active high tri-state output, detect for 440 Hz.
DET 4 Active high tri-state output, detect for 480 Hz.
DET 5 Active high tri-state output, detect for 425 Hz.
EN Active high enabled, when low drives STROBE low.
OE Active high input. When low tri-state DET n pins.
SIGIN Analog signal input (internally capacitive coupled).
STROBE Active high output, indicates valid DET n.
V
DD
Most positive power supply input pin.
V
REF
Internally generated mid-power supply voltage
(output).
V
SS
Most negative power supply input pin.
X358 Buffered oscillator output (3.58 MHz).
XIN Crystal oscillator or digital clock input.
XOUT Crystal oscillator output. Used only with a crystal.
Use X358 when clock output signal is required.
XRANGE Active low input. Adds 10 dB of gain to input stage.
MODE Compatibility selection. Connection to VSS selects
400 Hz detection. (M-981-02 emulation.) Connection
to VDDor no connection selects 620 Hz detection.
PD Power-down operation, logic high inhibits internal
clock. Internal pulldown resistor.
Note: This output indicates 400 Hz detect when MODE is connected to VSSand 620
Hz detect when open, or connected to VDD.