CIRRUS LOGIC EP9315 DATA SHEET

EP9315 Data Sheet

FEATURES

• 200-MHz ARM920T Processor

• 16-kbyte Instruction Cache

• 16-kbyte Data Cache

• Linux

• 100-MHz System Bus

• MaverickCrunch

• Floating Point, Integer, and Signal Processing

• Optimized for digital music compression and

• Hardware interlocks allow in-line coding.

• MaverickKey

• 32-bit Unique ID can be used for DRM-compliant

• Integrated Peripheral Interfaces

• 32-bit SDRAM Interface (up to 4 Banks)

• 32-/16-bit SRAM / FLASH / ROM

• Serial EEPROM Interface

• EIDE (up to 2 devices)

• 1/10/100-Mbps Ethernet MAC

• Three UARTs

• Three-port USB 2.0 Full-speed Host (OHCI)

• LCD and Raster Interface with Graphics

, Microsoft® Windows® CE-enabled MMU

™

Math Engine

Instructions

decompression algorithms.

™

IDs

128-bit random ID.

(12 Mbits per second)

Accelerator

Enhanced Universal Platform

System-on-Chip Processor

• IrDA Interface

• PCMCIA Interface

• Touchscreen Interface with ADC

• 8 x 8 Keypad Scanner

• One Serial Peripheral Interface (SPI

• 6-channel or 2-channel Serial Audio Interface (I

• 2-channel, Low-cost Serial Audio Interface (AC'97)

• 2 High-resolution PWMs (16 bits each)

• Internal Peripherals

• 12 Direct Memory Access (DMA) Channels

• Real-time Clock with Software Trim

• Dual PLL controls all clock domains.

• Watchdog Timer

• Two General-purpose 16-bit Timers

• One General-purpose 32-bit Timer

• One 40-bit Debug Timer

• Interrupt Controller

•Boot ROM

• Package

• 352-pin PBGA

™

) Port

COMMUNICATIONS PORTS

http://www.cirrus.com

Serial Audio

Interface

(3) UARTs

IrDA

(3) USB

Hosts

Ethernet

MAC

12-channel DMA

MaverickKey

EIDE

I/F

Boot ROM

SRAM & Flash I/F

PCMCIA

Peripheral Bus

MaverickCrunch

ARM920T

D-Cache

16KB

I-Cache

16KB

MMU

Unified

SDRAM I/F

Video/LCD

Controller

Bus

Bridge

Graphics

Accelerator

Clocks &

Timers

Interrupts

& GPIO

Keypad &

Touch

Screen I/F

Processor Bus

USER INTERFACE

MEMORY AND STORAGE

DS638PP4

EP9315 Enhanced Universal Platform SOC Processor

OVERVIEW

The EP9315 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications:

• Thin Client Computers for Business and Home

• Internet Radio

• Internet Access Devices

• Industrial Computers

• Specialized Terminals

• Point-of-sale Terminals

• Test and Measurement Equipment

The ARM920T microprocessor core with separate 16-kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunch™ coprocessor, enabling high-speed floating point calculations.

MaverickKey solution to the growing concern o ver sec ure web conten t and commerce. With Internet security playing an important role in the delivery of digital media such as

™

unique hardware programmed IDs are a

books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism.

A high-performance 1/10/100-Mbps Ethernet media access controller (EMAC) is included along with external

interfaces to SPI, I

S audio, Raster/LCD, IDE storage

peripherals, keypad, and touchscreen. A three-port USB

2.0 Full Speed Host (OHCI) (12 Mbits per second) and three UARTs are included as well.

The EP9315 is a high-performance, low-power, RISCbased, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1.8 V supply, while the I/O operates at 3.3 V with power usage between 100 mW and 750 mW (dependent on speed).

Table A. Change History

Revision Date Changes

PP1 January 2004 Initial Release. PP2 July 2004 PP3 Febuary 2005 Update electrical characteristics based upon more complete characterization data.

PP4 March 2005 Minor correction to block diagram on page 1. DD7 changed to pull down.

Update AC data. Add ADC data.

EP9315 Enhanced Universal Platform SOC Processor

List of Figures

Figure 1. Timing Diagram Drawing Key .................................................................................14

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement .....................................15

Figure 3. SDRAM Burst Read Cycle Timing Measurement ...................................................16

Figure 4. SDRAM Burst Write Cycle Timing Measurement ...................................................17

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18

Figure 6. Static Memory Single Word Read Cycle Timing Measurement ..............................19

Figure 7. Static Memory Single Word Write Cycle Timing Measurement ..............................20

Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement ....................21

Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement ....... .... ... ... ...22

Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement ................23

Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement ................24

Figure 12. Static Memory Burst Read Cycle Timing Measurement .......................................25

Figure 13. Static Memory Burst Write Cycle Timing Measurement .......................................26

Figure 14. Static Memory Single Read Wait Cycle Timing Measurement .............................27

Figure 15. Static Memory Single Write Wait Cycle Timing Measurement ..............................28

Figure 16. Static Memory Turnaround Cycle Timing Measurement .......................................29

Figure 17. PCMCIA Read Cycle Timing Measurement .................... ...... .......... ......... .......... ...30

Figure 18. PCMCIA Write Cycle Timing Measurement ................................ ..........................31

Figure 19. Register Transfer to/from Device ................................................................. .........33

Figure 20. PIO Data Transfer to/from Device ............... ... .... ... ... ....................................... ... ...35

Figure 21. Initiating an Ultra DMA data-in Burst ..................... ... ... ....................................... ...37

Figure 22. Sustained Ultra DMA data-in Burst .......................................................................38

Figure 23. Host Pausing an Ultra DMA data-in Burst ................... .... ... ... ................................38

Figure 24. Device Terminating an Ultra DMA data-in Burst ...................................................39

Figure 25. Host Terminating an Ultra DMA data-in Burst .......................................................40

Figure 26. Initiating an Ultra DMA data-out Burst ..... ... ... ....................................... ... .... .........41

Figure 27. Sustained Ultra DMA data-out Burst .....................................................................42

Figure 28. Device Pausing an Ultra DMA data-out Burst ....... ....................................... ......... 42

Figure 29. Host Terminating an Ultra DMA data-out Burst ....................................................43

Figure 30. Device Terminating an Ultra DMA data-out Burst .................... ... .... ... ... ... .... ... ......44

Figure 31. Ethernet MAC Timing Measurement .....................................................................46

Figure 32. TI Single Transfer Timing Measurement ............................ ... ...... ....... ...... ....... ......48

Figure 33. Microwire Frame Format, Single Transfer ......... ... ... ... .... ... ... ................................48

Figure 34. SPI Format with SPH=1 Timing Measurement .....................................................49

Figure 35. Inter-IC Sound (I2S) Timing Measurement ...........................................................50

Figure 36. AC ‘97 Configuration Timing Measurement .................... ...................................... 51

Figure 37. LCD Timing Measurement ....................................................................................52

Figure 38. ADC Transfer Function .........................................................................................53

Figure 39. JTAG Timing Measurement .................. ................................................................ 54

Figure 40. 352 Pin PBGA Pin Diagram ..................................................................................55

Figure 40. 352 PIN BGA PINOUT .........................................................................................57

List of Tables

Table A. Change History ..................................... ... ... ....................................... ... .... ................. 2

Table B. General Purpose Memory Interface Pin Assignments ................................ .............. 6

Table C.IDE Interface Pin Assignments .................................................................................. 7

Table D.Ethernet Media Access Controller Pin Assignments ................................................. 7

Table E. Audio Interfaces Pin Assignment .............................................................................. 7

Table F. LCD Interface Pin Assignments . ... .... ... ... ... .... ... ...... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... . 8

Table G.Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8

Table H.64-Key Keypad Interface Pin Assignments ............................................................... 8

Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9

Table J. Triple Port USB Host Pin Assignments ..................................................................... 9

Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9

Table L. Real-Time Clock with Pin Assignments ............................................. ... .... ... ... ... ...... 10

Table M. PLL and Clocking Pin Assignments ............................ ... ... ... ... .... ... ... ... .... ... ... ...... ... 10

Table N.External Interrupt Pin Assignment ........................................................................... 10

Table O.Dual LED Pin Assignments ......................................... ... ... ...................................... 10

Table P. General Purpose Input/Output Pin Assignment ...................................................... 11

Table Q.Reset and Power Management Pin Assignments ................................................... 11

Table R.Hardware Debug Interface ...................................................................................... 11

Table S. PCMCIA Interface ......................... .... ... ... ....................................... ... ... ................... 11

Table R.352 Pin Diagram Dimensions .................................................................................. 56

Table S. Pin Descriptions ..................................... ... ....................................... ... .... ............... 60

Table T. Pin Multiplex Usage Information ............................................................................. 62

EP9315

Enhanced Universal Platform SOC Processor

EP9315 Enhanced Universal Platform SOC Processor

Processor Core - ARM920T

The ARM920T is a Harvard architecture processor with separate 16-kbyte instruction and data caches with an 8word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. Key features include:

• ARM (32-bit) and Thumb (16-bit compressed) Instruction Sets

• 32-bit Advanced Micro-Controller Bus Architecture (AMBA)

• 16-kbyte Instruction Cache with Lockdown

• 16-kbyte Data Cache (pro grammable write-throu gh or write-back) with Lockdown

• MMU for Linux

, Microsoft® Windows® CE and Other

Operating Systems

• Translation Look Aside Buffers with 64 Data and 64 Instruction Entries

• Programmable Page Sizes of 1 Mbyte, 64 kbyte, 4 kbyte, and 1 kbyte

• Independent Lockdown of TLB Entries

MaverickCrunch™ Math Engine

The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include:

• IEEE-754 single and double precision floating point

• 32 / 64-bit integer

• Add / multiply / compare

• Integer MAC 32-bit input with 72-bit accumulate

• Integer Shifts

• Floating point to/from integer conversion

• Sixteen 64-bit register files

• Four 72-bit accumulators

MaverickKey™ Unique ID

MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quick ly becoming unreliable. The MaverickKey unique IDs

provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP9315 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9315 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances.

General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH)

The EP9315 features a unified memory address model where all memory devices are accessed over a common address/data bus. A separate internal po rt is dedicated to the read-only Raster/LCD refresh engine, while the rest of the memory accesses are performed via the Processor bus. The SRAM memory controller supports 8, 16 and 32-bit devices and accommodates an internal boot ROM concurrently with 32-bit SDRAM memory.

• 1-4 banks of 32-bit 66 or 100 MHz SDRAM

• One internal port dedicated to the Raster/LCD Refresh Engine (Read Only)

• Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory

• NOR FLASH memory supported

Table B. General Purpose Memory Interface Pin Assignments

Pin Mnemonic Pin Description

SDCLK SDRAM Clock SDCLKEN SDRAM Clock Enable SDCSn[3:0] SDRAM Chip Selects 3-0 RASn SDRAM RAS CASn SDRAM CAS SDWEn SDRAM Write Enable CSn[7:6] and CSn[3:0] Chip Selects 7, 6, 3, 2, 1, 0 AD[25:0] Address Bus 25-0 DA[31:0] Data Bus 31-0 DQMn[3:0] SDRAM Output Enables / Data Masks WRn SRAM Write Strobe RDn SRAM Read / OE Strobe WAITn SRAM Wait Input

EP9315

Enhanced Universal Platform SOC Processor

IDE Interface

The IDE Interface provides an industry-standard connection to two AT Advanced Packet Interface (ATAPI) compliant devices. The IDE port will attach to a master and a slave device. The internal DMA controller performs all data transfers using the Ultra DMA modes. The interface supports the following operating modes:

• PIO Mode 0 thru 4

• Ultra DMA Modes 0 thru 3

Table C. IDE Interface Pin Assignments

Pin Mnemonic Pin Description

DD[15-0] IDE Data bus IDEDA[2-0] IDE Device address IDECSn[0,1] IDE Chip Select 0 and 1 DIORn IDE Read Strobe DIOWn IDE Write Strobe DMACKn IDE DMA acknowledge

Ethernet Media Access Controller (MAC)

The MAC subsystem is compliant with the ISO/TEC

802.3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include:

• Supports 1/10/100 Mbps transfer rates for home / small-business / large-business applications

• Interfaces to an off-chip PHY through industry standard Media Independent Interface (MII)

Table D. Ethernet Media Access Controller Pin Assignments

Pin Mnemonic Pin Description

MDC Management Data Clock MDIO Management Data I/O RXCLK Receive Clock MIIRXD[3:0] Receive Data RXDVAL Receive Data Valid RXERR Receive Data Error TXCLK Transmit Clock MIITXD[3:0] Transmit Data TXEN Transmit Enable TXERR Transmit Error CRS Carrier Sense CLD Collision Detect

Serial Interfaces (SPI, I2S and AC ’97)

The SPI port can be configured as a master or a slave,

supporting the National Semi conductor

Texas Instruments

signaling protocols.

, Motorola® and

The AC'97 port supports multiple codecs for multicha nnel audio output with a single stereo input. Three I

S ports

can be configured to support six channel 24-bit audio. These ports are multiplexed so that I

S port 0 will take over either the AC'97 pins or the SPI pins. The second and third I2S ports' serial input and serial output pins are multiplexed with EGPIO[4,5,6,13]. The clocks supplied in the first I2S port are also used for the second and third I2S ports.

• Normal Mode: One SPI Port and one AC’97 Port

•I

S on SSP Mode: One AC’97 Port and up to three I2S

Ports

•I

S on AC’97 Mode: One SPI Port and up to three I2S

Ports

Table E. Audio Interfaces Pin Assignment

Normal Mode

Name

SCLK1 SPI Bit Clock I2S Serial Clock SPI Bit Clock SFRM1 SPI Frame Clock I2S Frame Clock SPI Frame Clock SSPRX1 SPI Serial Input I2S Serial Input SPI Serial Input

SSPTX1

ARSTn AC'97 Reset AC'97 Reset I2S Master Clock ABITCLK AC'97 Bit Clock AC'97 Bit Clock I2S Serial Clock

ASYNC

ASDI

ASDO

Description

SPI Serial Output

AC'97 Frame Clock

AC'97 Serial Input

AC'97 Serial Output

I2S on SSP

Mode

Pin Description Pin Description

I2S Serial Output SPI Serial Output (No I2S Master

Clock)

AC'97 Frame Clock

AC'97 Serial Input I2S Serial Input AC'97 Serial

Output

I2S on AC'97

Mode

I2S Frame Clock

I2S Serial Output

Raster / LCD Interface

The Raster / LCD interface provides data and interface signals for a variety of display types. It features fully programmable video interface timing for non-interlaced flat panel or dual scan displays. Resolutions up to 1024 x 768 are supported from a unified SDRAM based frame buffer. A 16-bit PWM provides control for LCD panel contrast. LCD specific features include:

EP9315 Enhanced Universal Platform SOC Processor

• Timing and interface signals for digital LCD and TFT displays

• Full programmability for either non-interlaced or dualscan color and grayscale flat panel displays

• Dedicated data path to SDRAM controller for improved system performance

• Pixel depths of 4, 8, 16, or 24 bits per pixel or 256 levels of grayscale

• Hardware Cursor up to 64 x 64 pixels

• 256 x 18 Color Lookup Table

• Hardware Blinking

• 8-bit interface to low end panel

Table F. LCD Interface Pin Assignments

Pin Mnemonic Pin Description

SPCLK Pixel Clock P[17:0] Pixel Data Bus [17:0]

HSYNC / LP

VCSYNC / FP BLANK Composite Blank

BRIGHT Pulse Width Modulated Brightness

Horizontal Synchronization / Line Pulse

Vertical or Composite Synchronization / Frame Pulse

Graphics Accelerator

The EP9315 contains a hardware graphics acceleration engine that improves graphic performance by handling block copy, block fill and hardware line draw operations. The Graphics Accelerator is used in the system to offload graphics operations from the processor.

Pixel depths supported by the Graphics Accelerator are 4, 8, 16 or 24 bits per pixel. The 24 bits per pixel mode can be operated as packed (4 pixels every 3 words) or unpacked (1 pixel per word with the high byte unused.)

The block copy operations of the Graphics Accelerator are similar to a DMA (Direct Memory Access) transfer that understands pixel organization, block width, transparency, and transformation from 1bpp to higher 4, 8, 16 or 24bpp.

The line draw operations also allow for solid lines or dashed lines. The colors for line drawing can be either foreground color and background color or foreground color with the background being transparent.

only interrupts the processor when a meaningful change occurs. The touch screen hardware may be disabled and the switch matrix and ADC controlled directly if desired. Features include:

• Support for 4-, 5-, 7-, or 8-wire analog resistive touch screens.

• Flexibility - unused lines may be used for temperature sensing or other functions.

• Touch screen interrupt function.

Table G. Touch Screen Interface with 12-bit Analog-to-Digital

Converter Pin Assignments

Pin Mnemonic Pin Description

Xp, Xm Touch screen ADC X Axis Yp, Ym Touch screen ADC Y Axis

SXp, SXm

SYp, SYm

Touch screen ADC X Axis Voltage Feedback

Touch screen ADC Y Axis Voltage Feedback

64-Key Keypad Interface

The keypad circuitry scans an 8 x 8 array of 64 normally open, single-pole switches. Any one or two keys depressed will be de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys is detected. If the keypad is not utilized, the 16 column/row pins may be used as general purpose I/O. The Keypad interface:

• Provides scanning, debounce, and decoding for a 64key switch array.

• Scans an 8-row by 8-column matrix.

• May decode 2 keys at once.

• Generates an interrupt when a new stable key is determined.

• Also generates a 3-key reset interrupt.

Table H. 64-Key Keypad Interface Pin Assignments

Pin Mnemonic

COL[7:0]

ROW[7:0]

Description

Key Matrix Column Inputs

Key Matrix Row Inputs

Alternative Usage

General Purpose I/O

Touch Screen Interface with 12-bit Analogto-digital Converter (ADC)

The touch screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog resistive touch screens. This controller

EP9315

Enhanced Universal Platform SOC Processor

Universal Asynchronous Receiver/T ransmitters (UARTs)

Three 16550-compatible UARTs are supplied. Two provide asynchronous HDLC (High-level Data Link Control) protocol support for full-duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the

UART FIFOs to buffer the data streams. A third IrDA compatible UART is also supplied.

• UART1 supports modem bit rates up to 115.2 Kbps, supports HDLC and includes a 16-byte FIFO for receive and a 16-byte FIFO for transmit. Interrupts are generated on Rx, Tx, and modem status change.

• UART2 contains an IrDA encoder operating at eith er the slow (up to 115 Kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16byte FIFO for receive and a 16-byte FIFO for transmit.

• UART3 supports HDLC and includes a 16-byte FIFO for receive and a 16-byte FIFO for transmit. Interrupts are generated on Rx and Tx.

Triple Port USB Host

The USB Open Host Controller Interface (Open HCI) provides full speed serial communications ports at a baud rate of 12 Mbits/sec. Up to 127 USB devices (printer, mouse, camera, keyboard, etc.) and USB hubs can be connected to the USB host in the USB “tieredstart” topology.

This includes the following features:

• Compliance with the USB 2.0 specification

• Compliance with the Open HCI Rev 1.0 specification

• Supports both low speed (1.5 Mbp s) and full speed

(12 Mbps) USB device connections

• Root HUB integrated with 3 downstream USB ports

• Transceiver buff ers integrated, over-current protection on ports

• Supports power management

• Operates as a master on the bus

The Open HCI host controller initializes the master DMA transfer with the AHB bus:

• Fetches endpoint descriptors and transfer descriptors

• Accesses endpoint data from system memory

• Accesses the HC communication area

• Writes status and retire transfer descriptor

Table I. Universal Asynchronous Receiver/Transmitters Pin

Pin Mnemonic Pin Name - Description

TXD0 UART1 Transmit RXD0 UART1 Receive

CTSn

DSRn / DCDn DTRn UART1 Data Terminal Ready

RTSn UART1 Ready To Send EGPIO[0] / RI UART1 Ring Indicator

TXD1 / SIROUT RXD1 / SIRIN UART2 Receive / IrDA Input

TXD2 UART3 Transmit RXD2 UART3 Receive EGPIO[3] / TENn HDLC3 Transmit Enable

Assignments

UART1 Clear To Send / Transmit Enable

UART1 Data Set Ready / Data Carrier Detect

UART2 Transmit / IrDA Output

Table J. Triple Port USB Host Pin Assignments

Pin Mnemonic Pin Name - Description

USBp[2:0] USB Positive signals USBm[2:0] USB Negative Signals

Two-wire Interface

The two-wire interface provides communication and control for synchronous-serial-driven devices.

Table K. Two-Wire Port with EEPROM Support Pin Assignments

Pin Mnemonic Pin Name - Description

EECLK Two-Wire Interface Clock

EEDATA Two-Wire Interface Data

Alternative

Usage

General Purpose I/O

EP9315 Enhanced Universal Platform SOC Processor

Real-Time Clock with Software Trim

The software trim feature on the real time clock (RTC) provides software controlled digital compensation of the

32.768 kHz input clock. This compensation is accurate to

± 1.24 sec/month.

Note: A real time clock must be connected to RTCXTALI or

the EP9315 device will not boot.

Table L. Real-Time Clock with Pin Assignments

Pin Mnemonic Pin Name - Description

RTCXTALI Real-Time Clock Oscillator Input RTCXTALO Real-Time Clock Oscillator Output

PLL and Clocking

The processor and the peripheral clocks operate from a single 14.7456 MHz crystal.

The real time clock operates from a 32.768 kHz external oscillator.

Table M. PLL and Clocking Pin Assignments

Pin Mnemonic Pin Name - Description

XTALI Main Oscillator Input XTALO Main Oscillator Output VDD_PLL Main Oscillator Power GND_PLL Main Oscillator Ground

Timers

low, level-sensitive inputs. GPIO may be programmed as active-high level-sensitive, active-low level-sensitive, rising-edge-triggered, falling-edge-triggered, or combined rising/falling-edge-triggered.

• Supports 64 interrupts from a variety of sources (such as UARTs, GPIO, and key matrix)

• Routes interrupt sources to either the ARM920T’s IRQ or FIQ (Fast IRQ) inputs

• Four dedicated off-chip interrupt lines INT[3:0] operate as active-high, level-sensitive interrupts

• Any of the 16 GPIO lines maybe configured to generate interrupts

• Software supported priority mask for all FIQs and IRQs

Table N. External Interrupt Pin Assignment

Pin Mnemonic Pin Name - Description

INT[3:0] External Interrupt 3-0

Dual LED Drivers

Two pins are assigned specifically to drive external LEDs.

Table O. Dual LED Pin Assignments

Pin Mnemonic

GRLED Green LED General Purpose I/O REDLED Red LED General Purpose I/O

Pin Name -

Description

Alternative Usage

The Watchdog Timer insures proper operation by requiring periodic attention to prevent a reset-on-timeout.

General Purpose Input/Output (GPIO)

The 16 EGPIO pins may each be configured individually as an output, an input, or an interrupt input. Port F may

Two 16-bit timers operate as free running down-counters or as periodic timers for fixed interval interrupts and have a range of 0.03 ms to 4.27 seconds.

One 32-bit timer, plus a 6-bit prescale counter, has a range of 0.03 µs to 73.3 hours.

One 40-bit debug timer , plu s 6-bit prescale co unter, has a range of 1.0 µs to 12.7 days.

Interrupt Controller

The interrupt controller allows up to 64 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments are provided fo r assisting

be configured as GPIO. Each Port F pin may be configured individually as an output, input or an interrupt input.

There are 23 pins that may be used as alternate input s or outputs, but do not support interrupts. These pins are:

• Key Matrix ROW[7:0], COL[7:0]

• Ethernet MDIO

• Both LED Outputs

• Two-wire Clock and Data

• SLA [1:0]

6 pins may alternatively be used as inputs only:

• CTSn, DSRn / DCDn

• 4 Interrupt Lines

IRQ vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible. Internal interrupts may be programmed as active-high or active-

2 pins may alternatively be used as outputs only:

•RTSn

•ARSTn

EP9315

Enhanced Universal Platform SOC Processor

Table P. General Purpose Input/Output Pin Assignment

Pin Mnemonic Pin Name - Description

EGPIO[15:0]

FGPIO[7:0]

Note: Port F defaults as PCMCIA pins. Port F must be

configured by software to be used as GPIO.

Expanded General Purpose Input / Output Pins with Interrupts

Reset and Power Management

The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn.

Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power.

The processor clock is dynamically adjustable from 0 to 200 MHz (184 MHz for industrial conditions).

Table Q. Reset and Power Management Pin Assignments

Pin Mnemonic Pin Name - Description

PRSTn Power On Reset RSTOn

User Reset In/Out – Open Drain – Preserves Real Time Clock value

Hardware Debug Interface

The JTAG interface allows use of ARM’s Multi-ICE or other in-circuit emulators.

Note: The JTAG interface does not support boundary scan.

Table R. Hardware Debug Interface

Pin Mnemonic Pin Name - Description

TCK JTAG Clock TDI JTAG Data In TDO JTAG Data Out TMS JTAG Test Mode Select TRSTn JTAG Port Reset

Internal Boot ROM

12-channel DMA Controller

The DMA module contains 12 separate DMA channels. Ten of these may be used for peripheral-to-memory or memory-to-peripheral access. Two of these are dedicated to memory-to-memory transfers. Each DMA channel is connected to the 16-bit DMA request bus.

The request bus is a collection of requests, Serial Audio, and UARTs. Each DMA channel can be used independently or dedicated to any request signal. For each DMA channel, source and destination addressing can be independently programmed to increment, decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses.

PCMCIA Interface

The EP9315 has a single PCMCIA port which can be used to access either 8 or 16-bit devices.

Table S. PCMCIA Interface

Pin Mnemonic Pin Name - Description

VS1 Voltage sense VS2 Voltage sense MCD1 Card detect MCD2 Card detect MCBVD1 Voltage detection / status change MCBVD2 Voltage detection MCDIR Data transceiver direction control MCDAENn Data bus transceiver enable MCADENn Address bus transceiver enable MCREGn Memory card register MCEHn Memory card high byte select MCELn Memory card low byte select IORDn I/O card read IOWRn I/O card write MCRDn Memory card read MCWRn Memory card write READY Ready / interrupt WP Write protect MCWAITn Wait Input MCRESETn Card reset

The Internal 16-kbyte ROM allows booting from FLASH memory, SPI or UART. Consult the EP93xx User’s Manual for operational details

EP9315 Enhanced Universal Platform SOC Processor

Electrical Specifications

Absolute Maximum Ratings

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter Symbol Min Max Unit

RVDD

Power Supplies

Total Power Dissipation (Note 1) - 2 W Input Current per Pin, DC (Except supply pins) - ±10 mA Output current per pin, DC -±50mA Digital Input voltage (Note 2) -0.3 RVDD+0.3 V Storage temperature -40 +125 °C

Note: 1. Includes all power generated due to AC and/or DC output loading.

2. The power supply pins are at recommended maximum values.

3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts.

CVDD

VDD_PLL

VDD_ADC

3.96

2.16

3.96

V V V V

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

Recommended Operating Conditions

(All grounds = 0 V, all voltages with respect to 0 V)

Parameter Symbol Min Typ Max Unit

RVDD

Power Supplies

Operating Ambient Temperature - Commercial Operating Ambient Temperature - Industrial Processor Clock Speed - Commercial FCLK - - 200 MHz

Processor Clock Speed - Industrial FCLK - - 184 MHz System Clock Speed - Commercial HCLK - - 100 MHz System Clock Speed - Industrial HCLK - - 92 MHz

CVDD

VDD_PLL

VDD_ADC

3.0

1.65

3.0 0+25+70°C

-40 +25 +85 °C

3.3

1.80

3.3

3.6

1.94

3.6

V V V V

DC Characteristics

(TA = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted)

Parameter Symbol Min Max Unit

High level output voltage Iout = -4 mA (Note 4) Low level output voltage Iout = 4 mA High level input voltage (Note 5) Low level input voltage (Note 5) High level leakage current Vin = 3.3 V (Note 5) Low level leakage current Vin = 0 (Note 5)

Parameter Min Typ Max Unit

EP9315

Enhanced Universal Platform SOC Processor

0.85 × RVDD - V

- 0.15 × RVDD V

0.65 × RVDD VDD + 0.3 V

-0.3 0.35 × RVDD V

-10 µA

--10 µA

Power Supply Pins (Outputs Unloaded), 25

Power Supply Current: CVDD / VDD_PLL Total

Low-Power Mode Supply Current CVDD / VDD_PLL Total

Note: 4. For open drain pins, high level output voltage is dependent on the external load.

5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on

page 60). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not

driven and programmed as an input, it should be tied to power or ground through its own resistor.

° C

RVDD

190

2 1

240

3.5 2

mA mA

EP9315 Enhanced Universal Platform SOC Processor

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labe lled when they occur. Therefore, no additional meaning should be attached unless specifically stated.

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to Tristate

Bus/Signal Omission

Figure 1. Timing Diagram Drawing Key

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurem e nts.

•T

= 0 to 70° C

• CVDD = VDD_PLL = 1.8V

•RVDD = 3.3V

• All grounds = 0 V

• Logic 0 = 0 V, Logic 1 = 3.3 V

• Output loading = 50 pF

• Timing reference levels = 1.5 V

• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequen cy is typica lly between 33 MHz and 100 MHz (92 MHz for industrial conditions).

EP9315

Enhanced Universal Platform SOC Processor

Memory Interface

Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter Symbol Min Typ Max Unit

SDCLK high time SDCLK low time SDCLK rise/fall time Signal delay from SDCLK rising edge time Signal hold from SDCLK rising edge time DQMn delay from SDCLK rising edge time DQMn hold from SDCLK rising edge time DA valid setup to SDCLK rising edge time DA valid hold from SDCLK rising edge time

clk_high

clk_low

clkrf

DQd

DQh

DAs

DAh

-24ns

--8ns

1--ns

--8ns 1--ns 2--ns 3--ns

(t (t

HCLK HCLK

) / 2 ) / 2

-ns

SDRAM Load Mode Register Cycle

SDCLK

SDCSn

RASn

CASn

SDWEn

DQMn

clkrf

clk_low

clk_high

OP-Code

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

EP9315 Enhanced Universal Platform SOC Processor

SDRAM Burst Read Cycle

SDCLK

SDCSn

RASn

CASn

SDWEn

DQMn

CL = 2

DQMn

CL = 3

CL = 2

clk_low

DQd

DAs

DAh

n n + 1 n + 2 n + 3

clk_high

clkrf

DQh

CL = 3

DAs

DAh

n n + 1 n + 2 n + 3

Figure 3. SDRAM Burst Read Cycle Timing Measurement

SDRAM Burst Write Cycle

SDCLK

SDCSn

RASn

CASn

SDWEn

EP9315

Enhanced Universal Platform SOC Processor

clk_low

clk_high

clkrf

DQMn

n n +1 n + 2 n + 3

Figure 4. SDRAM Burst Write Cycle Timing Measurement

EP9315 Enhanced Universal Platform SOC Processor

SDRAM Auto Refresh Cycle

SDCLK

SDCSn

RASn

CASn

SDWEn

7bde

clk_low

clk_high

clkrf

Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement

Static Memory Single Word Read Cycle

Parameter Symbol Min Typ Max Unit

AD setup to CSn assert time AD hold from CSn deassert time RDn assert time CSn to RDn delay time CSn assert to DQMn assert delay time DA setup to RDn deassert time DA hold from RDn deassert time

See “Timing Conditions” on page 14 for definition of HCLK.

ADs

ADh

RDpw

RDd

DQMd

DAs

DAh

EP9315

Enhanced Universal Platform SOC Processor

0--ns

HCLK

--3ns

--1ns

+ 12

HCLK

0--ns

HCLK

× (WST1 + 2)

--ns

-ns

CSn

WRn

RDn

DQMn

WAIT

ADs

RDd

DQMd

DAs

Figure 6. Static Memory Single Word Read Cycle Timing Measurement

ADh

RDd

DAh

EP9315 Enhanced Universal Platform SOC Processor

Static Memory Single Word Write Cycle

Parameter Symbol Min Typ Max Unit

AD setup to WRn assert time AD hold from WRn deassert time

WRn deassert to CSn deassert time CSn to WRn assert delay time WRn assert time CSn to DQMn assert delay time WRn deassert to DA transition time WRn assert to DA valid

CSn

WRn

ADs

WRd

ADs

ADh

CSh

WRd

WRpw

DQMd

DAh

DAV

- 3

HCLK

× 2

HCLK

--2ns

--1ns

HCLK

--8ns

WRpw

HCLK

--ns

× (WST1 + 1)

CSh

-ns

ADh

RDn

DQMn

WAIT

DQMd

DAV

Figure 7. Static Memory Single Word Write Cycle Timing Measurement

DAh

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