Cirrus Logic EP9312 Datasheet

Preliminary

SERIAL PORTS

USER INTERFACE

EP9312 Product Overview

FEATURES

■ 200MHz ARM920T Processor
— 16kbyte Instruction Cache
— 16kbyte Data Cache
— Windows CE enabled MMU

■ MaverickCrunch
— Floating point, integer and signal processing

instructions

— Optimized for digital music compression and

decompression algorithms

— Hardware interlocks allow in-line coding

■ MaverickLock
— Incorporates boot ROM, laser fuses, and

gate-level IP

— Multiple security vendors can co-exist in same

system

— Exceeds SDMI requirements

™

Math Engine



Security Features

Internet Audio Jukebox Processor

with MaverickCrunch™ Audio

Compression and MaverickLock™

Security

OVERVIEW

The EP9312 is an ARM920T based system on chip
designed for use in audio jukebox applications where
processor performance, signal processing capability,
communications bandwidth, storage capabilities, and the
user interface are properly balanced to provide up to 4
streams of compressed audio data (MP3, WMA, and
other audio compression standards) through a home
network.

(Cont.)(Cont.)

BLOCK DIAGRAM

Serial
Audio

Interface

(3) UARTs

w/

IRDA

(3) USB

Hosts

Ethernet

MAC

DMA w/

CRC

MaverickLock

Boot

ROM

EIDE

I/F

TM

MEMORY AND STORAGE

Peripheral Bus

MaverickCrunch

ARM920T

D-Cache

16KB

I-Cache

16KB

MMU

SRAM &

Flash I/F

TM

Bus

Bridge

Unified

SDRAM I/F

Clocks &

Timers

Interrupts

& GPIO

Keypad &

Touch

Screen I/F

Processor Bus

Video/LCD

Controller

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

Copyright 2001 Cirrus Logic (All Rights Reserved) Jan’01

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EP9312

Internet Audio Jukebox Processor Preliminary

FEATURES (cont.)

■ Integrated Peripheral Interfaces
— EIDE (up to 2 devices)
— 1/10/100Mbps Ethernet MAC
— Three 16550 compatible UARTs
— Three-port USB Host
— IRDA Interface
— 32-bit SDRAM Interface up to 4 banks
— 32/16-bit SRAM/FLASH/ROM
— EEPROM Interface

OVERVIEW (cont.)

The ARM920T microprocessor core with separate
16Kbyte, 64-way set-associative instruction and data
caches is augmented by the MaverickCrunch™ co­processor enabling faster than real-time compression of
audio CDs. The proprietary MaverickLock™ technology
exceeds security requirements set forth by SDMI to
protect music content. It may also be used to protect
proprietary firmware, transactions, and other digital
content.

A high-performance 1/10/100Mbps Ethernet Media
Access Controller (EMAC) is included along with

■ Internal Peripherals
— Real-time Clock with software Trim
— Eight Direct Memory Access (DMA) Channels

with Cyclic Redundancy Check (CRC) Generation
— Dual PLL controls all clock domains
— Watchdog Timer
— Interrupt Controller
— Four general purpose 16-bit timers
— 40-bit Debug Timer
— Boot ROM

■ Package
— 352 pin PBGA

2

external interfaces to SPI and I

S audio, LCD, IDE
storage peripherals, keypad, and touchscreen. A three­port USB host and three UARTs are included as well.

The EP9213 is a high-performance, low-power RISC­based single-chip computer built around an ARM920T
microprocessor core with a maximum operating clock
rate of 200MHz. The ARM core is operateS from a 2.5V
supply, while the I/O operates at 3.3V with power
between 350mW and 1000mW dependent on speed.

Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information
describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensu re that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the
property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this p ublication may be copied, reproduced, stored
in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.
Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a
retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the p rior written consent of Cirrus Logic,
Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of
products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be
registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.co m.

2 Copyright 2001 Cirrus Logic (All Rights Reserved) DS515PO3

EP9312

Preliminary Internet Audio Jukebox Processor

Processor Core - ARM920T

The ARM920T is a Harvard architecture processor with
separate 16Kbyte instruction and data caches with an 8­word line length. The processor utilizes a five-stage
pipeline consisting of fetch, decode, execute, memory
and write stages. Key features include:

• ARM (32-bit) and Thumb (16-bit compressed)
instruction sets

• 32-bit Advanced Micro-Controller Bus
Architecture (AMBA)

• 16Kbyte Instruction Cache with lockdown

• 16Kbyte Data Cache (programmable write­through or write-back) with lockdown

®

• MMU for Microsoft

Windows® CE and other

operating systems

• Translation Look Aside Buffers with 64 Data and
64 Instruction Entries

• Programmable Page Sizes of 64Kbyte, 4Kbyte,
and 1Kbyte

• Independent lockdown of TLB Entries

MaverickCrunch™ Math Engine

The MaverickCrunch Engine is a mixed-mode
coprocessor designed primarily to accelerate the math
processing required to rapidly encode digital audio
formats. It accelerates single and double precision integer
and floating point operations plus an integer multiply­accumulate (MAC) instruction that is considerably faster
than the ARM920T's native MAC instruction. The
ARM920T coprocessor interface is utilized thereby
sharing its memory interface and instruction stream.
Hardware forwarding and interlock allows the ARM to
handle looping and addressing while MaverickCrunch
handles computation. Features include:

from several security vendors including Microsoft

®

InterTrust

. It exceeds all the requirements set forth by

®

and

SDMI and allows for protection of object code as well as
content. Features include:

• 256 bits of laser fuses for permanent IDs and
passwords

• Security boot firmware and private passwords are
“invisible” except when the IC is “locked”

• Each instantiation of the system software may be
uniquely encoded and protected by using the
private ID

• Multiple security vendors can co-exist in the same
system

General Purpose Memory Interface
(SDRAM, SRAM, ROM, FLASH)

The Maverick 9312 features a unified memory address
model where all memory devices are accessed over a
common address/data bus. A separate internal port is
dedicated to the read-only LCD refresh engine, while the
rest of the memory accesses are performed via the
Advanced High Performance Bus (AHB). The memory
controller supports both 16- and 32-bit devices and
accommodates a 16-bit boot ROM concurrently with 32­bit SDRAM memory.

• 1-4 banks of 32-bit 66 or 100MHz SDRAM

• One internal port dedicated to the LCD Refresh
Engine (Read Only)

• One internal port dedicated to the rest of the chip
via the AHB

• Address and data bus shared between SDRAM,
SRAM, ROM, and FLASH memory

• Either NAND or NOR FLASH memory supported

• IEEE-754 single and double precision floating
point

• 32/64-bit integer

• Add/multiply/compare

• Integer MAC 32-bit input with 72-bit accumulate

• Integer Shifts

• Floating point to/from integer conversion

• Sixteen 64-bit register files

• Four 72-bit accumulators

MaverickLock™ Security

MaverickLock security is a generalized architecture
consisting of boot ROM, laser fuses, and proprietary
circuitry for secure hardware initialization. In the

Table A. General Purpose Memory Interface Pin Assignments

Pin Mnemonic I/O Pin Description

SDCLK O SDRAM Clock

SDCLKEN O SDRAM Clock Enable

SDCSn[3:0] O SDRAM Chip Selects 3-0

RASn O SDRAM RAS
CASn O SDRAM CAS

SDWEn O SDRAM Write Enable
CSn[7:0] O Chip Selects 7-0
AD[25:0] O Address Bus 25-0
DA[31:0] I/O Data Bus 31-00

DQMn[3:0] O

SDRAM Output Enables / Data

Masks

context of this environment, the EP9312 supports
multiple digital rights management content protection

DS515PO3 Copyright 2001 Cirrus Logic (All Rights Reserved) 3

EP9312

Internet Audio Jukebox Processor Preliminary

Table A. General Purpose Memory Interface Pin Assignments

Pin Mnemonic I/O Pin Description

WRn O SRAM Write Strobe

RDn O SRAM Read/OE Strobe

WAITn I Wait Input

IDE Interface

The IDE Interface provides an industry-standard
connection to two AT Packet Interface (ATAPI) compliant
devices. Each device may be controlled by any of the 8
DMA controllers. The IDE port will attach to a master
and a slave device. The internal DMA controller
performs all data transfers using the Multiword DMA
and Ultra DMA modes. The interface supports the
following operating modes:

• PIO Mode 4

• Multiword DMA Mode 2

• Ultra DMA Mode 2

Table B. IDE Interface Pin Assignments

Pin Mnemonic I/O Pin Description

DD[15-0] I/O IDE Data bus
IDEDA[2-0] O IDE Device address
IDECSn[0,1] O IDE Chip Select 0 and 1
DIORn O IDE Read Strobe
IDORWn O IDE Write Strobe
DMACKn O IDE DMA acknowledge

• Hardware Blinking

• 6-bit Contrast DAC

Table C. LCD Interface Pin Assignments

Pin Mnemonic I/O Pin Description

SPCLK I/O Pixel Clock
P[17:0) O Pixel Data Bus [17:0]

HSYNC/LP O

VCSYNC/FP O

BLANK O Composite Blank
BRIGHT O Pulse Width Modulated Brightness
CDACO O Contrast DAC Output

Horizontal
Synchronization/Line Pulse

Vertical or Composite
Synchronization / Frame Pulse

Ethernet Media Access Controller (EMAC)

The MAC subsystem is compliant with the ISO/TEC
8802-3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:

• Supports 1/10/100Mbps transfer rates for
home/small-business/large-business applications

• Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)

• May be configured entirely by the driver or
through auto-negotiation

Table D. Ethernet Media Access Controller Pin Assignments

LCD Interface

The LCD interface provides data and interface signals for
a variety of display types. It features fully programmable
video interface timing for non-interlaced flat panel or
dual scan displays. Resolutions up to 1024x768 are
supported from a unified SDRAM based frame buffer. A
6-bit DAC provides an analog DC voltage output for the
LCD panel contrast control. LCD specific features
include:

• Provides timing and interface signals for digital
LCD and TFT displays

• Fully programmable for either non-interlaced or
dual-scan color and grayscale flat panel displays

Pin Mnemonic I/O Pin Description

MDC O Management Data Clock
MDIO I/O Management Data I/O
RXCLK I Receive Clock
MIIRXD[3:0] I Receive Data
RXDVAL I Receive Data Valid
RXERR I Receive Data Error
TXCLK I/O Transmit Clock
MIITXD[3:0] O Transmit Data
TXEN O Transmit Enable
TXERR O Transmit Error
CRS I Carrier Sense
CLD I Collision Detect

• Dedicated data path to SDRAM controller for
improved system performance

• Pixel depths of 4-, 8-, 16-, or 18-bits per pixel or 256
levels of grayscale

• Hardware Cursor up to 64 x 64 x 2 pixels

• 256 x 18 Color Lookup Table

4 Copyright 2001 Cirrus Logic (All Rights Reserved) DS515PO3

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Preliminary Internet Audio Jukebox Processor

Touch Screen Interface with 12-bit Analog­to-Digital Converter (ADC)

The touch screen interface performs all sampling,
averaging, ADC range checking, and control for a wide
variety of analog resistive touch screens. This controller
only interrupts the processor when a meaningful change
occurs. The touch screen hardware may be disabled and
the switch matrix and ADC controlled directly if desired.
Features include:

• Supports 4-, 5-, 7-, or 8-wire analog resistive touch
screens

• Unused lines may be used for temperature sensing
or other functions

• Touch screen interrupt function is provided.

Table E. Touch Screen Interface with 12-bit Analog-to-Digital

Converter Pin Assignments

Pin Mnemonic I/O Pin Description

Xp,Xm O Touch screen ADC X Axis
Yp, Ym O Touch screen ADC Y Axis

SXp, SXm I

SYp, SYm I

Touch screen ADC X Axis
Voltage Feedback

Touch screen ADC Y Axis
Voltage Feedback

Audio Interfaces (SPI and I2S)

Two SPI ports are independently configured as masters

®

or slaves, supporting the Motorola

®

Semiconductor

, and Texas Instruments® signaling

protocols. SPI port 0 may be configured as an Inter-IC

2

Sound (I

S) port.

• Two SPI Ports

2

• Alternative I

Table G. Audio Interfaces Pin Assignments

Pin

Mnemonic

SCLK[0] O SPI[0] Clock SCLK
SFRM[0] O SPI[0] Frame Clock LRCLK
SSPRX(0) I SPI[0] Input SDI
SSPTX(0) O SPI[0] Output SDO
SCLK[1] O SPI[1] Clock None
SFRM[1] O SPI[1] Frame Clock None
SPRX(1) I SPI[1] Input None
SSPTX(1) O SPI[1] Output None
ARSTn O - MCCLK

S Port

I/O

Pin

Description

, National

Alternative

Usage (I

2

S)

64-Keypad Interface

The keypad circuitry scans an 8x8 array of 64 normally
open, single pole switches. Any one or two keys
depressed will be de-bounced and decoded. An interrupt
is generated whenever a stable set of depressed keys is
detected. If the keypad is not utilized, the 16
column/row pins may be used as general purpose I/O.

• Provides scanning, debounce and decoding for a
64-key array

• Scans an 8-row by 8-column matrix

• Up to 2 keys may be decoded at once

• An interrupt is generated when new stable key is
determined

• Also generates a 3-key reset interrupt

Table F. 64-Key Keypad Interface Pin Assignments

Pin Mnemonic I/O

COL[7:0] I

ROW[7:0] O

Pin\

Description

Key Matrix
Column Inputs

Key Matrix Row
Inputs

Alternative Usage

General Purpose I/O

General Purpose I/O

Triple Port USB Host

The USB host controller is configured for three root hub
ports and features integrated transceivers for each port.
The controller complies with the Open Host Controller
Interface (OHCI) Specification for USB, Revision 1.1.

Table H. Triple Port USB Host Pin Assignments

Pin Mnemonic I/O Pin Name - Description

USBp[2:0] I/O USB Positive signals
USBm[2:0] I/O USB Negative Signals
USBVDD[1:0] NA USB Power
USBGND[1:0] NA USB Ground

DS515PO3 Copyright 2001 Cirrus Logic (All Rights Reserved) 5