Cirrus Logic EP7312-IR-C, EP7312-IB-C, EP7312-EV-C, EP7312-IV-C, EP7312-CB-C Datasheet

...

FEATURES

■ ARM720T Processor —ARM7TDMI CPU — 8 KB of four-way set-associative cache — MMU with 64-entry TLB — Thumb code support enabled

■ Ultra low power — 90 mW at 74 MHz typical — 30 mW at 18 MHz typical — 10 mW in the Idle State — <1 mW in the Standby State

■ 48 KB of on-chip SRAM

™

■ MaverickKey — 32-bit unique ID can be used for SDMI compliance — 128-bit random ID

■ Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz

IDs

EP7311 Data Sheet

High-Performance,

Low-Power System on Chip with

SDRAM and Enhanced Digital

Audio Interface

OVERVIEW

The Maverick™ EP7311 is designed for ultra-low-power applications such as PDAs, smart cellular phones, and industrial hand held information appliances. The corelogic functionality of the device is built around an ARM720T processor with 8 KB of four-way setassociative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Linux

BLOCK DIAGRAM

Multimedia Codec Port

Serial

Interface

(2) UARTs

SERIAL PORTS

w/ IrDA

Internal Data Bus

MaverickKey

Power

Management

Boot ROM

Memory Controller

(cont.)

ARM720T

ICE-JTAG

ARM7TDMI CPU Core

8 KB

Cache

SDRAM I/FSRAM I/F

Write

Buffer

MMU

EPB Bus

Bus

Bridge

On-chip SRAM

48 KB

(cont.)

Clocks &

Timers

USER INTERFACE

Interrupts,

PWM & GPIO

Keypad&

Touch

Screen I/F

LCD

Controller

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

MEMORY AND STORAGE

DS506PP1

EP7311

High-Performance, Low-Power System on Chip

FEATURES (cont)

■ LCD controller

— Interfaces directly to a single-scan panel

monochrome STN LCD

— Interfaces to a single-scan panel color STN LCD

with minimal external glue logic

■ Full JTAG boundary scan and Embedded ICE support

■ Integrated Peripheral Interfaces

— 32-bit SDRAM Interface up to 2 external banks — 8/32/16-bit SRAM/FLASH/ROM Interface — Multimedia Codec Port — Two Synchronous Serial Interfaces (SSI1, SSI2) — CODEC Sound Interface

×8Keypad Scanner

— 8 — 27 General Purpose Input/Output pins — Dedicated LED flasher pin from the RTC

■ Internal Peripherals

— Two 16550 compatible UARTs — IrDA Interface — Two P WM I nt e rf a ces — Real-time Clock — Two general purpose 16-bit timers

— Interrupt Controller — Boot ROM

■ Package

— 208-Pin LQFP — 256-Ball PBGA



— 204-Ball TFBGA

■ The fully static EP7311 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process

■ Development Kits — EDB7312: Development Kit with color STN LCD

on board.

— EDB7312-LW: EDB7312 with Lynuxworks’

BlueCat Linux Tools and software for Windows host (free 30 day BlueCat support from Lynuxworks ).

— EDB7312-LL: EDB7312 with Lynuxworks’ BlueCat

Linux Tools and software for Linux host (free 30 day BlueCat support from Lynuxworks).

Note: * BlueCat available separately through Lynuxworks

only. * Use the EDB7312 Development Kit for all the EP73xx devices.

OVERVIEW (cont.)

The EP7311 is designed for low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V–3.3 V. The device has three basic power states: operating, idle and standby.

One of its notable features is MaverickKey unique IDs. These are factory programmed IDs in response to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music,

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminar y product i nformati on descr ibes product s which are in producti on, but f or which full char acterization dat a is not yet avai l able. Advance pr oduct inf ormation descri bes products which are in development and subject t o devel opment changes. Cirrus Logic, I nc. has made best ef forts to ensure that t he information contai ned i n this document is accurate and reli able. However, the inf ormation i s subj ect to change without not ice and is provi ded “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of t hird part ies. Thi s document is the property of Cirrus Lo gic, I nc. and impli es no lic ense under patent s, copyri ghts, t rademarks, or tr ade secrets. No part of this publicat ion may be copied, reproduced, s tored in a r etri eval system, or transmitted, in any form or by any means (elect roni c, mechanical, photographi c, or ot herwise) without the prior written consent of Cirr us Logi c, Inc. Items from any Cirrus Logi c websi te or disk may be print ed for use by the user. However, no part of t he print out or el ectronic fil es may be copi ed, reproduced, stored in a retri eval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior wri tten consent of Cirrus Logic, I nc.Furthermore, no part of this publ icati on may be used as a basis f or manufact ure or sale of any items without the prior wri tten consent of Cirrus Logic, I nc. The names of products of Cir rus Logic, Inc. or other vendor s and suppliers appearing in thi s document may be trademarks or servi ce marks of their respecti ve owners which may be registered in some jurisdi ctions. A list of Ci rrus Logic, Inc. tr ademarks and servi ce marks can be found at http:// www.cir rus.com.

traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs consist of two registers, one 32-bit series register and one random 128bit register that may be used by an OEM for an authentication mechanism.

Simply by adding desired memory and peripherals to the highly integrated EP7311 completes a low-power system solution. All necessary interface logic is integrated onchip.

EP7311

High-Performance, Low-Power System on Chip

Processor Core - ARM720T

The EP7311 incorporates an ARM 32-bit RISC microcontroller that controls a wide range of on-chip peripherals. The processor utilizes a three-stage pipeline consisting of fetch, decode and execute stages. Key features include:

• ARM (32-bit) and Thumb (16-bit compressed) instruction sets

• Enhanced MMU for Microsoft Windows CE and other operating systems

• 8 KB of 4-way set-associative cache.

• Translation Look Aside Buffers with 64 Translated

Entries

Power Management

The EP7311 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V–3.3 V allowing the device to achieve a performance level equivalent to 60 MIPS. The device has three basic power states:

• Operating — This state is the full performance state. All the clocks and peripheral logic are enabled.

• Idle — This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press.

• Standby — This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor.

Pin Mnemonic I/O Pin Description

BATOK I Battery ok input

nEXTPWR I

nPWRFL I Power fail sense input

nBATCHG I Battery changed sense input

Table A. Power Management Pin Assignments

External power supply sense input

MaverickKey™ Unique ID

MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure

Digital Music Initiative) or any other authentication mechanism.

Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7311 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7311 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances.

Memory Interfaces

There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burstmode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industryleading code density.

Pin Mnemonic I/O Pin Description

nCS[5:0] O Chip select out

A[27:0] O Address output

D[31:0] I/O Data I/O

nMOE/nSDCAS (Note) O ROM expansion OP enable

nMWE/nSDWE (Note) O ROM expansion write enable

HALFWORD O

WORD O Word access select output

WRITE/nSDRAS (Note) O Transfer direction

Table B. Static Memory Interface Pin Assignments

Note: Pins are multiplexed. See Table S on page 8 for more

information.

Halfword access select output

EP7311

High-Performance, Low-Power System on Chip

The second is the programmable 16- or 32-bit-wide SDRAM interface that allows direct connection of up to two banks of SDRAM, totaling 512 Mb. To assure the lowest possible power consumption, the EP7311 supports self-refresh SDRAMs, which are placed in a low-power state by the device when it enters the lowpower Standby State.

Pin Mnemonic I/O Pin Description

SDCLK O SDRAM clock output

SDCKE O SDRAM clock enable output

nSDCS[1:0] O SDRAM chip select out

WRITE/nSDRAS (Note 2) O SDRAM RAS signal output

nMOE/nSDCAS (Note 2) O SDRAM CAS control signal

nMWE/nSDWE (Note 2) O

A[27:15]/DRA[0:12] (Note 1) O SDRAM address

A[14:13]/DRA[12:14] O SDRAM internal bank select

PD[7:6]/SDQM[1:0] (Note 2) I/O SDRAM byte lane mask

SDQM[3:2] O SDRAM byte lane mask

D[31:0] I/O Data I/O

Table C. SDRAM Interface Pin Assignments

Note: 1. Pins A[27:13] map to DRA[0:14] respectively.

(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to

balance the load for large memory systems.

2. Pins are multiplexed. See Table S on page 8 for more information.

SDRAM write enable control signal

Digital Audio Capability

The EP7311 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor, and the availability of efficient C-compilers and other software development tools, ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7311

RX/TX signals to/from UART 1 to enable these signals to drive an infrared communication interface directly.

Pin Mnemonic I/O Pin Description

TXD[1] O UART 1 transmit

RXD[1] I UART 1 receive

CTS I UART 1 clear to send

DCD I UART 1 data carrier detect

DSR I UART 1 data set ready

TXD[2] O UART 2 transmit

RXD[2] I UART 2 receive

LEDDRV O Infrared LED drive output

PHDIN I Photo diode input

Table D. Universal Asynchronous Receiver/Transmitters Pin

Assignments

Multimedia Codec Port (MCP)

The Multimedia Codec Port provides access to an audio codec, a telecom codec, a touchscreen interface, four general purpose analog-to-digital converter inputs, and ten programmable digital I/O lines.

Pin Mnemonic I/O Pin Description

SIBCLK O Serial bit clock

SIBDOUT O Serial data out

SIBDIN I Serial data in

SIBSYNC O Sample clock

Table E. MCP Interface Pin Assignments

Note: See Table R on page 8 for information on pin

multiplexes.

Universal Asynchronous Receiver/Transmitters (UARTs)

The EP7311 includes two 16550-type UARTs for RS-232 serial communications, both of which have two 16-byte FIFOs for receiving and transmitting data. The UARTs support bit rates up to 115.2 kbps. An IrDA SIR protocol encoder/decoder can be optionally switched into the

EP7311

High-Performance, Low-Power System on Chip

CODEC Interface

The EP7311 includes an interface to telephony-type CODECs for easy integration into voice-over-IP and other voice communications systems. The CODEC interface is multiplexed to the same pins as the MCP and SSI2.

Pin Mnemonic I/O Pin Description

PCMCLK O Serial bit clock

PCMOUT O Serial data out

PCMIN I Serial data in

PCMSYNC O Frame sync

Table F. CODEC Interface Pin Assignments

Note: See Table R on page 8 for information on pin

multiplexes.

SSI2 Interface

An additional SPI/Microwire1-compatible interface is available for both master and slave mode communications. The SSI2 unit shares the same pins as the MCP and CODEC interfaces through a multiplexer.

• Synchronous clock speeds of up to 512 kHz

• Separate 16 entry TX and RX half-word wide FIFOs

• Half empty/full interrupts for FIFOs

• Separate RX and TX frame sync signals for

asymmetric traffic

Pin Mnemonic I/O Pin Description

SSICLK I/O Serial bit clock

SSITXDA O Serial data out

SSIRXDA I Serial data in

SSITXFR I/O Transmit frame sync

SSIRXFR I/O Receive frame sync

Table G. SSI2 Interface Pin Assignments

Note: See Table R on page 8 for information on pin

multiplexes.

Synchronous Serial Interface

• ADC (SSI) Interface: Master mode only; SPI and Microwire1-compatible (128 kbps operation)

• Selectable serial clock polarity

Pin Mnemonic I/O Pin Description

ADCLK O SSI1 ADC serial clock

ADCIN I SSI1 ADC serial input

ADCOUT O SSI1 ADC serial output

nADCCS O SSI1 ADC chip select

SMPCLK O SSI1 ADC sample clock

Table H. Serial Interface Pin Assignments

LCD Controller

A DMA address generator is provided that fetches video display data for the LCD controller from memory. The display frame buffer start address is programmable, allowing the LCD frame buffer to be in SDRAM, internal SRAM or external SRAM.

• Interfaces directly to a single-scan panel monochrome STN LCD

• Interfaces to a single-scan panel color STN LCD with minimal external glue logic

• Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments

• Video frame buffer size programmable up to 128 KB

• Bits per pixel of 1, 2, or 4 bits

Pin Mnemonic I/O Pin Description

CL1 O LCD line clock

CL2 O LCD pixel clock out

DD[3:0] O LCD serial display data bus

FRM O LCD frame synchronization pulse

M O LCD AC bias drive

Table I. LCD Interface Pin Assignments

EP7311

High-Performance, Low-Power System on Chip

64-Keypad Interface

Matrix keyboards and keypads can be easily read by the EP7311. A dedicated 8-bit column driver output generates strobes for each keyboard column signal. The pins of Port A, when configured as inputs, can be selectively OR’ed together to provide a keyboard interrupt that is capable of waking the system from a STANDBY or IDLE state.

• Column outputs can be individually set high with the remaining bits left at high-impedance

• Column outputs can be driven all-low, all-high, or allhigh-impedance

• Keyboard interrupt driven by OR'ing together all Port A bits

• Keyboard interrupt can be used to wake up the system

×8 keyboard matrix usable with no external logic,

• 8 extra keys can be added with minimal glue logic

Pin Mnemonic I/O Pin Description

COL[7:0] O Keyboard scanner column drive

Table J. Keypad Interface Pin Assignments

Interrupt Controller

When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. The EP7311 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources.

• Supports 22 interrupts from a variety of sources (such as UARTs, SSI1, and key matrix.)

• Routes interrupt sources to the ARM720T’s IRQ or FIQ (Fast IRQ) inputs

• Five dedicated off-chip interrupt lines operate as level sensitive interrupts

Pin Mnemonic I/O Pin Description

nEINT[2:1] I External interrupt

EINT[3] I External interrupt

nEXTFIQ I External Fast Interrupt input

nMEDCHG/nBROM (Note) I Media change interrupt input

Table K. Interrupt Controller Pin Assignments

Note: Pins are multiplexed. See Table S on page 8 for more

information.

Real-Time Clock

The EP7311 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt.

• Driven by an external 32.768 kHz crystal oscillator

Pin Mnemonic Pin Description

RTCIN Real-Time Clock Oscillator Input

RTCOUT Real-Time Clock Oscillator Output

VDDRTC Real-Time Clock Oscillator Power

VSSRTC Real-Time Clock Oscillator Ground

Table L. Real-Time Clock Pin Assignments

PLL and Clocking

• Processor and Peripheral Clocks operate from a single

3.6864 MHz crystal or external 13 MHz clock

• Programmable clock speeds allow the peripheral bus to run at 18 MHz when the processor is set to 18 MHz and at 36 MHz when the processor is set to 36, 49 or 74 MHz

Pin Mnemonic Pin Description

MOSCIN Main Oscillator Input

MOSCOUT Main Oscillator Output

VDDOSC Main Oscillator Power

VSSOSC Main Oscillator Ground

Table M. PLL and Clocking Pin Assignments

EP7311

High-Performance, Low-Power System on Chip

DC-to-DC converter interface (PWM)

• Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter

Pin Mnemonic I/O Pin Description

DRIVE[1:0] I/O PWM drive output

FB[1:0] I PWM feedback input

Table N. DC-to-DC Converter Interface Pin Assignments

Timers

• Internal (RTC) timer

• Two internal 16-bit programmable hardware count-

down timers

General Purpose Input/Output (GPIO)

• Three 8-bit and one 3-bit GPIO ports

• Supports scanning keyboard matrix

Hardware debug Interface

• Full JTAG boundary scan and Embedded ICE support

Pin Mnemonic I/O Pin Description

TCLK I JTAG clock

TDI I JTAG data input

TDO O JTAG data output

nTRST I JTAG async reset input

TMS I JTAG mode select

Table P. Hardware Debug Interface Pin Assignments

LED Flasher

A dedicated LED flasher module can be used to generate a low frequency signal on Port D pin 0 for the purpose of blinking an LED without CPU intervention. The LED flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicator on a portable phone or an appointment reminder on a PDA.

Pin Mnemonic I/O Pin Description

PA[7:0] I GPIO port A

PB[7:0] I GPIO port B

PD[0]/LEDFLSH (Note) I/O GPIO port D

PD[5:1] I/O GPIO port D

PD[7:6]/SDQM[1:0] (Note) I/O GPIO port D

PE[1:0]/BOOTSEL[1:0] (Note) I GPIO port E

PE[2]/CLKSEL (Note) I GPIO port E

Table O. General Purpose Input/Output Pin Assignments

Note: Pins are multiplexed. See Table S on page 8 for more

information.

• Software adjustable flash period and duty cycle

• Operates from 32 kHz RTC clock

• Will continue to flash in IDLE and STANDBY states

• 4 mA drive current

Pin Mnemonic I/O Pin Description

PD[0]/LEDFLSH (Note) O LED flasher driver

Table Q. LED Flasher Pin Assignments

Note: Pins are multiplexed. See Table S on page 8 for more

information.

Internal Boot ROM

The internal 128 byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH.

Packaging

The EP7311 is available in a 208-pin LQFP package, 256ball PBGA package or a 204-ball TFBGA package.

EP7311

High-Performance, Low-Power System on Chip

Pin Multiplexing

The following table shows the pin multiplexing of the MCP, SSI2 and the CODEC. The selection between SSI2 and the CODEC is controlled by the state of the SERSEL bit in SYSCON2. The choice between the SSI2, CODEC, and the MCP is controlled by the MCPSEL bit in SYSCON3 (see the EP73xx User’s Manual for more information).

Mnemonic

SSICLK I/O SIBCLK SSICLK PCMCLK

SSITXDA O SIBDOUT SSITXDA PCMOUT

SSIRXDA I SIBDIN SSIRXDA PCMIN

SSITXFR I/O SIBSYNC SSITXFR PCMSYNC

SSIRXFR I p/u SSIRXFR p/u

BUZ O

Table R. MCP/SSI2/CODEC Pin Multiplexing

I/O MCP SSI2 CODEC

The following table shows the pins that have been multiplexed in the EP7311.

Signal Block Signal Block

nMOE Static Memory nSDCAS SDRAM

nMWE Static Memory nSDWE SDRAM

WRITE Static Memory nSDRAS SDRAM

A[27:15] Static Memory DRA[0:12] SDRAM

A[14:13] Static Memory DRA[13:14] SDRAM

PD[7:6] GPIO SDQM[1:0] SDRAM

RUN

nMEDCHG

PD[0] GPIO LEDFLSH LED Flasher

PE[1:0] GPIO BOOTSEL[1:0]

PE[2] GPIO CLKSEL

System Configuration

Interrupt Controller

Table S. Pin Multiplexing

CLKEN

nBROM

System Configuration

Boot ROM select

System Configuration

System Design

EP7311

High-Performance, Low-Power System on Chip

As shown in system block diagram, simply adding desired memory and peripherals to the highly integrated

CRYSTAL

PC CARD

SOCKET

CONTROLLER

×16

SDRAM

×16

SDRAM

×16

FLASH

PC CARD

×16

SDRAM

×16

SDRAM

×16

FLASH

MOSCIN

RTCIN

nCS[4] PB0 EXPCLK

D[0-31]

A[0-27]

nMOE WRITE

SDRAS/

SDCAS

SDCS[0]

SDQM[0-3]

SDCS[1]

SDQM[0-3]

nCS[0] nCS[1]

EP7311 completes a low-power system solution. All necessary interface logic is integrated on-chip.

DD[0-3]

COL[0-7]

PA[0-7]

PB[0-7]

PD[0-7]

nPWRFL

BATOK

nEXTPWR

EP7311

nBATCHG

WAKEUP

DRIVE[0-1]

SSICLK

SSITXFR SSITXDA SSIRXDA SSIRXFR

CL1 CL2

FRM

PE[0-2]

nPOR

RUN

FB[0-1]

LCD

KEYBOARD

POWER

SUPPLY UNIT

AND

COMPARATORS

DC-TO-DC

CONVERTERS

CODEC/SSI2/

MCP

INPUT

BATTERY

×16

FLASH

EXTERNAL MEMORYMAPPED EXPANSION

×16

FLASH

BUFFERS

ADDITIONAL I/O

AND

LATCHES

Figure 1. A Maximum EP7311 Based System

Note: A system can only use one of the following peripheral

interfaces at any given time: SSI2,CODEC or MCP.

CS[n] WORD

nCS[2] nCS[3]

LEDFLSH

LEDDRV

PHDIN

RXD1/2

TXD1/2

DSR

CTS

DCD

ADCCLK nADCCS ADCOUT

ADCIN

SMPCLK

IR LED AND

PHOTODIODE

2× RS-232

TRANSCEIVERS

ADC

DIGITIZER

EP7311

High-Performance, Low-Power System on Chip

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

DC Core, PLL, and RTC Supply Voltage 2.9 V

DC I/O Supply Voltage (Pad Ring) 3.6 V

DC Pad Input Current

Storage Temperature, No Power –40

±10 mA/pin; ±100 mA cumulative

°C to +125°C

Recommended Operating Conditions

DC core, PLL, and RTC Supply Voltage 2.5 V

DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.6 V

DC Input / Output Voltage O–I/O supply voltage

Operating Temperature

± 0.2 V

Extended -20 Industrial -40

°C to +70°C; Commercial 0°C to +70°C;

°C to +85°C

DC Characteristics

All characteristics are specified at VDD = 2.5 V and VSS = 0 V over an operating temperature of 0°C to +70°C for all frequencies of operation. The current consumption figures relate to typical conditions at 2.5 V, 18.432 MHz operation

with the PLL switched “on.”

Symbol Parameter Min Typ Max Unit Conditions

VIH CMOS input high voltage

0.65

× V

DDIO

+ 0.3

DDIO

= 2.5 V

× V

VIL CMOS input low voltage -0.3

VT+

VT-

Vhst Schmitt trigger hysteresis 0.1 0.4 V VIL to VIH

VOH

VOL

IIN

IOZ

CIN Input capacitance 8 10.0 pF

Schmitt trigger positive going threshold

Schmitt trigger negative going threshold

CMOS output high voltage

Output drive 1

Output drive 2

CMOS output low voltage

Output drive 1

Output drive 2

Input leakage current

Bidirectional 3-state leakage

current

b c

1.6 (Typ) 2.0 V

0.8 1.2 (Typ) V

VDD – 0.2

2.5

25 100 µA

0.25

DDIO

0.3

0.5

1.0 µA

V V V

= 2.5 V

DDIO

IOH = 0.1 mA IOH = 4 mA IOH = 12 mA

IOL = –0.1 mA IOL = –4mA IOL = –12 mA

VIN = V

VOUT = V

or GND

High-Performance, Low-Power System on Chip

Symbol Parameter Min Typ Max Unit Conditions

COUT Output capacitance 8 10.0 pF

CI/O Transceiver capacitance 8 10.0 pF

EP7311

Only 32 kHz oscillator running, Cache disabled, all other I/O static, VIH = V

VIL = GND ± 0.1 V

IDD

standby

Standby current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V

TBD TBD

300 µA

Both oscillators running, CPU static, Cache disabled, LCD refresh active, VIH = V

VIL = GND ± 0.1 V

IDD

idle

Idle current consumption Core, Osc, RTC @2.5 V I/O @ 2.5 V

TBD TBD

4.2 mA

At 13 MHz

IDD

operatin

Operating current consumption Core, Osc, RTC @2.5 V I/O @ 3.3 V

TBD TBD

All system active, running typical program, cache disabled, and LCD inactive

Minimum standby voltage for

DDstandby

Standby supply voltage TBD V

state retention and RTC operation only

a. See Table T on page 29.

b. Assumes buffer has no pull-up or pull-down resistors.

c. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven.

Note: 1) All power dissipation values can be derived from taking the particular IDD current and multiplying by 2.5 V.

2) The RTC of the EP7311 should be brought up at room temperature. This is required because the RTC OSC will NOT function properly if it is brought up at –40

°C. Once operational, it will continue to operate down to –20°C extended and 0°C

commercial.

3) A typical design will provide 3.3 V to the I/O supply (i.e., V

IO), and 2.5 V to the remaining logic. This is to allow the I/O to be

compatible with 3.3 V powered external logic (i.e., 3.3 V SDRAMs).

4) Pull-up current = 50 µA typical at V

= 3.3 V.

± 0.1 V,

EP7311

Clock

High to Low

High/Low to High

Bus Change

Bus Valid

Undefined/Invalid

Valid Bus to Tristate

Bus/Signal Omission

High-Performance, Low-Power System on Chip

Timings

Timing Diagram Conventions

This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated.

Timing Conditions

Unless specified otherwise, the following conditions are true for all timing measurements. All characteristics are specified at V

marked with a # will be significantly different for 13 MHz mode because the EXPCLK is provided as an input rather than generated internally. These timings are estimated at present. The timing values are referenced to 1/2 V

= 2.3 - 2.7 V and VSS = 0 V over an operating temperature of 0°C to +70°C. Those characteristics

EP7311

High-Performance, Low-Power System on Chip

SDRAM Interface

Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the

values for the timings of each of the SDRAM modes.

Parameter Symbol Min Typ Max Unit

SDCLK rising edge to SDCS assert delay time

SDCLK rising edge to SDCS deassert delay time

SDCLK rising edge to SDRAS assert delay time

SDCLK rising edge to SDRAS deassert delay time

SDCLK rising edge to SDRAS invalid delay time

SDCLK rising edge to SDCAS assert delay time

SDCLK rising edge to SDCAS deassert delay time

SDCLK rising edge to ADDR transition time

SDCLK rising edge to ADDR invalid delay time

SDCLK rising edge to SDMWE assert delay time

SDCLK rising edge to SDMWE deassert delay time

DATA transition to SDCLK rising edge time

SDCLK rising edge to DATA transition hold time

SDCLK rising edge to DATA transition delay time

CSa

CSd

RAa

RAd

RAnv

CAa

CAd

ADv

ADx

MWa

MWd

DAs

DAh

DAd

TBD 0 TBD ns

TBD - TBD ns

EP7311

High-Performance, Low-Power System on Chip

SDRAM Load Mode Register Cycle

SDCLK

SDCS

SDRAS

SDCAS

ADDR

DATA

SDQM

SDMWE

MWa

CSa

RAa

CAa

ADv

CSd

RAd

CAd

MWd

ADx

Figure 2. SDRAM Load Mode Register Cycle Timing Measurement

SDRAM Burst Read Cycle

SDCLK

EP7311

High-Performance, Low-Power System on Chip

SDCS

SDRAS

SDCAS

ADDR

DATA

SDQM

[0:3]

SDMWE

CSd

RAd

CSa

RAa

ADv

CSa

CSd

CAa

CAd

ADv

ADRAS ADCAS

DAs

D1 D4D3D2

DAh

DAs

DAh

DAs

DAh

DAs

DAh

RAnv

Figure 3. SDRAM Burst Read Cycle Timing Measurement

Note: 1. Timings are shown with CAS latency = 2

2. Depending on clock line loading, SDCLK may be phase shifted to the right.

+ 35 hidden pages