Cirrus Logic EP7311 User Manual
FEATURES
LCD
Controller
Boot
ROM
MaverickKey
TM
ARM7TDMI CPU Core
MMU
8 KB
Cache
Write
Buffer
Internal Data Bus
EPB Bus
Memory Controller
SDRAM I/FSRAM I/F
On-chip SRAM
48 KB
ICE-JTAG
Clocks &
Timers
Keypad&
Touch
Screen I/F
Interrupts,
PWM & GPIO
Bus
Bridge
(2) UARTs
w/ IrDA
Power
Management
Serial
Interface
Multimedia
Codec Port
ARM720T
MEMORY AND STORAGE
USER INTERFACE
SERIAL PORTS
ARM720T Processor
— ARM7TDMI CPU
— 8 KB of four-way set-associative cache
— MMU with 64-entry TLB
— Thumb code support enabled
Ultra low power
— 90 mW at 74 MHz typical
— 30 mW at 18 MHz typical
— 10 mW in the Idle State
— <1 mW in the Standby State
48 KB of on-chip SRAM
™
MaverickKey
— 32-bit unique ID can be used for SDMI compliance
— 128-bit random ID
Dynamically programmable clock speeds of
18, 36, 49, and 74 MHz
IDs
EP7311 Data Sheet
High-performance,
Low-power, System-on-chip
with SDRAM & Enhanced
Digital Audio Interface
OVERVIEW
The Maverick™ EP7311 is designed for ultra-low-power
applications such as PDAs, smart cellular phones, and
industrial hand held information appliances. The core-logic
functionality of the device is built around an ARM720T
processor with 8 KB of four-way set-associative unified cache
and a write buffer. Incorporated into the ARM720T is an
enhanced memory management unit (MMU) which allows for
support of sophisticated operating systems like Linux
®
.
BLOCK DIAGRAM
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) MAR ‘11
(cont.)
(cont.)
DS506F2
EP7311
High-Performance, Low-Power System on Chip
FEATURES (cont)
LCD controller
— Interfaces directly to a single-scan panel monochrome
STN LCD
— Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
Full JTAG boundary scan and Embedded ICE
support
Integrated Peripheral Interfaces
— 32-bit SDRAM Interface up to 2 external banks
— 8/32/16-bit SRAM/FLASH/ROM Interface
— Multimedia Codec Port
— Two Synchronous Serial Interfaces (SSI1, SSI2)
— CODEC Sound Interface
—8×8 Keypad Scanner
— 27 General Purpose Input/Output pins
— Dedicated LED flasher pin from the RTC
Internal Peripherals
OVERVIEW (cont.)
The EP7311 is designed for low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V. The device has three basic power states:
operating, idle and standby.
— Two 16550 compatible UARTs
— IrDA Interface
— Two PWM Interfaces
— Real-time Clock
— Two general purpose 16-bit timers
— Interrupt Controller
— Boot ROM
Package
—256-Ball PBGA
The fully static EP7311 is optimized for low power
dissipation and is fabricated on a 0.25 micron CMOS
process
Development Kits
— EDB7312: Development Kit with color STN LCD on
board.
Note: * Use the EDB7312 Development Kit for all the EP73xx
devices.
One of its notable features is MaverickKey unique IDs. These
are factory programmed IDs in response to the growing
concern over secure web content and commerce. With Internet
security playing an important role in the delivery of digital
media such as books or music, traditional software methods are
quickly becoming unreliable. The MaverickKey unique IDs
consist of two registers, one 32-bit series register and one
random 128-bit register that may be used by an OEM for an
authentication mechanism.
Simply by adding desired memory and peripherals to the
highly integrated EP7311 completes a low-power system
solution. All necessary interface logic is integrated on-chip.
2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
Table of Contents
FEATURES.........................................................................................................................................................2
OVERVIEW..................................................................................................................................................................2
Processor Core - ARM720T ..................................................................................................................................6
Power Management ..............................................................................................................................................6
MaverickKey™ Unique ID .....................................................................................................................................6
Memory Interfaces .............................. ... .... ... ... ... ... .... ... .......................................... ... ... .... .....................................6
Digital Audio Capability ... .......................................... ... ... ... .... ... ............................................................................7
Universal Asynchronous Receiver/Transmitters (UARTs) .....................................................................................7
Multimedia Codec Port (MCP) ...............................................................................................................................7
CODEC Interface ..... ... .... ... ... ... .... ... ... ... .... ... .......................................... ... ... ... .... ... ... ... .... .....................................8
SSI2 Interface ........................................................................................................................................................8
Synchronous Serial Interface ................................................................................................................................8
LCD Controller .......................................................................................................................................................8
Interrupt Controller ................................................................................................................................................9
Real-Time Clock ....................................................................................................................................................9
PLL and Clocking ..................................................................................................................................................9
DC-to-DC converter interface (PWM) ..................................................................................................................10
Timers .................................................................................................................................................................10
General Purpose Input/Output (GPIO) ................................................................................................................10
Hardware debug Interface ...................................................................................................................................10
Internal Boot ROM ........................... ... ... .... ... .......................................... ... ... ... .... ... .............................................10
Packaging ..................................... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ... ....... .............................................10
Pin Multiplexing ...................................................................................................................................................11
System Design ....................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................13
Absolute Maximum Ratings .................................................................................................................................13
Recommended Operating Conditions .................................................................................................................13
DC Characteristics ....................................... ... .......................................... ... ... .... ... ... ..........................................13
Timings ........................................................................................... .............. ............................ ..........15
Timing Diagram Conventions ...................... .......................................... .... ... ... ... .... ... ... ... ... .......................15
Timing Conditions ........................ .... ... ... ... .......................................... ... .... ... ... ... .......................................15
SDRAM Interface ..... ... .... ... .......................................... ... ... .... ... ... .......................................................................16
SDRAM Load Mode Register Cycle ..........................................................................................................17
SDRAM Burst Read Cycle ........... .... ... ... ... ... .... ... ... ... .... ... ... .......................................... ... ... .... ...................18
SDRAM Burst Write Cycle ........... .... ... .......................................... ... ..........................................................19
SDRAM Refresh Cycle ....................................................... ... .......................................... ... .......................20
Static Memory ......................................................................................................................................................21
Static Memory Single Read Cycle .............................................................................................................22
Static Memory Single Write Cycle ..............................................................................................................23
Static Memory Burst Read Cycle ...............................................................................................................24
Static Memory Burst Write Cycle ...............................................................................................................25
SSI1 Interface ......................................................................................................................................................26
SSI2 Interface ......................................................................................................................................................27
LCD Interface ......................................................................................................................................................28
JTAG Interface ................................ ... ... .......................................... .... ... ... ... ... ....................................................29
Packages ...................................................................................................................... .............. ........30
256-Ball PBGA Package Characteristics ............................................................................................................30
256-Ball PBGA Package Specifications ....................................................................................................30
256-Ball PBGA Pinout (Top View) .............................................................................................................31
256-Ball PBGA Ball Listing ........................................................................................................................32
JTAG Boundary Scan Signal Ordering ...................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ...................................35
DS506F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 3
EP7311
High-Performance, Low-Power System on Chip
CONVENTIONS .................................................................................................................................40
Acronyms and Abbreviations .............................................................................................................................. 40
Units of Measurement ......................................................................................................................................... 40
General Conventions .......................................................... ... ... .... ... ... ... .... ... ... ... ... ............................................. 41
Pin Description Conventions ............................................................................................................................... 41
.................................................................................................................................................................. 41
Ordering Information .......................................................................................................................42
Environmental, Manufacturing, & Handling Information .............................................................42
Revision History ..............................................................................................................................42
4 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
List of Figures
Figure 1. A Maximum EP7311 Based System ....... ... ... ... .... ... ... ... .... .......................................... ... ... .............................12
Figure 2. Legend for Timing Diagrams .........................................................................................................................15
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement ..................... ................................ .......................17
Figure 4. SDRAM Burst Read Cycle Timing Measurement ..........................................................................................18
Figure 5. SDRAM Burst Write Cycle Timing Measurement ..........................................................................................19
Figure 6. SDRAM Refresh Cycle Timing Measurement ......................................... ... .... ... .............................................20
Figure 7. Static Memory Single Read Cycle Timing Measurement ...............................................................................22
Figure 8. Static Memory Single Write Cycle Timing Measurement .................. ................................... ..........................23
Figure 9. Static Memory Burst Read Cycle Timing Measurement ................................................................................24
Figure 10. Static Memory Burst Write Cycle Timing Measurement ..............................................................................25
Figure 11. SSI1 Interface Timing Measurement ...........................................................................................................26
Figure 12. SSI2 Interface Timing Measurement ...........................................................................................................27
Figure 13. LCD Controller Timing Measurement ..........................................................................................................28
Figure 14. JTAG Timing Measurement ........................ .............................................................. ...................................29
Figure 15. 256-Ball PBGA Package ..............................................................................................................................30
List of Tables
Table A. Power Management Pin Assignments ..............................................................................................................6
Table B. Static Memory Interface Pin Assignments ........................................................................................................6
Table C. SDRAM Interface Pin Assignments ..................................................................................................................7
Table D. Universal Asynchronous Receiver/Transmitters Pin Assignments ...................................................................7
Table E. MCP Interface Pin Assignments .......................................................................................................................7
Table F. CODEC Interface Pin Assignments ..................................................................................................................8
Table G. SSI2 Interface Pin Assignments .......................................................................................................................8
Table H. Serial Interface Pin Assignments ............................ ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ..................................8
Table I. LCD Interface Pin Assignments ............................................. ... ... ......................................................................8
Table J. Keypad Interface Pin Assignments ...................................................................................................................9
Table K. Interrupt Controller Pin Assignments ................................................................................................................9
Table L. Real-Time Clock Pin Assignments ....................................................................................................................9
Table M. PLL and Clocking Pin Assignments .................................................................................................................9
Table N. DC-to-DC Converter Interface Pin Assignments ............................................................................................10
Table O. General Purpose Input/Output Pin Assignments ...........................................................................................10
Table P. Hardware Debug Interface Pin Assignments ..................................................................................................10
Table Q. LED Flasher Pin Assignments .......................................................................................................................10
Table R. MCP/SSI2/CODEC Pin Multiplexing ...............................................................................................................11
Table S. Pin Multiplexing ..............................................................................................................................................11
Table T. 256-Ball PBGA Ball Listing ............ .......................................... ... .... ... ... ... ... .... ... ... ... .......................................32
Table U. JTAG Boundary Scan Signal Ordering .......... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ..........................35
Table V. Acronyms and Abbreviations ..........................................................................................................................40
Table W. Unit of Measurement .................... .......................................... ... .... ... ... ... ... .... ... ... ..........................................40
Table X. Pin Description Conventions ..........................................................................................................................41
DS506F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 5
EP7311
High-Performance, Low-Power System on Chip
Processor Core - ARM720T
The EP7311 incorporates an ARM 32-bit RISC
microcontroller that controls a wide range of on-chip
peripherals. The processor utilizes a three-stage pipeline
consisting of fetch, decode and execute stages. Key features
include:
• ARM (32-bit) and Thumb (16-bit compressed) instruction
sets
• Enhanced MMU for Microsoft Windows CE and other
operating systems
• 8 KB of 4-way set-associative cache.
• Translation Look Aside Buffers with 64 Translated Entries
Power Management
The EP7311 is designed for ultra-low-power operation. Its core
operates at only 2.5 V, while its I/O has an operation range of
2.5 V–3.3 V allowing the device to achieve a performance
level equivalent to 60 MIPS. The device has three basic power
states:
• Operating — This state is the full performance state.
All the clocks and peripheral logic are enabled.
• Idle — This state is the same as the Operating State,
except the CPU clock is halted while waiting for an
event such as a key press.
• Standby — This state is equivalent to the computer
being switched off (no display), and the main
oscillator shut down. An event such as a key press
can wake-up the processor.
Pin Mnemonic I/O Pin Description
BATOK I Battery ok input
nEXTPWR I
nPWRFL I Power fail sense input
nBATCHG I Battery changed sense input
External power supply sense
input
Both a specific 32-bit ID as well as a 128-bit random ID is
programmed into the EP7311 through the use of laser probing
technology. These IDs can then be used to match secure
copyrighted content with the ID of the target device the
EP7311 is powering, and then deliver the copyrighted
information over a secure connection. In addition, secure
transactions can benefit by also matching device IDs to server
IDs. MaverickKey IDs provide a level of hardware security
required for today’s Internet appliances.
Memory Interfaces
There are two main external memory interfaces. The first one
is the ROM/SRAM/FLASH-style interface that has
programmable wait-state timings and includes burst-mode
capability, with six chip selects decoding six 256 MB sections
of addressable space. For maximum flexibility, each bank can
be specified to be 8-, 16-, or 32-bits wide. This allows the use
of 8-bit-wide boot ROM options to minimize overall system
cost. The on-chip boot ROM can be used in product
manufacturing to serially download system code into system
FLASH memory. To further minimize system memory
requirements and cost, the ARM Thumb instruction set is
supported, providing for the use of high-speed 32-bit
operations in 16-bit op-codes and yielding industry-leading
code density.
Pin Mnemonic I/O Pin Description
nCS[5:0] O Chip select out
A[27:0] O Address output
D[31:0] I/O Data I/O
nMOE/nSDCAS (Note) O ROM expansion OP enable
nMWE/nSDWE (Note) O ROM expansion write enable
HALFWORD O
WORD O Word access select output
WRITE/nSDRAS (Note) O Transfer direction
Table B. Static Memory Interface Pin Assignments
Halfword access select
output
Table A. Power Management Pin Assignments
Note: Pins are multiplexed. See Table S on page 11 for more
information.
MaverickKey™ Unique ID
MaverickKey unique hardware programmed IDs are a solution
to the growing concern over secure web content and
commerce. With Internet security playing an important role in
the delivery of digital media such as books or music,
traditional software methods are quickly becoming unreliable.
The MaverickKey unique IDs provide OEMs with a method of
utilizing specific hardware IDs such as those assigned for
SDMI (Secure Digital Music Initiative) or any other
authentication mechanism.
6 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
The second is the programmable 16- or 32-bit-wide SDRAM
interface that allows direct connection of up to two banks of
SDRAM, totaling 512 Mb. To assure the lowest possible power
consumption, the EP7311 supports self-refresh SDRAMs,
which are placed in a low-power state by the device when it
enters the low-power Standby State.
Pin Mnemonic I/O Pin Description
SDCLK O SDRAM clock output
SDCKE O SDRAM clock enable output
nSDCS[1:0] O SDRAM chip select out
WRITE/nSDRAS (Note 2) O SDRAM RAS signal output
nMOE/nSDCAS (Note 2) O SDRAM CAS control signal
nMWE/nSDWE (Note 2) O
A[27:15]/DRA[0:12] (Note 1) O SDRAM address
A[14:13]/DRA[12:14] O SDRAM internal bank select
PD[7:6]/SDQM[1:0] (Note 2) I/O SDRAM byte lane mask
SDQM[3:2] O SDRAM byte lane mask
D[31:0] I/O Data I/O
Table C. SDRAM Interface Pin Assignments
SDRAM write enable control
signal
UART 1 to enable these signals to drive an infrared
communication interface directly.
Pin Mnemonic I/O Pin Description
TXD[1] O UART 1 transmit
RXD[1] I UART 1 receive
CTS I UART 1 clear to send
DCD I UART 1 data carrier detect
DSR I UART 1 data set ready
TXD[2] O UART 2 transmit
RXD[2] I UART 2 receive
LEDDRV O Infrared LED drive output
PHDIN I Photo diode input
Table D. Universal Asynchronous Receiver/Transmitters Pin
Assignments
Multimedia Codec Port (MCP)
The Multimedia Codec Port provides access to an audio codec,
a telecom codec, a touchscreen interface, four general purpose
analog-to-digital converter inputs, and ten programmable
digital I/O lines.
Note: 1. Pins A[27:13] map to DRA[0:14] respectively.
(i.e. A[27}/DRA[0}, A[26}/DRA[1], etc.) This is to
balance the load for large memory systems.
2. Pins are multiplexed. See Table S on page 11 for
more information.
Digital Audio Capability
The EP7311 uses its powerful 32-bit RISC processing engine
to implement audio decompression algorithms in software. The
nature of the on-board RISC processor, and the availability of
efficient C-compilers and other software development tools,
ensures that a wide range of audio decompression algorithms
can easily be ported to and run on the EP7311
Universal Asynchronous Receiver/T ransmitters (UARTs)
The EP7311 includes two 16550-type UARTs for RS-232
serial communications, both of which have two 16-byte FIFOs
for receiving and transmitting data. The UARTs support bit
rates up to 115.2 kbps. An IrDA SIR protocol encoder/ decoder
can be optionally switched into the RX/TX signals to/from
Pin Mnemonic I/O Pin Description
SIBCLK O Serial bit clock
SIBDOUT O Serial data out
SIBDIN I Serial data in
SIBSYNC O Sample clock
Table E. MCP Interface Pin Assignments
Note: See Table R on page 11 for information on pin
multiplexes.
DS506F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 7
EP7311
High-Performance, Low-Power System on Chip
CODEC Interface
The EP7311 includes an interface to telephony-type CODECs
for easy integration into voice-over-IP and other voice
communications systems. The CODEC interface is
multiplexed to the same pins as the MCP and SSI2.
Pin Mnemonic I/O Pin Description
PCMCLK O Serial bit clock
PCMOUT O Serial data out
PCMIN I Serial data in
PCMSYNC O Frame sync
Table F. CODEC Interface Pin Assignments
Note: See Table R on page 11 for information on pin
multiplexes.
SSI2 Interface
An additional SPI/Microwire1-compatible interface is
available for both master and slave mode communications. The
SSI2 unit shares the same pins as the MCP and CODEC
interfaces through a multiplexer.
Synchronous Serial Interface
• ADC (SSI) Interface: Master mode only; SPI and
Microwire1-compatible (128 kbps operation)
• Selectable serial clock polarity
Pin Mnemonic I/O Pin Description
ADCLK O SSI1 ADC serial clock
ADCIN I SSI1 ADC serial input
ADCOUT O SSI1 ADC serial output
nADCCS O SSI1 ADC chip select
SMPCLK O SSI1 ADC sample clock
Table H. Serial Interface Pin Assignments
LCD Controller
A DMA address generator is provided that fetches video
display data for the LCD controller from memory. The display
frame buffer start address is programmable, allowing the LCD
frame buffer to be in SDRAM, internal SRAM or external
SRAM.
• Synchronous clock speeds of up to 512 kHz
• Separate 16 entry TX and RX half-word wide FIFOs
• Half empty/full interrupts for FIFOs
• Separate RX and TX frame sync signals for asymmetric
traffic
Pin Mnemonic I/O Pin Description
SSICLK I/O Serial bit clock
SSITXDA O Serial data out
SSIRXDA I Serial data in
SSITXFR I/O Transmit frame sync
SSIRXFR I/O Receive frame sync
Table G. SSI2 Interface Pin Assignments
Note: See Table R on page 11 for information on pin
multiplexes.
• Interfaces directly to a single-scan panel monochrome STN
LCD
• Interfaces to a single-scan panel color STN LCD with
minimal external glue logic
• Panel width size is programmable from 32 to 1024 pixels in
16-pixel increments
• Video frame buffer size programmable up to
128 KB
• Bits per pixel of 1, 2, or 4 bits
Pin Mnemonic I/O Pin Description
CL1 O LCD line clock
CL2 O LCD pixel clock out
DD[3:0] O LCD serial display data bus
FRM O LCD frame synchronization pulse
M O LCD AC bias drive
Table I. LCD Interface Pin Assignments
8 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
64-Keypad Interface
Matrix keyboards and keypads can be easily read by the
EP7311. A dedicated 8-bit column driver output generates
strobes for each keyboard column signal. The pins of Port A,
when configured as inputs, can be selectively OR'ed together
to provide a keyboard interrupt that is capable of waking the
system from a STANDBY or IDLE state.
• Column outputs can be individually set high with the
remaining bits left at high-impedance
• Column outputs can be driven all-low, all-high, or all-highimpedance
• Keyboard interrupt driven by OR'ing together all Port A
bits
• Keyboard interrupt can be used to wake up the system
•88 keyboard matrix usable with no external logic, extra
keys can be added with minimal glue logic
Pin Mnemonic I/O Pin Description
COL[7:0] O
Table J. Keypad Interface Pin Assignments
Keyboard scanner column
drive
Interrupt Controller
When unexpected events arise during the execution of a
program (i.e., interrupt or memory fault) an exception is
usually generated. When these exceptions occur at the same
time, a fixed priority system determines the order in which
they are handled. The EP7311 interrupt controller has two
interrupt types: interrupt request (IRQ) and fast interrupt
request (FIQ). The interrupt controller has the ability to control
interrupts from 22 different FIQ and IRQ sources.
• Supports 22 interrupts from a variety of sources (such as
UARTs, SSI1, and key matrix.)
• Routes interrupt sources to the ARM720T’s IRQ or FIQ
(Fast IRQ) inputs
• Five dedicated off-chip interrupt lines operate as level
sensitive interrupts
.
Pin Mnemonic I/O Pin Description
nEINT[2:1] I External interrupt
EINT[3] I External interrupt
nEXTFIQ I External Fast Interrupt input
nMEDCHG/nBROM (Note) I Media change interrupt input
Table K. Interrupt Controller Pin Assignments
Note: Pins are multiplexed. See Table S on page 11 for more
information.
Real-Time Clock
The EP7311 contains a 32-bit Real Time Clock (RTC) that can
be written to and read from in the same manner as the timer
counters. It also contains a 32-bit output match register which
can be programmed to generate an interrupt.
• Driven by an external 32.768 kHz crystal oscillator
Pin Mnemonic Pin Description
RTCIN Real-Time Clock Oscillator Input
RTCOUT Real-Time Clock Oscillator Output
VDDRTC Real-Time Clock Oscillator Power
VSSRTC Real-Time Clock Oscillator Ground
Table L. Real-Time Clock Pin Assignments
PLL and Clocking
• Processor and Peripheral Clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
• Programmable clock speeds allow the peripheral bus to run
at 18 MHz when the processor is set to 18 MHz and at
36 MHz when the processor is set to 36, 49 or 74 MHz
Pin Mnemonic Pin Description
MOSCIN Main Oscillator Input
MOSCOUT Main Oscillator Output
VDDOSC Main Oscillator Power
VSSOSC Main Oscillator Ground
Table M. PLL and Clocking Pin Assignments
DS506F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 9
EP7311
High-Performance, Low-Power System on Chip
DC-to-DC converter interface (PWM)
• Provides two 96 kHz clock outputs with programmable
duty ratio (from 1-in-16 to 15-in-16) that can be used to
drive a positive or negative DC to DC converter
Pin Mnemonic I/O Pin Description
DRIVE[1:0] I/O PWM drive output
FB[1:0] I PWM feedback input
Table N. DC-to-DC Converter Interface Pin Assignments
Timers
• Internal (RTC) timer
• Two internal 16-bit programmable hardware count-down
timers
General Purpose Input/Output (GPIO)
• Three 8-bit and one 3-bit GPIO ports
• Supports scanning keyboard matrix
Pin Mnemonic I/O Pin Description
PA[7:0] I/O GPIO port A
PB[7:0] I/O GPIO port B
PD[0]/LEDFLSH (Note) I/O GPIO port D
PD[5:1] I/O GPIO port D
PD[7:6]/SDQM[1:0] (Note) I/O GPIO port D
PE[1:0]/BOOTSEL[1:0] (Note) I/O GPIO port E
PE[2]/CLKSEL (Note) I/O GPIO port E
Table O. General Purpose Input/Output Pin Assignments
Note: Pins are multiplexed. See T able S on page 11 for more
information.
Hardware debug Interface
• Full JTAG boundary scan and Embedded ICE support
Pin Mnemonic I/O Pin Description
TCLK I JTAG clock
TDI I JTAG data input
TDO O JTAG data output
nTRST I JTAG async reset input
TMS I JTAG mode select
Table P. Hardware Debug Interface Pin Assignments
LED Flasher
A dedicated LED flasher module can be used to generate a low
frequency signal on Port D pin 0 for the purpose of blinking an
LED without CPU intervention. The LED flasher feature is
ideal as a visual annunciator in battery powered applications,
such as a voice mail indicator on a portable phone or an
appointment reminder on a PDA.
• Software adjustable flash period and duty cycle
• Operates from 32 kHz RTC clock
• Will continue to flash in IDLE and STANDBY states
• 4 mA drive current
Pin Mnemonic I/O Pin Description
PD[0]/LEDFLSH (Note) O LED flasher driver
Table Q. LED Flasher Pin Assignments
Note: Pins are multiplexed. See Table S on page 11 for more
information.
Internal Boot ROM
The internal 128 byte Boot ROM facilitates download of saved
code to the on-board SRAM/FLASH.
Packaging
The EP7311 is available in a 208-pin LQFP package, 256-ball
PBGA package or a 204-ball TFBGA package.
10 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) DS506F2
EP7311
High-Performance, Low-Power System on Chip
Pin Multiplexing
The following table shows the pin multiplexing of the MCP,
SSI2 and the CODEC. The selection between SSI2 and the
CODEC is controlled by the state of the SERSEL bit in
SYSCON2. The choice between the SSI2, CODEC, and the
MCP is controlled by the MCPSEL bit in SYSCON3 (see the
EP73xx User’s Manual for more information).
Pin
Mnemonic
SSICLK I/O SIBCLK SSICLK PCMCLK
SSITXDA O SIBDOUT SSITXDA PCMOUT
SSIRXDA I SIBDIN SSIRXDA PCMIN
SSITXFR I/O SIBSYNC SSITXFR PCMSYNC
SSIRXFR I p/u SSIRXFR p/u
BUZ O
Table R. MCP/SSI2/CODEC Pin Multiplexing
I/O MCP SSI2 CODEC
The following table shows the pins that have been multiplexed
in the EP7311.
Signal Block Signal Block
nMOE Static Memory nSDCAS SDRAM
nMWE Static Memory nSDWE SDRAM
WRITE Static Memory nSDRAS SDRAM
A[27:15] Static Memory DRA[0:12] SDRAM
A[14:13] Static Memory DRA[13:14] SDRAM
PD[7:6] GPIO SDQM[1:0] SDRAM
RUN
nMEDCHG
PD[0] GPIO LEDFLSH LED Flasher
PE[1:0] GPIO BOOTSEL[1:0]
PE[2] GPIO CLKSEL
System
Configuration
Interrupt
Controller
Table S. Pin Multiplexing
CLKEN
nBROM
System
Configuration
Boot ROM
select
System
Configuration
System
Configuration
DS506F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 11
EP7311
LCD
KEYBOARD
BATTER Y
DC-TO-DC
CONVERTERS
ADC
DIGITIZER
IR LED AND
PHOTODIODE
2RS-232
TRANSCEIVERS
ADDITIONAL I/O
PC CARD
CONTROLLER
PC CARD
SOCKET
nCS[4]
PB0
EXPCLK
DD[0-3]
CL1
CL2
FRM
M
D[0-31]
A[0-27]
COL[0-7]
PA[0-7]
DC
INPUT
nMOE
WRITE
PB[0-7]
PD[0-7]
PE[0-2]
nPOR
nPWRFL
BATOK
nEXTPWR
nBATCHG
RUN
WAKEUP
nCS[0]
nCS[1]
DRIVE[0-1]
FB[0-1]
EP7311
ADCCLK
nADCCS
ADCOUT
ADCIN
SMPCLK
LEDDRV
PHDIN
RXD1/2
TXD1/2
DSR
CTS
DCD
CS[n]
WORD
nCS[2]
nCS[3]
16
FLASH
16
FLASH
6
FLASH
EXTERNAL MEMORY MAPPED EXPANSION
BUFFERS
BUFFERS
AND
LATCHES
16
FLASH
POWER
SUPPLY UNIT
AND
COMPARATORS
CRYSTAL
CODEC/SSI2/
MCP
SSICLK
SSITXFR
SSITXDA
SSIRXDA
SSIRXFR
RTCIN
LEDFLSH
CRYSTAL
MOSCIN
16
SDRAM
16
SDRAM
6
SDRAM
16
SDRAM
SDCS[1]
SDQM[0-3]
SDCS[0]
SDQM[0-3]
SDRAS/
SDCAS
High-Performance, Low-Power System on Chip
System Design
As shown in system block diagram, simply adding desired
memory and peripherals to the highly integrated EP7311
completes a low-power system solution. All necessary
interface logic is integrated on-chip.
Note: A system can only use one of the following peripheral
interfaces at any given time: SSI2,CODEC or MCP.
12 Copyright Cirrus Logic, Inc. 2011
Figure 1. A Maximum EP7311 Based System
(All Rights Reserved) DS506F2
High-Performance, Low-Power System on Chip
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
DC Core, PLL, and RTC Supply Voltage 2.9 V
DC I/O Supply Voltage (Pad Ring) 3.6 V
DC Pad Input Current 10 mA/pin; 100 mA cumulative
Storage Temperature, No Power –40C to +125C
Recommended Operating Conditions
DC core, PLL, and RTC Supply Voltage 2.5 V 0.2 V
DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.5 V
DC Input / Output Voltage O–I/O supply voltage
EP7311
Operating Temperature
Extended -20C to +70C; Commercial 0C to +70C;
Industrial -40C to +85C
DC Characteristics
All characteristics are specified at V
DDCORE
for all frequencies of operation. The current consumption figures have test conditions specified per parameter.”
Symbol Parameter Min T yp Max Unit Conditions
VIH CMOS input high voltage
VIL CMOS input low voltage
VT+
VT-
Vhst Schmitt trigger hysteresis 0.1 - 0.4 V VIL to VIH
VOH
Schmitt trigger positive going
threshold
Schmitt trigger negative going
threshold
CMOS output high voltage
Output drive 1
Output drive 2
a
a
a
= 2.5 V , V
0.65 V
DDIO
0.3
V
SS
--2.1V
0.8 - - V
VDD – 0.2
2.5
2.5
= 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C
DDIO
+ 0.3
-
-
-
-
-
V
DDIO
0.25 V
-
-
-
DDIO
V
V
V
V
V
V
= 2.5 V
DDIO
= 2.5 V
V
DDIO
IOH = 0.1 mA
IOH = 4 mA
IOH = 12 mA
CMOS output low voltage
VOL
IIN Input leakage current - - 1.0 µA
IOZ
CIN Input capacitance 8 - 10.0 pF
COUT Output capacitance 8 - 10.0 pF
Output drive 1
Output drive 2
Bidirectional 3-state leakage
current
a
a
b c
a
-
-
-
25 - 100 µA
-
-
-
0.3
0.5
0.5
DS506F2 Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved) 13
V
V
V
IOL = –0.1 mA
IOL = –4 mA
IOL = –12 mA
VIN = V
VOUT = V
or GND
DD
DD
or GND
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