Cirrus Logic EP7209 Datasheet

FEATURES

EP7209

■ Audio decoder system-on-chip

— Allows for support of multiple audio decompression

algorithms

— Supports MPEG 1, 2, & 2.5 layer 3 audio decoding,

including ISO compliant MPEG 1 & 2 layer 3 support for

all standard sample rates and bit rates — Supports bit streams with adaptive bit rates — DAI (Digital Audio Interface) providing glueless interface

to low power DACs, ADCs, and Codecs

■

Ultra low power consumption for MP3 playback

— 87 mW (typical) for 44.1 kHz samples/sec,

128 kbits/s econd — 50 mW for 22.05 kHz samples/s ec, 64kbits/second — <1 mW in St andb y State

■

ARM720T processor

— ARM7TDMI CPU — 8 kbytes of four-way set-associative cache — MMU with 64-entry TLB (transition look-aside buffer) — Write Buffer — Windows



CE enabled

— Thumb code support enabled

Functional Block Diagram

13-MHZ INPUT

3.6864 MHZ

32.768 KHZ

NPOR, RUN,

RESET, WAKEUP

BAT OK, NEXTPWR

PWRFL, BATCHG

EINT[1:3], FIQ,

MEDCHG

FLASHING LED DRIVE

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (0:7)

BUZZER DRIVE

DC-TO-DC

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

ADCCS

SSIRSFR

PLL

32.768-KHZ

OSCILLA TOR

STATE CONTROL

POWER

MANAGEMENT

INTERRUPT

CONTROLLER

RTC

GPIO

PWM

SSI1 (ADC)

DAI

SSI2

CODEC

Ultra-Low-Power Audio Decoder

System-on-Chip

OVERVIEW

The EP7209 is a complete integrated system on a chip for enabli ng per sonal di gi tal audio solutions. It is designed specifica lly for implementing audio processing algorithms in power sensitive applications. The core-logic functionality of the device is built around an ARM7 20T embedd ed p r ocessor.

The EP7209 also i ncludes a 32- bit Y2K-comp liant Real-Time Clock ( RTC) and comp ar ator.

(cont.) (cont.)

ARM720T

ARM7TDMI CPU CORE

8-KBYTE

CACHE

MMU

WRITE

BUFFER

TIMER

COUNTERS (2)

ON-CHIP

BOOT ROM

EPB BRIDGE

EPB BUS

INTERNAL DATA BUS

MEMORY CONTROLLER

CL-PS6700

INTFC.

EXPANSION

CONTROL

INTERNAL ADDRESS BUS

LCD

DMA

CONTROLLER

ON-CHIP SRAM

38,400 BYTES

ICE-JTAG

LCD

UART1 UART2

IrDA

D[0:31]

PB[0:1], NCS[4:5]

EXPCLK, WORD , NCS[0:3], EXPRDY, WRITE

A[0:27], DRA[0:12]

TEST AND DEVELOPMENT

LCD DRIVE

LED AND PHOTODIODE

ASYNC INTERFACE 1

ASYNC INTERFACE 2

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

DEC ‘99

DS453PP2

EP7209

FEATURES

■

Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz at 2.5 V

■

Performance matching 100 MHz Intel Pentium-based PC

■

OEM customization

— Integrated ARM720T RISC processor — Up to 25 MHz of CPU processing power avai lable (after

digital audio decoding) for custom features such as soft-

ware EQ or tone control, volume control, spectrum

analyzer, random play order, etc. — Allows for control of digital voice recorder function

■

LCD controller

— Interfaces directly to a single-scan panel monochrome

LCD — Panel width is programmable from 32 to 1024 pixels in

16-pixel increments — Video frame buffer size programmable up to 128kbytes — Bits per pixel of 1, 2, or 4 bits

■

Memory co nt r oller

— Decodes up to 6 separate memory segments of up to

256 Mbytes each — Each segment can be configured as 8, 16, or 32 bits

wide and supports page-mode access

(cont.)



— Programmable access time for conventional

ROM/SRAM/FLASH memory — Supports Removable FLASH card interface — Enables connection to removable FLASH card for addi-

tion of expansion FLASH memory modules

■

38,400 bytes ( 0x9 60 0) of on -ch i p SRA M fo r fast program execution and/or as a frame buffer

■

On-chip boot ROM for manufacturing support

■

Integrated D AI in te rf ac e

— Connects directly to a Crystal® audio DAC

■

27-bits of general-purpose I/O

— Three 8-bit and one 3-bit GPIO port — Supports scanning keyboard matrix

■

SIR (up to 115.2 kbps) infrared encoder/decoder

— IrDA (Infrared Data Association) SIR protocol

encoder/decoder

■

DC-to-DC converter interface (PWM)

— Provides two 96 kHz clock outputs with programmable

duty ratio (from 1-in-16 to 15-in-16) that can be used to

drive a DC to DC converter

■

208-pin LQFP or 256-ball PBGA p a ck ag e s

■

Full JTAG boundary scan and Embedded ICE support

OVERVIEW

(cont.)

The EP7209 also includes a comprehensive set of integrated peripherals such as an LCD display controller , an audio DAC inter face, and a FLASH memory interface. Using the EP7209, a portable audio decoder solution can be built with the addition of an LCD display, an audio DAC, a FL ASH memo ry subsystem, and a small number of additional low cost components.

The EP7209 uses its powerful 32-bit RISC processing engine to implement audio decompression algorithms in software. The nature of the on-board RISC processor and th e avai labi lity of ef fic ient C-comp iler s and other software dev elopme nt too ls ensure s that a wide range of audio decompression algorithms can easily be ported t o an d run o n t he EP 720 9.

The EP7209 uses external memory for storing application code. The use of external memory to support software audio decompression algorithms ensures that the audio deco mpression system so lution can be tailored to the requirements of the application. Software can be place d in a low cost mask ROM f or pri ce

sensitive applicati ons, or can be plac ed in external FLASH memory to enabl e upgradeable systems. The

EP7209’s 8 kbyte on-board cache and programmable wait state generator ensure that a wide range of memory options can be uti lize d.

The EP7209 runs a full ISO-compliant MPEG 1, 2, &

2.5 layer 3 audio decompre ssion engine with less than 50% of its availab le proces sing capab ility. This leaves significant processin g power available for product differentiation.

MPEG 1, 2, & 2.5 Layer 3 Object Code Library

Cirrus Logic provides an object code library for enabling MPEG 1, 2, & 2 .5 layer 3 aud io decomp ression. This library supports the MPEG 1 sample rates of 48 k, 44.1 k and 32 k bits per second; the MPEG 2 sample rates of 24 k, 22.05 k and 16 k bits per second; and the MPEG 2.5 s ample rates of 12 k,

11.025 k and 8 k bits per second. In addition to all standard fixed compressed data rates, the MPEG layer 3 object co de library also supports de compression of variabl e bi t- ra te data streams.

2 DS453PP2

EP7209

OVERVIEW

(cont.)

Power Management

The EP7209 is designed for ultra-low-power operation. Its core ope rat es at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. Through careful design, Cirrus Logic h as achieved extremely low power consumption with the EP7209. This is achieved by using a combination of dynamically adjustable core clock frequencies, low power states utilized during periods of inactivity, and fully static design principles. For example, when decompressing MPEG 1 layer 3 music data with sample rates of

44.1 kHz and 128 kbits/sec, the EP7209 consumes less than 87 mW. At sampling frequencies of

22.05 kHz and 64 kbits/sec, power consumption falls to 50 mW.

Audio Data Memory Interfaces

The EP7209 connects directly to both on-system FLASH memory and to re movable FLASH m emorycards. The generality of the external interface on the EP7209 allows for the use of a wide variety of additional memory type s for com press ed audi o dat a storage.

downloading of compressed music or data from a PC to an EP7209-ba sed po rtable digital aud io p la yer.

The EP7209 can also be connected to industry standard USB slave devices through an external interface. The power of the EP720 9 coupled with the 36 MHz external data bus ensures that the EP7209 can support rapid transfer of compressed audio data over a USB interface .

The EP7209 also includes a built-in 115.2 kbps IrDA SIR protocol encoder/decoder that can be used to drive an infrared communication interface to download the dat a.

Digital Audio Interface

The EP7209 integrates an DAI interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI interface can be used to drive the Crystal CS43L41 / 42 / 43 low power audio DACs and the Crystal CS53L32 low power audio A DC. Some of t hese devices f eature digital bass and treble boost, digital volume control and compressor-l imi ter fu ncti ons .

LCD Interface

The EP7209 int erfaces directl y to a singl e-scan pane l monochrome LCD display. For portable digital audio

Packaging

The EP7209 is available in a 208-pin LQFP package and a 256-ball PBGA pa cka ge.

player applications that require LCDs, a 128 kbyte display buf fer is pr ovi ded .

Data Download

System Design

As shown in the system block diagram, simply adding FLASH memory, an LCD, an audio DAC, and some

The EP7209 along with minimal glue logic can connect to a PC through the parallel port. This enables

discrete components, a complete low power digital audio player syst em can be made . (See the f ollowing illustration).

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product inf o rmation describes product s whi ch are in production, b ut f or which full character iza t i on da t a i s not yet available. Advance p rodu ct i nformation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document i s accurat e and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” without warrant y of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the pro perty of Cirrus Logi c, Inc. and i mplie s no licen se under patents, copyrights, tr ademarks, or trade secre ts. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electro nic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. It e ms f rom any Ci rrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

DS453PP2 3

EP7209

OVERVIEW

CRYSTAL

FLASH MEMORY

PC PARALLEL PORT

SMART MEDIA

INTERFACE

(cont.)

LCD

FLASH CARD/

CARD

NOR

FLASH

× 16

NAND

FLASH

× 8

MOSCIN

RTCIN

D[31:0] A[27:0]

NMOE NMWE

EINT[X] CS[3]

CS[0] CS[1]

PB[6:7]

NEXTPWR

EP7209

NBATCHG

COL[7:0]

PA[7:0]

PE[2:0]

NPOR NPWRFL NBATOK

RUN

WAKEUP

SSICLK

SSITXFR

SSITXDA

SSIRXDA

KEYBOARD/

PUSH BUTTONS

POWER

SUPPLY UNIT

AND

COMPARATORS

STEREO DAC CS43L41 / 42 /

STEREO ADC

CS53L32

BATTERY

HEADPHONES

MIC

USB

CS[4]

Figure 1. A Typical EP7209-Based Digital Audio Player Reference

4 DS453PP2

TABLE OF CONTENTS

1. CONVENTIONS ...................................................................................................................... 10

1.1 Acronyms and Abbreviations ............................................................................................ 10

1.2 Units of Measurement ......................................................................................................11

1.3 General Conventions ........................................................................................................11

1.4 Pin Description Conventions ............................................................................................. 11

2. PIN INFORMATION ..... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....................................... .......... 12

2.1 208-Pin LQFP Pin Diagram .............................................................................................. 12

2.2 Pin Descriptions ................................................................................................................ 13

2.2.1 External Signal Functions ................................................................................... 13

2.2.2 SSI/Codec/DAI Pin Multiplexing ............................................................................ 16

2.2.3 Output Bi-Directional Pins .................................................................................... 17

3. FUNCTIONAL DESCRIPTION ............................................................................................... 18

3.1 CPU Core .......................................................................................................................... 19

3.2 State Control ..................................................................................................................... 20

3.2.1 Standby State .......................................................................................................... 20

3.2.1.1 UART in Standby State ............................................................................... 21

3.2.2 Idle State ................................................................................................................. 22

3.2.3 Keyboard Interrupt ................................................................................................... 22

3.3 Resets ............................................................................................................................... 23

3.4 Clocks ............................................................................................................................... 23

3.4.1 On-Chip PLL ............................................................................................................ 23

3.4.1.1 Characteristics of the PLL Interface ............................................................ 24

3.4.2 External Clock Input (13 MHz) ................................................................................ 24

3.4.3 Dynamic Clock Switching When in the PLL Clocking Mode .................................... 26

3.5 Interrupt Controller ............................................................................................................ 26

3.5.1 Interrupt Latencies in Different States ..................................................................... 28

3.5.1.1 Operating State ........................................................................................... 28

3.5.1.2 Standby State .............................................................................................. 28

3.6 EP7209 Boot ROM .......................................................................................................... 29

3.7 Memory and I/O Expansion Interface ............................................................................... 30

3.8 CL-PS6700 PC Card Controller Interface ......................................................................... 31

3.9 Endianness ....................................................................................................................... 33

3.10 Internal UARTs (Two) and SIR Encoder ......................................................................... 34

3.11 Serial Interfaces .............................................................................................................. 34

3.11.1 Codec Sound Interface .......................................................................................... 36

3.11.2 Digital Audio Interface ........................................................................................... 37

3.11.2.1 DAI Operation ............................................................................................ 38

3.11.2.2 DAI Frame Format ..................................................................................... 38

3.11.2.3 DAI Signals ................................................................................................ 38

3.11.3 ADC Interface — Master Mode Only SSI1 (Synchronous Serial Interface) .......... 39

3.11.4 Master/Slave SSI2 (Syn chro nou s Serial Interfa ce 2) .................... ....... ...... ....... ... 39

3.11.4.1 Read Back of Residual Data ..................................................................... 42

3.11.4.2 Support for Asymmetric Traffic .................................................................. 42

3.11.4.3 Continuous Data Transfer ......................................................................... 43

3.11.4.4 Discontinuous Clock .................................................................................. 43

3.11.4.5 Error Conditions ........................................................................................ 43

3.11.4.6 Clock Polarity ............................................................................................ 43

3.12 LCD Controller with Support for On-Chip Frame Buffer .................................................. 43

3.13 Timer Counters ............................................................................................................... 45

3.13.1 Free Running Mode ............................................................................................... 46

3.13.2 Prescale Mode ............................ ...... ....... ...... ...... ....... ....................................... ... 46

3.14 Real Time Clock .............................................................................................................. 46

EP7209

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EP7209

3.14.1 Characteristics of the Real Time Clock Interface ................................................... 46

3.15 Dedicated LED Flasher ...................................................................................................47

3.16 Two PWM Interfaces .......................................................................................................47

3.17 Boundary Scan ................................................................................................................47

3.18 In-Circuit Emulation .........................................................................................................48

3.18.1 Introduction ............................................... ...... ...... ....... ...... ....................................48

3.18.2 Functionality .................................................... ...... ....... ...... ....... ...... ....... ...... ..........48

3.19 Maximum EP7209-Based System ..................................................................................48

4. MEMORY MAP ................................ ...................................... ....... ...... ....... ...... ....... ...... ..........50

5. REGISTER DESCRIPTIONS ..................................................................................................51

5.1 Internal Registers ..............................................................................................................51

5.1.1 PADR Port A Data Register .....................................................................................54

5.1.2 PBDR Port B Data Register .....................................................................................54

5.1.3 PDDR Port D Data Register ....................................................................................54

5.1.4 PADDR Port A Data Direction Register ................................................................... 54

5.1.5 PBDDR Port B Data Direction Register ................................................................... 54

5.1.6 PDDDR Port D Data Direction Register ...................................................................55

5.1.7 PEDR Port E Data Register .....................................................................................55

5.1.8 PEDDR Port E Data Direction Register ................................................................... 55

5.2 SYSTEM Control Registers ...............................................................................................56

5.2.1 SYSCON1 The System Control Register 1 ............................................................. 56

5.2.2 SYSCON2 System Control Register 2 .....................................................................59

5.2.3 SYSCON3 System Control Register 3 .....................................................................61

5.2.4 SYSFLG1 — The System Status Flags Register .................................................... 62

5.2.5 SYSFLG2 System Status Register 2 ....................................................................... 64

5.3 Interrupt Registers .............................................................................................................65

5.3.1 INTSR1 Interrupt Status Register 1 ......................................................................... 65

5.3.2 INTMR1 Interrupt Mask Register 1 ..........................................................................67

5.3.3 INTSR2 Interrupt Status Register 2 ......................................................................... 67

5.3.4 INTMR2 Interrupt Mask Register 2 ..........................................................................68

5.3.5 INTSR3 Interrupt Status Register 3 ......................................................................... 68

5.3.6 INTMR3 Interrupt Mask Register 3 ..........................................................................68

5.4 Memory Configuration Registers .......................................................................................69

5.4.1 MEMCFG1 Memory Configuration Register 1 .........................................................69

5.4.2 MEMCFG2 Memory Configuration Register 2 .........................................................69

5.5 Timer/Counter Registers ...................................................................................................71

5.5.1 TC1D Timer Counter 1 Data Register ..................................................................... 71

5.5.2 TC2D Timer Counter 2 Data Register ..................................................................... 71

5.5.3 RTCDR Real Time Clock Data Register ..................................................................71

5.5.4 RTCMR Real Time Clock Match Register ...............................................................71

5.6 LEDFLSH Register ............................................................................................................72

5.7 PMPCON Pump Control Register .....................................................................................73

5.8 CODR — The CODEC Interface Data Register ................................................................74

5.9 UART Registers ................................................................................................................74

5.9.1 UARTDR1–2 UART1–2 Data Registers ..................................................................74

5.9.2 UBRLCR1–2 UART1–2 Bit Rate and Line Control Registers ..................................75

5.10 LCD Registers .................................................................................................................77

5.10.1 LCDCON — The LCD Control Register ................................................................. 77

5.10.2 PALLSW Least Signi fic an t Word — LCD Palette Register ....................................78

5.10.3 PALMSW Most Significant Word — LCD Palette Register ....................................78

5.10.4 FBADDR LCD Frame Buffer Start Address ...........................................................79

5.11 SSI Register ....................................................................................................................79

5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register ..................................79

5.12 STFCLR Clear all ‘Start Up Reason’ flags location ........ ....... ...... ....... ...... ....... ...... ....... ... 8 0

6 DS453PP2

EP7209

5.13 ‘End Of Interrupt’ Locations ............................................................................................ 81

5.13.1 BLEOI Battery Low End of Interrupt ...................................................................... 81

5.13.2 MCEOI Media Changed End of Interrupt .............................................................. 81

5.13.3 TEOI Tick End of Interrupt Location ...................................................................... 81

5.13.4 TC1EOI TC1 End of Interrupt Location ................................................................. 81

5.13.5 TC2EOI TC2 End of Interrupt Location ................................................................. 82

5.13.6 RTCEOI RTC Match End of Interrupt .......................................................... ....... ... 82

5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt .................................. 82

5.13.8 COEOI Codec End of Interrupt Location ............................................................... 82

5.13.9 KBDEOI Keyboard End of Interrupt Location ........................................................ 82

5.13.10 SRXEOF End of Interrupt Location ..................................................................... 82

5.14 State Control Registers ...................................................................................................82

5.14.1 STDBY Enter the Standby State Location ............................................................. 82

5.14.2 HALT Enter the Idle State Location ....................................................................... 82

5.15 SS2 Registers ................................................................................................................. 83

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register ......................................... 83

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte ............................... 83

5.16 DAI Register Definitions ..................................................................................................83

5.16.1 DAI Control Register ............................................................................................. 84

5.16.1.1 DAI Enable (DAIEN) .................................................................................. 85

5.16.1.2 DAI Interrupt Generation ........................................................................... 85

5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM) ................................. 85

5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM) ................................. 85

5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM) .............................. 86

5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM) .............................. 86

5.16.1.7 Loop Back Mode (LBM) ............................................................................. 86

5.16.2 DAI Data Registers .. ....... ...... ....... ...... ....... ...... ....................................... ...... ....... ... 87

5.16.2.1 DAI Data Register 0 .................................................................................. 87

5.16.2.2 DAI Data Register 1 .................................................................................. 88

5.16.2.3 DAI Data Register 2 .................................................................................. 88

5.16.3 DAI Status Register ............................................................................................... 89

5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS) ................... 89

5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS) ................... 89

5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS) ...................... 89

5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS) ...................... 90

5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU) ........................... 90

5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO) ............................. 90

5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU) .............................. 90

5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO) ................................ 90

5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF) ................................. 90

5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE) ........................... 90

5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF) .................................. 91

5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE) .............................. 91

5.16.3.13 FIFO Operation Completed Flag (FIFO) ................................................. 91

6. ELECTRICAL SPECIFICATIONS .......................................................................................... 93

6.1 Absolute Maximum Ratings .............................................................................................. 93

6.2 Recommended Operating Conditions .............................................................................. 93

6.3 DC Characteristics ............................................................................................................ 93

6.4 AC Characteristics ............................................................................................................ 95

6.5 I/O Buffer Characteristics ................................................................................................ 102

6.6 JTAG Bandary Scan Signal Ordering ............................................................................. 102

7. TEST MODES ........ ...... ....................................... ....... ...... ...... ....... ...... ....... ...... ....... .............. 106

7.1 Oscillator and PLL Bypass Mode .................................................................................... 106

7.2 Oscillator and PLL Test Mode ......................................................................................... 106

DS453PP2

7.3 Debug/ICE Test Mode ....................................................................................................107

7.4 Hi-Z (System) Test Mode ...............................................................................................107

7.5 Software Selectable Test Functionality ..........................................................................107

8. PIN INFORMATION ..... ....... ...... ....... ...................................... ....... ...... ....... ...... ....... ...... ........ 108

8.1 208-Pin LQFP Pin Diagram .............................................................................................108

8.2 208-Pin LQFP Numeric Pin Listing .................................................................................109

8.3 256-Pin PBGA Pin Diagram ............................................................................................112

8.4 256-Ball PBGA Ball Listing ..............................................................................................113

8.4.1 PBGA Ground Connections ...................................................................................116

9. PACKAGE SPECIFICATIONS .............................................................................................117

9.1 208-Pin LQFP Package Outline Drawing .......................................................................117

9.2 EP7209 256-Ball PBGA (17

10. ORDERING INFORMATION ...............................................................................................119

11. APPENDIX A: BOOT CODE ..............................................................................................120

12. INDEX ................................................................................................................................. 125

LIST OF FIGURES

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram.............................................12

Figure 2. EP7209 Block Diagram..................................................................................................19

Figure 3. State Diagram ................................................................................................................ 20

Figure 4. CLKEN Timing Entering the Standby State ...................................................................25

Figure 5. CLKEN Timing Entering the Standby State ...................................................................25

Figure 6. Codec Interrupt Timing...................................................................................................36

Figure 7. DAI Interface .............. ...... ....................................... ...... ....... ...... ....... ...... ....... ...... ..........37

Figure 8. EP7209 Rev C - Digital Audio Interface Timing – MSB/Left Justified format................ 38

Figure 9. SSI2 Port Directions in Slave and Master Mode............................................................ 40

Figure 10. Residual Byte Reading.................................................................................................42

Figure 11. Video Buffer Mapping...................................................................................................45

Figure 12. A Maximum EP7209 Based System ............................................................................ 49

Figure 13. Consecutive Memory Read Cycles with Minimum Wait States....................................97

Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States.................................98

Figure 15. Consecutive Memory Write Cycles with Minimum Wait States.................................... 99

Figure 16. LCD Controller Timings..............................................................................................100

Figure 17. SSI Interface for AD7811/2 ........................................................................................100

Figure 18. SSI Timing Interface for MAX148/9............................................................................101

Figure 19. SSI2 Interface Timings...............................................................................................101

Figure 20. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram.........................................108

Figure 21. 256-Ball Plastic Ball Grid Array Diagram ...................................................................112

EP7209

× 17 × 1.53-mm Body) Dimensions ..................................118

LIST OF TABLES

Table 1. Acronyms and Abbreviations...........................................................................................10

Table 2. Unit of Measurement.......................................................................................................11

Table 3. Pin Description Conventions ...........................................................................................11

Table 4. External Signal Functions................................................................................................13

Table 5. SSI/Codec/DAI Pin Multiplexing......................................................................................16

Table 6. Output Bi-Directional Pins ...............................................................................................17

Table 7. Peripheral Status in Different Power Management States.............................................. 21

Table 8. Exception Priority Handling .............................................................................................26

Table 9. Interrupt Allocation in the First Interrupt Register............................................................ 27

Table 10. Interrupt Allocation in the Second Interrupt Register.....................................................27

Table 11. Interrupt Allocation in the Third Interrupt Register.........................................................27

Table 12. External Interrupt Source Latencies..............................................................................29

Table 13. Chip Select Address Ranges After Boot From On-Chip Boot ROM..............................29

8 DS453PP2

EP7209

Table 14. Boot Options ................................................................................................................. 30

Table 15. CL-PS6700 Memory Map.............................................................................................. 31

Table 16. Space Field Decoding................................................................................................... 32

Table 19. Serial Interface Options................................................................................................. 35

Table 20. Serial-Pin Assignments................................................................................................. 35

Table 21. ADC Interface Operation Frequencies.......................................................................... 39

Table 17. Effect of Endianness on Read Operations.................................................................... 41

Table 18. Effect of Endianness on Write Operations .................................................................... 41

Table 22. Instructions Supported in JTAG Mode .......................................................................... 47

Table 23. Device ID Register ........................................................................................................ 48

Table 24. EP7209 Memory Map in External Boot Mode............................................................... 50

Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode)............. 52

Table 26. EP7209 Internal Registers (Big Endian Mode) ............................................................. 54

Table 27. SYSCON1..................................................................................................................... 56

Table 28. SYSCON2..................................................................................................................... 59

Table 29. SYSCON3..................................................................................................................... 61

Table 30. SYSFLG........................................................................................................................ 62

Table 31. SYSFLG2...................................................................................................................... 64

Table 32. INTSR1 ......................................................................................................................... 65

Table 34. INTSR3 ......................................................................................................................... 68

Table 35. Values of the Bus Width Field....................................................................................... 70

Table 36. Values of the Wait State Field at 13 MHz and 18 MHz................................................. 70

Table 37. Values of the Wait State Field at 36 MHz ..................................................................... 70

Table 38. MEMCFG ...................................................................................................................... 71

Table 39. LED Flash Rates........................................................................................................... 72

Table 40. LED Duty Ratio ............................................................................................................. 72

Table 41. PMPCON ...................................................................................................................... 73

Table 42. Sense of PWM control lines.......................................................................................... 73

Table 43. UARTDR1-2 UART1-2.................................................................................................. 74

Table 44. UBRLCR1-2 UART1-2 .................................................................................................. 75

Table 45. LCDCON....................................................................................................................... 77

Table 46. Gray Scale Value to Color Mapping.............................................................................. 79

Table 47. SYNCIO ........................................................................................................................ 80

Table 48. DAI Control Register ..................................................................................................... 84

Table 49. DAI Data Register 0...................................................................................................... 87

Table 50. DAI Data Register 1...................................................................................................... 88

Table 51. DAI Control, Data and Status Register Locations......................................................... 91

Table 52. absolute Maximum Ratings........................................................................................... 93

Table 53. Recommended Operating Conditions........................................................................... 93

Table 54. DC Characteristics........................................................................................................ 93

Table 55. AC Timing Characteristics.............................................................................................95

Table 56. Timing Characteristics................................................................................................... 96

Table 57. I/O Buffer Output Characteristics ................................................................................ 102

Table 58. 208-Pin LQFP Numeric Pin Listing ............................................................................. 102

Table 59. EP7209 Hardware Test Modes................................................................................... 106

Table 60. Oscillator and PLL Test Mode Signals........................................................................ 107

Table 61. Software Selectable Test Functionality....................................................................... 107

Table 62. 208-Pin LQFP Numeric Pin Listing ............................................................................. 109

Table 63. 256-Ball PBGA Ball Listing.......................................................................................... 113

Table 64. PBGA Balls to Connect to Ground (V

) .................................................................... 116

DS453PP2

EP7209

1. CONVENTIONS

This section presents acronyms, abbreviations, units of measurement, and conventions used in this data sheet.

1.1 Acronyms and Abbreviations

Table 1 lists abbreviations and acronyms used in

this data sheet.

Acronym/

Abbreviation

AC alternating current. A/D analog-to-digital. ADC analog-to-digi tal conve r ter.

CMOS CODEC coder/decoder.

CPU central processing unit. D/A digital-to-analog. DC direct current. DMA direct-memory access. EPB embedded peripheral bus. FCS frame check sequence. FIFO first in/first out. GPIO general purpose I/O. ICT in circuit test. IR infrared. IrDA Infrared Data Association. JTAG Joint Test Action Group.

complementary metal oxide semiconductor.

Definition

Acronym/

Abbreviation

LCD liquid crystal display. LED light-emitting diode. LQFP low profile quad flat pack. LSB least significant bit.

MIPS MMU memory management unit.

MSB most significant bit. PBGA plastic ball grid array. PCB printed circuit board. PDA personal digital assistant. PIA peripheral inter face a dapt er. PLL phase locked loop. PSU power supply unit. p/u pull-up resistor. RAM random access memory.

RISC ROM read-only memory.

RTC Real Time Clock. SIR slow (9600–115.2 kbps) infrared. SRAM static random access memory. SSI synchronous serial interface. TAP te st acces s port. TLB tran slati on loo ka side buffer.

UART

millions of instructions per second.

reduced instruction set computer.

universal asynchro n ous receiver.

Definition

Table 1. Acronyms and Abbreviations

10 DS453PP2

Table 1. Acronyms and Abbreviations (cont.)

1.2 Units of Measurement 1.3 General Conventions

EP7209

Symbol Unit of Measure

°C

Hz hertz (cycle per second) kbits/s kilobits per second kbyte kilobyte (1,024 bytes) kHz kilohertz

Ω kilohm

k Mbps megabits (1,048,576 bits) per second Mbyte megabyte (1,048,576 bytes) MHz megahertz (1,000 kilohertz)

µAmicroampere µFmicrofarad µWmicrowatt µs microsecond (1,000 nanoseconds)

mA milliampere mW milliwatt ms millisecond (1,000 microseconds) ns nanosecond Vvolt Wwatt

degree Celsius

Table 2. Unit of Measurement

Hexadecimal numbers are presen ted with all l etters in uppercase and a lowercase ‘h’ appended or with a 0x at the beginning. For example, 0x14 and 03CAh are hexadecimal numbers. Binary numbers are enclosed in single quotation marks when in text (for example, ‘11’ designates a binary number). Numbers not indicated by an ‘h’, 0x or quotation marks are decimal.

Registers are referred to by acronym, as listed in the tables on the previous page, with bits listed in brackets MSB-to-LSB separated by a colon (:) (for example, CODR[7:0]), or LSB-to-MSB separated by a hyphen (for example, CODR[0–2]).

The use of ‘tbd’ indicates values that are ‘to be determined’, ‘n/a’ designates ‘not available’, and ‘n/c’ indicates a pin that is a ‘no connect’.

1.4 Pin Description Conventions

Abbreviations used for signal directions are listed in Table 3.

Abbreviation Direction

I Input OOutput I/O Input or Output

DS453PP2

Table 3. Pin Description Conventions

2. PIN INFORMATION

2.1 208-Pin LQFP Pin Diagram

NEXTPWR

BATOK

NPOR

VDDOSC

MOSCIN

MOSCOUT

VSSOSC WAKEUP NPWRFL

A[6] D[6] A[5] D[5]

VDDIO

VSSIO

A[4] D[4] A[3] D[3] A[2]

VSSIO

D[2] A[1] D[1] A[0] D[0]

VSSCORE

VDDCORE

VSSIO

VDDIO

CL[2] CL[1]

FRM

DD[3] DD[2]

VSSIO

DD[1] DD[0]

N/C N/C N/C N/C

VDDIO

VSSIO

N/C N/C

NMWE

NMOE

VSSIO NCS[0] NCS[1] NCS[2] NCS[3] NCS[4]

NURESET

NMEDCHG/NBROM

156

155

157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186

187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208

D[7]

A[7]

D[8]

A[8]

D[9]

D[10]

154

153

152

NBATCHG

151

150

VSSIO

149

148

147

146

145

A[9]

144

143

A[10]

142

D[11]

141

2345678910111213141516171819202122232425262728293031323334353637383940414243444546474849515052

VSSIO

VDDIO

A[11]

D[12]

A[12]

D[13]

A[13]

140

139

138

137

136

134

135

EP7209

208-Pin LQFP

(Top View)

D[14]

133

A[14]

132

D[15]

131

A[15]

130

D[16]

129

A[16]

128

D[17]

127

A[17]

126

NTRST

125

VSSIO

124

VDDIO

D[18]

122

123

A[18]

121

D[19]

120

EP7209

A[19]

D[20]

VSSIO

A[21]

D[22]

D[23]

A[23]

D[24]

VSSIO

VDDIO

A[24]

109

108

107

106

HALFWORD

105

104 103 102 101 100

D[25] A[25] D[26] A[26] D[27]

99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53

A[27] VSSIO D[28] D[29] D[30] D[31] BUZ COL[0] COL[1] TCLK VDDIO COL[2] COL[3] COL[4] COL[5] COL[6] COL[7] FB[0] VSSIO FB[1] SMPCLK ADCOUT ADCCLK DRIVE[0] DRIVE[1] VDDIO VSSIO VDDCORE VSSCORE NADCCS ADCIN SSIRXFR SSIRXDA SSITXDA SSITXFR VSSIO SSICLK PD[0]/LEDFL SH PD[1] PD[2] PD[3] TMS VDDIO PD[4] PD[5] PD[6] PD[7]

A[22]

D[21]

A[20]

111

110

112

113

114

115

116

117

118

119

NCS[5]

VSSIO

VDDIO

TDI

PB[7]

PB[6]

PB[5]

PB[4]

TXD[2]

WORD

WRITE

EXPCLK

VSSIO

RXD[2]

EXPRDY

PB[3]

RUN/CLKEN

TDO

PA[6]

PA[5]

PA[3]

PA[2]

PA[1]

PB[2]

PA[7]

VDDIO

PB[1]/PRDY[2]

PB[0]/PRDY[1]

PA[0]

PA[4]

TXD[1]

LEDDRV

CTS

DSR

DCD

VSSIO

PHDIN

RXD[1]

EINT[3]

NEINT[2]

NEINT[1]

NTEST[1]

NEXTFIQ

NTEST[0]

PE[2]/CLKSEL

PE[1]BOOTSEL[1]

PE[0]BOOTSEL[0]

N/C

RTCIN

VDDRTC

VSSRTC

RTCOUT

Notes: 1)For package specifications, please see 208--Pin LQFP Package Outline Drawing on page 117

2)N/C should not be grounded but left as no connects

Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

12 DS453PP2

EP7209

2.2 Pin Descriptions

Table 4 describes the function of all the external signals to the EP7209. Note that all output signals are tri-

stateable to enable the Hi-Z test modes to be supported.

2.2.1 External Signal Functions

Function Signal

Signal Description

Name

Data bus D[0:31] I/O 32-bit system data bus for memory and I/O interface

A[0:27] O 28 bits of system byte address during memory and expansion cycles

Whenever the EP7209 is in the Standby State, the external address and data

Address bus

nMOE O Memory output enable, active low

nMWE O Memory write enable, active low nCS[0:3] O Chip select; active low, SRAM-like chip selects for expansion nCS[4:5] O Chip select; active low, CS for expansion or for CL-PS6700 select

EXPRDY I

WRITE O Write strobe, low during reads, high during writes from the EP7209

buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to p reve nt perip herals that are powe red-d own from draining current. Also, the internal peripheral’s signals get set to their Reset State.

Expansion port ready; external expansion devices drive this low to extend the bus cycle. This is used to insert wait states for an external bus cycle.

To do write accesses of dif fere nt siz es W ord and Hal f-W ord mus t be extern ally decoded. The encoding of these signals is as follows:

Access Size Word Half-Word

Word 1 0

Memory

Interface

Half-Word * 1

Byte 0 0

DS453PP2

WORD/

HALFWORD

EXPCLK I/O

The core will generate an address. When doing a read, the ARM core will select the appropriate byte channels. When doing a write, the correct bytes will have to be enabled depending on the above signals and the least significant bits of the address bus. The ARM architecture does no t sup port un ali gne d ac ces s es. For a read using x 32 memory, it is assumed tha t y ou w ill i gno re b it s 1 an d 0 of the address bus and perform a word rea d (or i n po wer c ritical systems decode the relevan t bits depending on the size of the access). If an unaligned read takes place, the core will rotate the resulting data in the register. For more information on this behavior see the LDR instruction in the ARM7TDMI data sheet.

Expansion cl oc k ra te i s t he s am e a s the CP U clock for 13 MHz and 18MHz. It runs at 36.864 MHz for 36,49 and 74 MHz modes; in 13 MHz mode this pin is used as the clock input.

Table 4. External Signal Functions

EP7209

Function Signal

Name

nMEDCHG/

nBROM

Interrupts

Power

Management

nEXTFIQ I External active low fast interrupt request input

EINT[3] I External active high interrupt request input

nEINT[1:2] I Two general purpose, active low interrupt inputs

nPWRFL

BATOK

nEXTPWR I

nBATCHG

nPOR I

Signal Description

Media changed input; active low, deglitched. Used as a general purpose FIQ interrupt during normal ope r ati on. It is also us ed on pow er up to co nfi gure the

processor to either boot from the internal Boot ROM, or from external memory. When low, the chip will boot from the internal Boot ROM.

Power fail input; active low, deglitched input to force system into the Standby

State Main battery OK input; fallin g edge gen erates a FIQ, a low lev el in th e Standby

State inhibits system start up; deglitched input External power sense; must be driven low if the system is powered by an

external source New battery sense; driven low if battery voltage falls below the "no-battery"

threshold; it is a deglitched input Power-on reset input. This signal is not deglitched. When active it completely

resets the entire system, including all the RTC registers. Upon power-up, the signal must be held active low for a minimum of 100 µsec after Vdd has settled. During normal operation, nPOR needs to be held low for at least one clock cycle of the selected clock speed (i.e., when running at 13 MHz, the pulse width of nPOR needs to be > 77 nsec).

State Control

DAI, Codec or

SSI2

Interface

(See Table 5 for SSI2/Codec/DAI Pin Multiplexing)

Note that nURESET, RUN/CLKEN, TEST(0), TEST(1), PE(0), PE(1), PE(2), DRIVE(0), DRIVE(1), DD(0), DD(1), DD(2), and DD(3) are al l latched on rising edge of nPOR.

This pin is programmed to either output the RUN signal or the CLKEN signal. The CLKENSL bit is used to configure this pin. When RUN is selected, the pin

RUN/CLKEN I/O

WAKEUP

nURESET

SSICLK I/O DAI/Codec/SSI2 clock signal

SSITXFR I/O DAI/Codec/SSI2 serial data output frame/synchronization pulse output

SSITXDA O DAI/Codec/SSI2 serial data output SSIRXDA I

SSIRXFR I/O

will be high when the system is active or idle, low while in the Standby State. When CLKEN is selected, the pin will only be driven low when in the Standby State (For RUN, see Table 6).

Wake up deglitched input signal; rising edge forces system into the Operating State from the Standby State; active after an nPOR reset. The wakeup signa l can not be used to exit Idle, only Standby. Wakeup must wait at least 2 sec-

onds before it goes high for it to be detected by the CPU. It must also be held high for at least 125 first detection has no effect (i.e., it is ignored).

User reset input; active low deglitched input from user reset button. This pin is also latched upon the rising edge of nPOR and read along with the

input pins nTEST[0:1] to force the device into special test modes. nURESET does not reset the RTC.

DAI/Codec/SSI2 seri al data input

SSI2 serial data input frame/synchronizati on pulse DAI external clock input

µsec to guarantee its detection. Toggling wakeup after its

Table 4. External Signal Functions (cont.)

14 DS453PP2

EP7209

Function Signal

Name

ADCCLK O Serial clock output

ADC

Interface

(SSI1)

IrDA and

RS232

Interfaces

LCD

Keyboard & Buzzer drive LED Flasher

General

Purpose I/O

PWM

Drives

nADCCS O Chip select for ADC interface

ADCOUT O Seria l data output

ADCIN I Serial data input SMPCLK O Sample cloc k output LEDDRV O Infrared LED drive output (UART1)

PHDIN I Photo diode input (UART1)

TXD[1:2] O RS232 UART1 and 2 TX outputs

RXD[1:2] I RS232 UART1 and 2 RX inputs

DSR I RS232 DSR input

DCD I RS232 DCD input

CTS I RS232 CTS input

DD[0:3] I/O

CL[1] O LCD line clock CL[2] O LCD pixel clock FRM O LCD frame synchronization pulse output

M O LCD AC bias drive

COL[0:7] O Keyboard column drives (SYSCON1)

BUZ O Buzzer drive output (SYSCON1)

PD[0]/

LEDFLSH

PA[0:7] I/O

PB[0]/PRDY1 PB[1]/PRDY2

PB[2:7]

PD[0:7] I/O Port D I/O

PE[0]/

BOOTSEL[0]

PE[1]/

BOOTSEL[1]

PE[2]/

CLKSEL

DRIVE[0:1] I/O

FB[0:1] I PWM feedback inputs

Signal Description

LCD serial display data; pins can be used on power up to read the ID of some LCD modules (See Table 6).

LED flasher driver — multiplexed with Port D bit 0. This pin can provide up to

4 mA of drive current. Port A I/O (bit 6 for boot clock option, bit 7 for CL-PS6700 PRDY input); also

used as keyboard row inputs Port B I/O. All eight Port B bits can be used as GPIOs.

When the PC CARD1 or 2 control bits in the SYSCON2 register are de-

I/O

asserted, PB[0] and PB[1] are available for GPIO. When asserted, these port bits are used as the PRDY signals for connected CL-PS6700 PC Card Host Adapter devices.

Port E I/O (3 bits only). Can be used as general purpose I/O during normal

I/O

operation. During power-on reset, PE[0] and PE[1] are inputs and are latched by the ris-

I/O

ing edge of nPOR to s el ect the me mo ry wi d th tha t th e EP7209 will use to read from the boot code storage device (i.e., external 8-bit-wide FLASH bank).

During power-on reset, PE[2] is latched by the rising edge of nPOR to select

I/O

the clock mode of operation (i.e., either the PLL or external 13 MHz clock mode).

PWM drive ou tputs. These pins are inputs on power up to determine what polarity the output of the PWM should be when active. Otherwise, these pins are always an output (See Table 6).

DS453PP2

Table 4. External Signal Functions (cont.)

EP7209

Function Signal

Signal Description

Name

TDI I JTAG data in

Boundary

Scan

Test nTEST[0:1] I

Oscillators

No connects N/C No connects should be left as no connects; do not connect to ground

TDO O JTAG data out TMS I JTAG mode select

TCLK I JTAG clock

nTRST I JTAG async reset

Test mode select input s. Th ese pi ns are u sed in conju nction with t he power-o n latched state of nURESET to select between the various device test models.

MOSCIN

MOSCOUT

RTCIN

RTCOUT

Main 3.6864 MHz oscillator for 18.432 MHz–73.728 MHz PLL

Real Time Clock 32.768 kHz oscillator

Table 4. External Signal Functions (cont.)

1. All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least two clock periods. Therefore, the input signal must be active for at least ~125

µs to be detected cleanly.

NOTE: The RTC crystal must be populated for the device to function properly.

2.2.2 SSI/Codec/DAI Pin Multiplexing

SSI2 Codec DAI Direction Strength

SSICLK PCMCLK SCLK I/O 1 SSITXFR PCMSYNC LRCK I/O 1 SSITXDA PCMOUT SDOUT Output 1

SSIRXDA PCMIN SDIN Input SSIRXFR p/u* MCLK I/O 1

* p/u = use an ~10 k pull-up

The selection between SSI2 and the codec is controlled by the state of the SERSEL bit in SYSCON2 (See SYSCON2 System Control Register 2). The choice between the SSI2, codec, and the DAI is controlled by the DAISEL bit in SYSCON3 (See SYSCON3 System Control Register 3).

Table 5. SSI/Codec/DAI Pin Multiplex ing

16 DS453PP2

EP7209

2.2.3 Output Bi-Directional Pins

RUN The RUN pin is looped back in to skew the address and data bus from each other. Drive [0:1] Drive 0 and 1 are looped back in on power up to determine what polarity the output of the PWM should be

when active.

DD[3:0] DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules.

NOTE: The above output pins ar e implemen ted as b i-direction al pins to enable the out put side of the pad to

be monitored and hence provide more accurate control of timing or duration:

Table 6. Output Bi-Directional Pins

DS453PP2

EP7209

3. FUNCTIONAL DESCRIPTION

The EP7209 device is a single-chip embedded controller designed to be used in low cost and ultralow-power digital audio players. Operating at 74 MHz, the EP7209 delivers approximately 66 Dhrystone 2.1 MIPS of sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC.

The EP7209 contains the following functional blocks:

• ARM720T processor which consists of the fol-

lowing functional sub-blocks:

- ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced multiplier, JTAG, and the Embedded ICE) running at a dynamically programmable clock speed of 18 MHz, 36 MHz, 49 MHz, or 74 MHz.

- Memory Management Unit (MMU) compatible with the ARM710 core (providing address translation and a 64 entry translation lookaside buffer) with added support for Windows CE.

- 8 kbytes of unified instruction and data cache with a four-way set associative cache controller.

- Write buffer

• 38,400 bytes (0x9600) of on-chip SRAM that can be shared between the LCD controller and general application use.

• Memory interfaces for up to 6 independent 256 Mbyte expansion segments with programming wait states.

• 27 bits of general purpose I/O - multiplexed to provide additional functionality where necessary.

• Digital Audio Interface (DAI) for connection to CD-quality DACs and codecs.

• Interrupt controller

• Advanced system state control and power man-

agement.

• Two full-duplex 16550A compatible UARTs with 16-byte transmit and receive FIFOs.

• IrDA SIR protocol controller capable of speeds up to 115.2 kbps.

• Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level gray scaler.

• Programmable frame buffer start address, allowing a system to be built using only internal SRAM for memory.

• On-chip boot ROM programmed with serial load boot sequence.

• Two 16-bit general purpose timer counters.

• A 32-bit Real Time Clock (RTC) and compar-

ator.

• Dedicated LED flasher pin driven from the RTC with programmable duty ratio (multiplexed with a GPIO pin).

• Two synchronous serial interfaces for Microwire or SPI peripherals such as ADCs, one supporting both the master and slave mode and the other supporting only the master mode.

• Full JTAG boundary scan and Embedded ICE support.

• Two programmable pulse-width modulation interfaces.

• An interface to one or two Cirrus Logic CLPS6700 PC Card controller devices to support two PC Card slots.

18 DS453PP2

EP7209

• Oscillator and phase locked loop (PLL) to generate the core clock speeds of 18.432 MHz,

36.864 MHz, 49.152 MHz, and 73.728 MHz from an external 3.6864 MHz crystal, with an alternative external clock input (used in 13 MHz mode).

• A low power 32.768 kHz oscillator.

The EP7209 design is optimized for low power dissipation and is fabricated on a fully static

0.25 micron CMOS process. It is available in a

256-ball PBGA or a 208-pin LQFP package.

Figure 2 shows a simplified block diagram of the

EP7209. All external memory and peripheral devices are connected to the 32-bit data bus using the external 28-bit address bus and control signals.

3.1 CPU Core

The ARM720T consists of an ARM7TDMI 32-bit RISC processor, a unified cache, and a memory management unit (MMU). The cache is four-way set associative with 8-kbytes organized as 512 lines of 4 words. The cache is directly connected to the ARM7TDMI, and therefore caches the virtual address from the CPU. When the cache misses, the MMU translates the virtual address into a physical address. A 64-entry translation lookaside buffer (TLB) is utilized to speed the address translation process and reduce bus traffic necessary to read the page table. The MMU saves power by only translating the cache misses.

See the ARM720T Data sheet for a complete description of the various logic blocks that make up the processor, as well as all internal registe r information.

13-MHZ INPUT

3.6864 MHZ

32.768 KHZ

NPOR, RUN,

RESET, WAKEUP

BAT OK, NEXTPWR

PWRFL, BATCHG

EINT[1:3], FIQ,

MEDCHG

FLASHING LED DRIVE

PORTS A, B, D (8-B IT)

PORT E (3-BIT)

KEYBD DRIVERS (0:7)

BUZZER DRIVE

DC-TO-DC

ADCCLK, ADCIN,

ADCOUT, SMPCLK,

SSICLK, SSITXFR,

SSITXDA, SSIRXDA,

ADCCS

SSIRSFR

PLL

32.768-KHZ

OSCILLATOR

STATE CONTRO L

POWER

MANAGEMENT

INTERRUPT

CONTROLLER

RTC

GPIO

PWM

SSI1 (ADC)

DAI

SSI2

CODEC

INTERNAL DATA BUS

ARM720T

ARM7TDMI CPU CORE

8-KBYTE

CACHE

MMU

WRITE

BUFFER

TIMER

COUNTERS (2)

ON-CHIP

BOOT ROM

EPB BRIDGE

EPB BUS

MEMORY CONTROLLER

CL-PS6700

INTFC.

EXPANSION

CONTROL

INTERNAL ADDRESS BUS

LCD

DMA

LCD

CONTROLLER

ON-CHIP SRAM

38,400 BYTES

UART1 UART2

Figure 2. EP7209 Block Diagram

ICE-JTAG

IrDA

D[0:31]

PB[0:1], NCS[4:5]

EXPCLK, WORD, NCS[0:3], EXPRDY, WRITE

A[0:27], DRA[0:12]

TEST AND DEVELOPMENT

LCD DRIVE

LED AND PHOTODIODE

ASYNC INTERFACE 1

ASYNC INTERFACE 2

DS453PP2

EP7209

Figure 3. State Diagram

Standby

Operating

Idle

Interrupt or r ising wakeup

Write to standby location, power fail, or user reset

Write to halt location

nPOR, power fail, or user reset

3.2 State Control

The EP7209 supports the following Power Management States: Operating, Idle, and Standby (see

Figure 3). The normal program execution state is

the Operating State; this is a full performance state where all of the clocks and peripheral logic are enabled. The Idle State is the same as the Operating State with the exception of the CPU clock being halted, and an interrupt or wakeup will return it back to the Operating State. The Standby State has the lowest power consumption, selecting this mode shuts down the main oscillator, leaving only the Real Time Clock and its associated logic powered. It is important when the EP7209 is in Standby that all power and ground pins remain connected to power and ground in order to have a proper system wake-up. The only state that Standby can transition to is the Operating State.

3.2.1 Standby State

The Standby State equates to the system being switched "off" (i.e., no display, and the main oscillator is shut down). When the 18.432–73.72 MHz mode is selected, the PLL will be shut down. In the 13 MHz mode, if the CLKENSL bit is set low, then the CLKEN signal will be forced low and can, if required, be used to disable an external oscillator.

In the Standby State, all the system memory and state is maintained and the system time is kept upto-date. The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except for the low power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal is driven low and this signal can be used externally in the system to power down other system modules.

Whenever the EP7209 is in the Standby State, the external address and data buses are forced low internally by the RUN signal. Thi s i s do ne to preve nt peripherals that are powered-down from draining current. Also, the internal peripheral’s signals get set to their Reset State.

In the description below, the RUN/CLKEN pin can be used either for the RUN functionality, or the CLKEN functionality to allow an external oscillator to be disabled in the 13 MHz mode. Either RUN or CLKEN functionality can be selected according to the state of the CLKENSL bit in the SYSCON2 register. Table 7 on the following page shows peripheral status in various power management states.

When first powered, or reset by the nPOR (Power On Reset, active low) signal, the EP7209 is forced into the Standby State. This is known as a cold reset, and when leaving the Standby State after a cold reset, external wake up is the only way to wake up the device. When leaving the Standby State after non-cold reset conditions (i.e., the software has forced the device into the Standby State), the transition to the Operating State can be caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when entering the Standby State from the Operating State, the software will leave some interrupt sources enabled.

NOTE: The CPU cannot be awakened by the T INT,

WEINT, and BLINT interrupts when in the Standby State.

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EP7209

Address (W/B) Operating Idle Standby nPOR

UARTs LCD FIFO LCD ADC Interface SSI2 Interface DAI Interface Codec Timers RTC LED Flasher DC-to-DC CPU Interrupt Control PLL/CLKEN Signal

Table 7. Peripheral Status in Different Power Management States

On On Off Reset Reset On On Reset Reset Reset On On Off Reset Reset On On Off Reset Reset On On Off Reset Reset On On Off Reset Reset On On Off Reset Reset On On Off Reset Reset On On On On On On On On Reset Reset On On Off Reset Reset On Off Off Reset Reset On On On Reset Reset On On Off Off Off

Typically, software writes to the Standby internal memory location to cause the transition from the Operating State to the Standby State. Before entering the Standby State, if external I/O devices (such as the CL-PS6700s connected to nCS[4] or nCS[5]) are in use, the software must c heck to ensure that they are idle before issuing the write to the Standby State location.

Before entering the Standby State, the software must properly disable the DAI. Failing to do so will result in higher than expected power consumption in the Standby State, as well as unpredictable operation of the DAI. The DAI ca n be r e-enabled afte r transitioning back to the Operating State.

nURESET

RESET

and either the nEXTPWR input pin is low or the BATOK input pin is high. This prevents the system from starting when the power supply is inadequate (i.e., the main batteries are low), corresponding to a low level on nPWRFL or BATOK.

From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock running, the EP7209 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point. After the first clock is applied, there will be a delay of about eight clock cycles before the CPU is enabled. This delay is to allow the clock to the CPU time to settle.

The system can also be forced into the Standby State by hardware if the nPWRFL or nURESET inputs are forced low. The only exit from the Standby State is to the Operating State.

The system will only transition to the Operating State from the Standby State under the following conditions: when the nPWRFL input pin is high

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3.2.1.1 UART in Standby State

During the Standby State, the UARTs are disabled and cannot detect any activity (i.e., start bit) on the receiver. If this functionality is required then this can be accomplished in software by the following method:

EP7209

1) Permanently connect the RX pin to one of t he active low external interrupt pins.

2) Ensure that on entry to the Standby State, t he chosen interrupt source is not masked, and the UART is enabled.

3) Send a preamble that consists of one start bit, 8 bits of zero, and one stop bit. This will cause the EP7209 to wake and execute the enabled interrupt vector.

The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the star t of the preamble, the timing of the sample point will be offcenter during the preamble byte. However, the next byte transmitted will be correctly aligned. Thus, the actual first real byte to be received by the UART will get captured correctly.

3.2.2 Idle State

If in the Operating State, the Idle State can be entered by writing to a special internal memory location (HALT) in the EP7209. If an interrupt occurs, the EP7209 will return immediately back to the Operating State and execute the next instruction. The WAKEUP signal can not be used to exit the Idle State. It is only used to exit the Standby State.

In the Idle State, the device functions just like it does when in the Operating State. However, the CPU clock is halted while it waits for an event such as a key press to generate an interrupt. The PLL (in 18.432–73.728 MHz mode) or the external 13 MHz clock source always remains active in the Idle State.

3.2.3 Keyboard Interrupt

For the case of the keyboard interr upt, the following options are available and are selectable according to bits 1 and 3 of the SYSCON2 regis-

ter (refer to the SYSCON2 Register Description for details).

• If the KBWEN bit (SYSCON2 bit 3) is set low, then a keypress will cause a transition from a power saving state only if the keyboard interrupt is non-masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is high).

• When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the “Keyboard Direct Wakeup’ mode. In this mode, the interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off before it entered the power saving state. If the interrupt is non-masked, then the processor will service the interrupt.

• When the KBD6 bit (SYSCON2 bit 1) is low, all 8 of Port A inputs are OR’ed together to produce the internal wakeup signal and keyboard interrupt request. This is the default reset state.

• When the KBD6 bit (SYSCON2 bit 1) is high, only the lowest 6 bits of Port A are OR’ed together to produce the internal wakeup signal and keyboard interrupt request. The two most significant bits of Port A are available as GPIO when this bit is set high.

In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup the device by using the external WAKEUP pin or another enabled interrupt source. The keyboard interrupt capability allows an OS to use either a polled or interrupt-driven keyboard routine, or a combination of both.

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EP7209

NOTE: The keyboard interrupt is NOT deglitched.

3.3 Resets

There are three asynchronous resets to the EP7209: nPOR, nPWRFL and nURESET. If any of these are active, a system reset is generated internally. This will reset all internal registers in the EP7209 except the RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be preserved through a user reset or power fail condition.

Any reset will also reset the CPU and cause it to start execution at the reset vector when the EP7209 returns to the Operating State.

Internal to the EP7209, three different signals are used to reset storage elements. These are nPOR, nSYSRES and nSTBY. nPOR is an external signal. nSTBY is equivalent to the external RUN signal.

nPOR (Power On Reset, active low) is the highest priority reset signal. When active (low), it will reset all storage elements in the EP7209. nPOR active forces nSYSRES and nSTBY active. nPOR will only be active after the EP7209 is first powered up and not during any other resets. nPOR active will clear all flags in the status register except for the cold reset flag (CLDFLG) bit, which is set.

nSYSRES (System Reset, active low) is generated internally to the EP7209 if nPOR, nPWRFL or nURESET are active. It is the second highest priority reset signal, used to asynchronously reset most internal registers in the EP7209. nSYSRES active forces nSTBY and RUN low. nSYSRES is used to reset the EP7209 and force it into the Standby State with no co-operation from software. The CPU is also reset.

The nSTBY and RUN signals are high when the EP7209 is in the Operating or Idle States and low when in the Standby State . The ma in syst em c lock is valid when nSTBY is high. The nSTBY signal will disable any peripheral block that is clocked from the master clock source (i.e., everything ex-

cept for the RTC). In general, a system reset will clear all registers and nSTBY will disable all peripherals that require a main clock. The following peripherals are always disabled by a low level on nSTBY: two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI interfaces. In addition, when in the Standby State, the LCD controller and PWM drive are also disabled.

When operating from an external 13 MHz oscilla tor which has become disabled in the Standby State by using the CLKEN signal (i.e., with CLKENSL = 0), the oscillator must be stable within 0.125 sec from the rising edge of the CLKEN signal.

3.4 Clocks

There are two clocking modes for the EP7209. Either an external clock input can be used or the onchip PLL. The clock source is selected by a strapping option on Port E, pin 2 (PE[2]). If PE[2] is high at the rising edge of nPOR (i.e., upon power up), the external clock mode is selected. If PE[2] is low, then the on-chip PLL mode is selected. After power-up, PE[2] can be used as a GPIO.

The EP7209 device contains several separate sections of logic, each clocked according to its own clock frequency requirements. When the EP7209 is in external clock mode, the actual frequencies at the peripherals will be different than when in PLL mode. See each peripheral device section for more details. The section below describes the clocking for both the ARM720T and address/data bus.

3.4.1 On-Chip PLL

The ARM720T clock can be programmed to

18.432 MHz, 36.864 MHz, 49.152 MHz or

73.728 MHz with the PLL running at twice the highest possible CPU clock frequency (147.456 MHz). The PLL uses an external

3.6864 MHz crystal. By chip default, the on-chip PLL is used and configured such that the ARM720T and address/data buses run at

18.432 MHz.

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EP7209

When the clock frequency is selected to be 36 MHz, both the ARM720T and the address/data buses are clocked at 36 MHz. When t he clock frequency is selected higher than 36 MHz, only the ARM720T gets clocked at this higher speed. The address/data will be fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the SYSCON3 register. The clock frequency selection does not effect the EPB. Therefore, all the peripheral clocks are fixed, regardless of the clock speed selected for the ARM720T.

NOTE: After modifying the CLKCTL[1:0] bits, the

next instruction should always be a ‘NOP’.

3.4.1.1 Characteristics of the PLL Interface

When connecting a crystal to the on-chip PLL interface pins (i.e. MOSCIN and MOSCOUT), the crystal and circuit should conform to the following requirements:

• The 3.6864 MHz frequency should be created by the crystals fundamental tone (i.e., it should be a fundamental mode crystal).

• A start-up resistor is not necessary, since one is provided internally.

• Start-up loading capacitors may be placed on each side of the external crystal and ground. Their value should be in the range of 10 pF. However, their values should be selected based

upon the crystal specifications. The total sum of the capacitance of the traces between the EP7209’s clock pins, the capacitors, and the crystal leads should be subtracted from the crystal’s specifications when determining the values for the loading capacitors.

• The crystal should have a maximum 100 ppm frequency drift over the chip’s operating temperature range.

Alternatively, a digital clock source can be used to drive the MOSCIN pin of the EP7209. With this approach, the voltage levels of the clock source should match that of the Vdd supply for the EP7209’s pads (i.e. the supply voltage level used to drive all of the non-Vdd core pins on the EP7209). The output clock pin (i.e., MOSCOUT) should be left floating.

3.4.2 External Clock Input (13 MHz)

An external 13 MHz crystal oscillator can be used to drive all of the EP7209. When selected the ARM720T and the address/data buses both get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different frequencies than in the PLL mode. In this configuration, the PLL will not be used at all.

NOTE: When operating at 13 MHz, the

CLKCTL[1:0] bits should not be changed from their default value of ‘00’.

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EP7209

13 MHz

CLKEN

Figure 4. CLKEN Timing Entering the St andby State

EXPCLK

(internal)

RUN

CLKEN

Interrupt /

WAKEUP

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Figure 5. CLKEN Timing Entering the Standby State

EP7209

3.4.3 Dynamic Clock Switching When in the PLL Clocking Mode

The clock frequency used for the CPU and the buses is controlled by programming the CLKC TL[1:0] bits in the SYSCON3 register. When this occurs, the state controller switches from the current to th e new clock frequency as soon as possible without causing a glitch on the clock signals. The glitchfree clock switching logic waits until the clock that is currently in use and the newly programmed clock source are both low, and then switches from the previous clock to the new clock without a glitch on the clocks.

3.5 Interrupt Controller

When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled.

Table 8 shows the priority order of all the excep-

tions.

Priority Exception

Highest Reset

. Data Abort .FIQ .IRQ . Prefetch Abort

Lowest

Table 8. Exception Priority Handling

The EP7209 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. Of these, seventeen are mapped to the IRQ input and five sources are mapped to the FIQ input.

Undefined Instruction,

Software Interrupt

FIQs have a higher priority than IRQs. If two interrupts are received from within the same group (IRQ or FIQ), the order in which they are serviced must be resolved in software. The priorities are listed in

Table 9. All interrupts are level sensitive; that is,

they must conform to the following sequence.

1) The interrupting device (either external or internal) asserts the appropriate interrupt.

2) If the appropriate bit is se t in the interrupt mask register, then either a FIQ or an IRQ will be asserted by the interrupt controller. (A description for each bit in this register can be found in INTSR1 Interrupt Status Register 1).

3) If interrupts are enabled the processor will jump to the appropriate address.

4) Interrupt dispatch software reads the interrupt status register to establish the source(s) of the interrupt and calls the appropriate interrupt service routine(s).

5) Software in the interrupt service routine will clear the interrupt source by some action specific to the device requesting the interrupt (i.e., reading the UART RX register).

The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be serviced in a similar way. Alternately, it may re turn to the interrupt dispatch code, which can check for any more pending interrupts and dispatch them accordingly. The “End of Interrupt” type interrupts are latched. All other interrupt sources (i.e., external interrupt source) must be held active until its respective service routine starts executing. See ‘End of Interrupt’ Locations for more details.

Table 9, Table 10 and Table 11 show the names

and allocation of interrupts in the EP7209.

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EP7209

Interrupt Bit in INTMR1 and

INTSR1

FIQ 0 EXTFIQ FIQ 1 BLINT FIQ 2 WEINT FIQ 3 MCINT IRQ 4 CSINT IRQ 5 EINT1 IRQ 6 EINT2 IRQ 7 EINT3 IRQ 8 TC1OI IRQ 9 TC2OI IRQ 10 RTCMI IRQ 11 TINT IRQ 12 UTXINT1 IRQ 13 URXINT1 IRQ 14 UMSINT IRQ 15 SSEOTI

Table 9. Interrupt Allocation in the First Interrupt Register

Name Comment

External fast interrupt input (nEXTFIQ pin) Battery low interrupt Tick Watchdog expired interrupt Media changed interrupt Codec sound interrupt External interrupt input 1 (nEINT[1] pin) External interrupt input 2 (nEINT[2] pin) External interrupt input 3 (EINT[3] pin) TC1 underflow interrupt TC2 underflow interrupt RTC compare match interrupt 64 Hz tick interrupt Internal UART1 transmit FIFO empty interrupt Internal UART1 receive FIFO full interrupt Internal UART1 modem status changed interrupt Synchronous serial interface 1 end of transfer interrupt

Interrupt Bit in INTMR2 and

Name Comment

INTSR2

IRQ 0 KBDINT IRQ 1 SS2RX IRQ 2 SS2TX IRQ 12 UTXINT2 IRQ 13 URXINT2

Table 10. Interrupt Allocation in the Second Interrupt Register

Interrupt Bit in INTMR3 and

INTSR3

FIQ 0 DAIINT

Table 11. Interrupt Allocation in the Third Interrupt Register

Key press interr upt Master/slave SSI 16 bytes received Master/slave SSI 16 bytes transmitted UART2 transmit FIFO empty interrupt UART2 receive FIFO full interrupt

Name Comment

DAI interface interrupt

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EP7209

3.5.1 Interrupt Latencies in Different States

3.5.1.1 Operating State

The ARM720T processor checks for a low level on its FIQ and IRQ inputs at the end of each instruction. The interrupt latency is therefore directly related to the amount of time it takes to complete execution of the current inst ruction whe n the interrupt condition is detected. First, there is a one to two clock cycle synchronization penalty. For the case where the EP7209 is operating at 13 MHz with a 16-bit external me mory system, and instruction sequence stored in one wait state FLASH memory, the worst case interrupt latency is 251 clock cycles. This includes a delay for cache line fills for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x 240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress.

This would give a worst-case interrupt latency of about 19.3 µs for the ARM720T processor operating at 13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is increased by the maximum time required to pass through the deglitcher, which is approximately 125 µs (2 cycle of the 16.384 kHz clock derived from the RTC oscillator). This would create an absolute worst case latency of approximately 141 µs. If the ARM720T is run at 36 MHz or greater and/or 32 bit wide external memory, the 19.3 µs value will be reduced.

All the serial data transfer peripherals included in the EP7209 (except for the master-only SSI1) have local buffering to ensure a reasonable interrupt latency response requirement for the OS of 1 ms or less. This assumes that the maximum data rates described in this specification are complied with. If

the OS cannot meet this requirement, there will be a risk of data over/underflow occurring. Idle State

When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two clock cycles. However, there is still potentia lly up to 20 µsec latency as described in the first section above, unless the code is written to include at least two single cycle instructions immediately after the write to the IDLE register (in which c ase the latency drops to a few microseconds). This is important, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.

3.5.1.2 Standby State

In the Standby State, the latency will depend on whether the system clock is shut down and if the FASTWAKE bit in the SYSCON3 register is set. If the system is configured to run from the internal PLL clock, then the PLL will always be shut down when in the Standby State. In this case, if the FASTWAKE bit is cleared, then there will be a latency of between 0.125 sec to 0.25 sec. If the FASTWAKE bit is set, then there will be a latency of between 250 µsec to 500 µsec. If the system is running from the external clock (at 13 MHz), with the CLKENSL bit in SYSCON2 set to 0, then the latency will also be between 0.125 sec and 0.25 sec to allow an external oscillator to stabilize. In the case of a 13 MHz system where the clock is not disabled during the Standby State (CLKENSL = 1), then the latency will be the same as descri bed in the Idle State section above.

Whenever the EP7209 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripherals that are power-down from draining current. Also, the internal peripheral’s signals get set to their Reset State.

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EP7209

Table 12 summarizes the five external interrupt

sources and the effect they have on the processor interrupts.

3.6 EP7209 Boot ROM

The 128 bytes of on-chip Boot ROM contain a instruction sequence that initializes the device and then configures UART1 to receive 2048 bytes of serial data that will then be placed in the on-chip SRAM. Once the download is complete, execution jumps to the start of the on-chip SRAM. This would allow, for example, code to be downloaded to program system FLASH during a product’s manufacturing process. See Appendix A: Boot Code for details of the ROM Boot Code with com- ments to describe the stages of execution.

Selection of the Boot ROM option is determined by the state of the nMEDCHG pin during a power on reset. If nMEDCHG is high while nPOR is active, then the EP7209 will boot from an external memory device connected to CS[0] (normal boot mode). If nMEDCHG is low, then the boot will be from the on-chip ROM. Note that in both cases, following the de-assertion of power on reset, the EP7209 will be in the Standby State and requires a low-to-high

transition on the external WAKEUP pin in order to actually start the boot sequence.

The effect of booting from the on-chip Boot ROM is to reverse the decoding for all chip selects internally. Table 13 shows this decoding. The control signal for the boot option is latched by nPOR, which means that the remapping of addresses and bus widths will continue to apply until nPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM can be read back from address 0x00000000 onwards, and in normal state of operation the Boot ROM contents can be read back from address range 0x70000000.

Address Range Chip Select

0000.0000–0FFF.FFFF CS[7] (Internal only)

1000.0000–1FFF.FFFF CS[6] (Internal only)

2000.0000–2FFF.FFFF nCS[5]

3000.0000–3FFF.FFFF nCS[4]

4000.0000–4FFF.FFFF nCS[3]

5000.0000–5FFF.FFFF nCS[2]

6000.0000–6FFF.FFFF nCS[1]

7000.0000–7FFF.FFFF nCS[0]

Table 13. Chip Select Address Ranges After Boot From

On-Chip Boot ROM

Interrupt

nEXTFIQ Not deglitched; must be

nEINT1–2 N ot degl itc hed Worst case latency

EINT3 Not deglitched Worst case latency

nMEDCHG Deglitched by 16 kHz

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Input State Operating State

Worst case latency active for 20 µs to be detected

clock; must be active for at least 125 µs to be detected

of 20 µsec

Worst case latency

of 141 µsec

Table 12. External Interrupt Source Latencies

Latency

Idle State

Latency

Worst case 20 µsec: if only single cycle instructio ns, less than 1 µsec

As above As above

Worst case 80 µsec: if only single cycle instructions, 125 µsec

Including PLL/osc. settling time, approx.

0.25 sec when FASTWAKE = 0, or approx. 500 µsec when F ASTWAKE = 1, or = Idle State if in 13 MHz mode with CLKENSL set

As above (note difference if in 13 MHz mode with CLKENSL set)

Standby State Latency

EP7209

3.7 Memory and I/O Expansion Interface

Six separate linear memory or expansion segments are decoded by the EP7209, two of which can be reserved for two PC Card cards, each interfacing to a separate single CL-PS6700 device. Each segment is 256 Mbytes in size. Two additional segments (i.e., in addition to these six) are dedicated to the on-chip SRAM and the on-chip ROM. The on-chip ROM space is fully decoded, and the SRAM space is fully decoded up to the maximum size of the video frame buffer programmed in the LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded (i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of the six segments are configured to interface to a conventional SRAM-like interface, and can be individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute f rom 1 to 8 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait state sequential access feature is designed to support burst mode ROMs. For writable memory devices which use the nMWE pin, zero wait state sequential accesses are not permitted and one wait state is the minimum which should be programmed in the sequential field of the appropriate MEMCFG register. Bus cycles can also be extended using the EXPRDY input signal.

Page mode access is accomplished by setting SQAEN = 1, which enables accesse s of the form one random address followed by three sequential addresses, etc., while keeping nCS asserted. These sequential bursts can be up to four words long be-

fore nCS is released to allow DMA and refreshes to take place. This can significantly improve bus bandwidth to devices such as ROMs which support page mode. When SQAEN = 0, all accesses to memory are by random access without nCS being de-asserted between accesses. Again nCS is de-asserted after four consecutive accesses to allow DMAS.

Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC Card slot drivers). When either of these interfaces are enabled, the corresponding chip select (nCS4 and/or nCS5) becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 bit 5 determines the function of chip select nCS4 (i.e., CL-PS6700 interface or standard chip select functionality); bit 6 controls nCS5 in a similar way. There is no interaction between these bits.

For applications that require a display buffer smaller than 38,400 bytes, the on-chip SRAM can be used as the frame buffer.

The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on reset. These inputs are latched by the rising edge of nPOR to select the boot option.

PE[1] PE[0] Boot Block

(nCS0)

0032-bit 018-bit 1016-bit 1 1 Undefined

Table 14. Boot Options

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