CIRRUS LOGIC CY7C1370CV25, CY7C1372CV25 Service Manual

a b c d

查询CY7C1370CV25-167AC供应商

512K x 36/1M x 18 Pipelined SRAM

Features

• Pin-compatible and functionally equivalent to ZBT™

• Supports 250-MHz bus operations with zero wait states

— Available speed grades are 250, 225, 200 and 167

MHz

• Internally self-timed output buffer control to eliminate the need to use asynchronous OE

• Fully registered (inputs and outputs) for pipelined operation

• Byte Write capability

• Single 2.5V power supply

• Fast clock-to-output times

— 2.6 ns (for 250-MHz device)

— 2.8 ns (for 225-MHz device)

— 3.0 ns (for 200-MHz device)

— 3.4 ns (for 167-MHz device)

• Clock Enable (CEN

• Synchronous self-timed writes

• Available in 100 TQFP, 119 BGA, and 165 fBGA packages

• IEEE 1149.1 JTAG Boundary Scan

• Burst capability—linear or interleaved burst order

• “ZZ” Sleep Mode option and Stop Clock option

) pin to suspend operation

CY7C1370CV25

CY7C1372CV25

with NoBL™ Architecture

Functional Description

The CY7C1370CV25 and CY7C1372CV25 are 2.5V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively. They are designed to support unlimited true back-to-back Read/Write operations with no wait states. The CY7C1370CV25 and CY7C1372CV25 are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent Write/Read transitions. The CY7C1370CV25 and CY7C1372CV25 are pin compatible and functionally equivalent to ZBT devices.

All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN which when deasserted suspends operation and extends the previous clock cycle.

Write operations are controlled by the Byte Write Selects (BW

–BWd for CY7C1370CV25 and BWa–BWb for

CY7C1372CV25) and a Write Enable (WE

) input. All writes are

conducted with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE

, CE2, CE3) and an

) provide for easy bank selection and output three-state control. In order to avoid bus contention, the output drivers are synchronously three-stated during the data portion of a write sequence.

) signal,

Logic Block Diagram–CY7C1370CV25 (512K x 36)

A0, A1, A

MODE

CLK

ADV/LD

OE CE1 CE2 CE3

Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Document #: 38-05235 Rev. *C Revised June 03, 2004

ADDRESS

WRITE ADDRESS

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

SLEEP

CONTROL

ADV/LD

WRITE ADDRESS

D1D0Q1

BURST LOGIC

A1' A0'

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

U T

S E

R E G

S T

R S

INPUT

U T

T B

S T E E R

I N G

DQs

DQP

R S

a b

Logic Block Diagram-CY7C1372CV25 (1M x 18)

A0, A1, A

MODE

CLK

ADDRESS

WRITE ADDRESS

ADV/LD

WRITE ADDRESS

D1D0Q1

BURST LOGIC

CY7C1370CV25

CY7C1372CV25

A1' A0'

O U

T P

INPUT

N S

ADV/LD

OE CE1 CE2 CE3

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

READ LOGIC

Sleep

Control

WRITE

DRIVERS

MEMORY

ARRAY

INPUT

O U

T P

T A

B U

I N G

Selection Guide

CY7C1370CV25-250 CY7C1372CV25-250

Maximum Access Time

Maximum Operating Current

Maximum CMOS Standby

2.6 2.8 3.0 3.4 ns

350 325 300 275 mA

70 70 70 70 mA

Current

Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.

CY7C1370CV25-225 CY7C1372CV25-225

CY7C1370CV25-200 CY7C1372CV25-200

DQs DQP DQP

CY7C1370CV25-167 CY7C1372CV25-167 Unit

Document #: 38-05235 Rev. *C Page 2 of 27

Pin Configurations

100-pin TQFP Packages

CY7C1370CV25

CY7C1372CV25

DQPc

DQc DQc

DDQ

DQc DQc

DDQ

DQc

NC V

DQd DQd

DDQ

DQd DQd DQd

DQd

DDQ

DQd DQd

DQPd

1CE2

BWd

BWc

BWa

VDDV

CLKWECEN

BWb

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

CY7C1370CV25

(512K × 36)

17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

ADV/LD

DDQ SS

DDQ

DQa

DDQ

DQPa

NC NC NC

DDQ

NC DQb DQb

DDQ

DQb DQb

DDQ

DQb DQb

DQPb

DDQ

DQPb

DQb

65 64

DQa

57 56

DQa

52 51

1CE2

100999897969594939291908988878685848382

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

31323334353637383940414243444546474849

bBWa

VDDV

CLKWECEN

CY7C1372CV25

(1M × 18)

ADV/LD

DDQ

DQP

DQa DQa V

DDQ

DQa DQa V

NC V

ZZ DQa DQa V

DDQ

DQa DQa NC NC V

DDQ

NC NC NC

73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

AAA

MODE

1A0

E(288)

E(144)

E(72)

E(36)

AAA

MODE

1A0

E(144)

E(288)

AAA

E(72)

E(36)

Document #: 38-05235 Rev. *C Page 3 of 27

Pin Configurations (continued)

B C

F G

R T

119-ball BGA Pinout

CY7C1370CV25 (512K × 36) – 14 × 22 BGA

2345 671

DDQ

AA AAAV

DQP

DQd

DQP

E(72)

TMS

MODE

ADV/LD

NC DQP

WE V

CLK

CEN

A0 V

TCK

ACE3NC

AANC

NC V

DQP

E(36)

NCTDI TDO V

CY7C1370CV25

CY7C1372CV25

DDQ

NCA

DDQ

CY7C1372CV25 (1M x 18)–14 x 22 BGA

2345671

B C D

E F

G H J

L M N

T U

DDQ

E(72)

DDQ

AA AAAV

NCDQ

DQP

TMS

MODE

ADV/LD

NC NCDQP

AVSSNC

CLK

NC NC

CEN

A0 V

E(36)

AANC

NC V

TCK

NCV

NC V

NCTDI TDO V

DDQ

Document #: 38-05235 Rev. *C Page 4 of 27

Pin Configurations (continued)

234 5671

B C D

E F G

H J K L

M N P

B C D

G H

M N P

E(288)

DQP

MODE

E(288)

NC V

NC NC

DQP

MODE

NC / V

E(72)

E(36)

234 5671

NC / V

E(72)

E(36)

CE2

165-Ball fBGA Pinout

CY7C1370CV25 (512K × 36) – 13 × 15 fBGA

V V V

TDI

TMS

DDQ

CY7C1372CV25 (1M × 18) – 13 × 15 fBGA

TDI

TMS

DDQ

NC BW

CLK

CEN

TDO

TCKA0

CLK

CEN

TDO

TCKA0

CY7C1370CV25

CY7C1372CV25

891011

DDQ

ADV/LD

891011

DDQ

ADV/LD

E(144)

NC DQP

DQP

E(144)

NC DQP

NC NC

NCV

Document #: 38-05235 Rev. *C Page 5 of 27

CY7C1370CV25

CY7C1372CV25

Pin Definitions

Name I/O Type Pin Description

A0, A1, A Input-

Synchronous

BW BW

a, BWb c, BWd

Input-

Synchronous

Input-

Synchronous

ADV/LD

Input-

Synchronous

CLK Input-

Clock

Input-

Synchronous

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

CEN

Input-

Synchronous

DQ DQ DQ DQ

DQP DQP

a b c d

DQP

I/O-

Synchronous

I/O-

Synchronous

MODE Input Strap Pin Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved

TDO JTAG serial output

Synchronous

TDI JTAG serial input

Synchronous

TMS Test Mode Select

Synchronous

TCK JTAG-Clock Clock input to the JTAG circuitry.

DDQ

Power Supply Power supply inputs to the core of the device.

I/O Power Supply Power supply for the I/O circuitry.

Ground Ground for the device. Should be connected to ground of the system. NC – No connects. This pin is not connected to the die. NC / VDD – Can either be left unconnected or connected to V

Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK.

Byte Write Select Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled on the rising edge of CLK. BW DQb and DQPb, BWc controls DQc and DQPc, BWd controls DQd and DQPd.

controls DQa and DQPa, BWb controls

Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW. This signal must be asserted LOW to initiate a write sequence.

Advance/Load Input used to advance the on-chip address counter or load a new address. When HIGH (and CEN is asserted LOW) the internal burst counter is

advanced. When LOW, a new address can be loaded into the device for an access. After being deselected, ADV/LD should be driven LOW in order to load a new address.

Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN

. CLK is only recognized if CEN is active LOW.

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3 to select/deselect the device.

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE3 to select/deselect the device.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE1 and CE2 to select/deselect the device.

Output Enable, active LOW. Combined with the synchronous logic block inside the device to control the direction of the I/O pins. When LOW, the I/O pins are allowed to behave as outputs. When deasserted HIGH, I/O pins are three-stated, and act as input data pins. OE is masked during the data portion of a write sequence, during the first clock when emerging from a deselected state and when the device has been deselected.

Clock Enable Input, active LOW. When asserted LOW the clock signal is recognized by the SRAM. When deasserted HIGH the clock signal is masked. Since deasserting CEN does not deselect the device, CEN can be used to extend the previous cycle when required.

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by A direction of the pins is controlled by OE and the internal control logic. When OE is

during the previous clock rise of the read cycle. The

[17:0]

asserted LOW, the pins can behave as outputs. When HIGH, DQa–DQd are placed in a three-state condition. The outputs are automatically three-stated during the data portion of a write sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of OE.

Bidirectional Data Parity I/O lines. Functionally, these signals are identical to DQ During write sequences, DQPa is controlled by BWa, DQPb is controlled by BWb, DQPc

[31:0]

is controlled by BWc, and DQPd is controlled by BWd.

burst order. Pulled LOW selects the linear burst order. MODE should not change states during operation. When left floating MODE will default HIGH, to an interleaved burst order.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.

Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK.

This pin controls the Test Access Port state machine. Sampled on the rising edge

of TCK.

Must not be connected to V

DD.

SS.

Document #: 38-05235 Rev. *C Page 6 of 27

CY7C1370CV25

CY7C1372CV25

Pin Definitions (continued)

Name I/O Type Pin Description

E(36,72, 144, 288) – These pins are not connected. They will be used for expansion to the 36M, 72M, 144M

ZZ Input-

Asynchronous

and 288M densities.

ZZ “sleep” Input. This active HIGH input places the device in a non-time critical “sleep” condition with data integrity preserved. During normal operation, this pin can be connected to Vss or left floating.

Functional Overview

The CY7C1370CV25 and CY7C1372CV25 are synchronous-pipelined Burst NoBL SRAMs designed specifically to eliminate wait states during Write/Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock signal is qualified with the Clock Enable input signal (CEN signal is not recognized and all internal states are maintained. All synchronous operations are qualified with CEN. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t

) is 3.0 ns (200-MHz device).

Accesses can be initiated by asserting all three Chip Enables (CE

, CE2, CE3) active at the rising edge of the clock. If Clock

Enable (CEN

) is active LOW and ADV/LD is asserted LOW, the address presented to the device will be latched. The access can either be a read or write operation, depending on the status of the Write Enable (WE conduct byte write operations.

Write operations are qualified by the Write Enable (WE writes are simplified with on-chip synchronous self-timed write circuitry.

Three synchronous Chip Enables (CE asynchronous Output Enable (OE All operations (Reads, Writes, and Deselects) are pipelined. ADV/LD should be driven LOW once the device has been deselected in order to load a new address for the next operation.

Single Read Accesses

A read access is initiated when the following conditions are satisfied at clock rise: (1) CEN and CE signal WE

are ALL asserted active, (3) the Write Enable input

is deasserted HIGH, and (4) ADV/LD is asserted LOW. The address presented to the address inputs is latched into the Address Register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the rising edge of the next clock the requested data is allowed to propagate through the output register and onto the data bus within 3.2 ns (200-MHz device) provided OE clock of the read access the output buffers are controlled by OE

and the internal control logic. OE must be driven LOW in order for the device to drive out the requested data. During the second clock, a subsequent operation (Read/Write/Deselect) can be initiated. Deselecting the device is also pipelined. Therefore, when the SRAM is deselected at clock rise by one of the chip enable signals, its output will three-state following the next clock rise.

). If CEN is HIGH, the clock

). BW

can be used to

[a:d]

). All

, CE2, CE3) and an

) simplify depth expansion.

is asserted LOW, (2) CE1, CE2,

is active LOW. After the first

Burst Read Accesses

The CY7C1370CV25 and CY7C1372CV25 have an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD

must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above. The sequence of the burst counter is determined by the MODE input signal. A LOW input on MODE selects a linear burst mode, a HIGH selects an interleaved burst sequence. Both burst counters use A0 and A1 in the burst sequence, and will wrap-around when incremented sufficiently. A HIGH input on ADV/LD

will increment the internal burst counter regardless of the state of chip enables inputs or WE

. WE is latched at the beginning of a burst cycle. Therefore, the type of access (Read or Write) is maintained throughout the burst sequence.

Single Write Accesses

Write access are initiated when the following conditions are satisfied at clock rise: (1) CEN and CE is asserted LOW. The address presented to A0–A16 is loaded

are ALL asserted active, and (3) the write signal WE

is asserted LOW, (2) CE1, CE2,

into the Address Register. The write signals are latched into the Control Logic block.

On the subsequent clock rise the data lines are automatically three-stated regardless of the state of the OE allows the external logic to present the data on DQ (DQ for CY7C1372CV25). In addition, the address for the subse-

a,b,c,d

/DQP

for CY7C1370CV25 and DQ

a,b,c,d

input signal. This

and DQP

/DQP

a,b

quent access (Read/Write/Deselect) is latched into the Address Register (provided the appropriate control signals are asserted).

On the next clock rise the data presented to DQ

a,b,c,d

/DQP

(DQ CY7C1372CV25) (or a subset for byte write operations, see

for CY7C1370CV25 & DQ

a,b,c,d

a,b

/DQP

and DQP

for

a,b

Write Cycle Description table for details) inputs is latched into the device and the write is complete.

The data written during the Write operation is controlled by BW (BW CY7C1372CV25) signals. The CY7C1370CV25/

for CY7C1370CV25 and BW

a,b,c,d

a,b

for

CY7C1372CV25 provides byte write capability that is described in the Write Cycle Description table. Asserting the Write Enable input (WE (BW

) input will selectively write to only the desired bytes. Bytes

) with the selected Byte Write Select

not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Byte write capability has been included in order to greatly simplify Read/Modify/Write sequences, which can be reduced to simple byte write operations.

Because the CY7C1370CV25 and CY7C1372CV25 are common I/O devices, data should not be driven into the device while the outputs are active. The Output Enable (OE deasserted HIGH before presenting data to the DQ

) can be

and DQP

Document #: 38-05235 Rev. *C Page 7 of 27

CY7C1370CV25

CY7C1372CV25

a,b,c,d

/DQP

(DQ for CY7C1372CV25) inputs. Doing so will three-state the output drivers. As a safety precaution, DQ DQP CY7C1372CV25) are automatically three-stated during the

for CY7C1370CV25 and DQ

a,b,c,d

for CY7C1370CV25 and DQ

a,b,c,d

a,b

and DQP (DQ

/DQP

a,b

/DQP

a,b,c,d

for

a,b

data portion of a write cycle, regardless of the state of OE.

Burst Write Accesses

The CY7C1370CV25/CY7C1372CV25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four WRITE operations without reasserting the address inputs. ADV/LD

must be driven LOW in order to load the initial address, as described in the Single Write Access section above. When ADV/LD is driven HIGH on the subsequent clock rise, the chip enables (CE CE

) and WE inputs are ignored and the burst counter is incre-

mented. The correct BW BW

for CY7C1372CV25) inputs must be driven in each

a,b

cycle of the burst write in order to write the correct bytes of

(BW

for CY7C1370CV25 and

a,b,c,d

, CE2, and

data.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed.

considered valid nor is the completion of the operation

a,b

guaranteed. The device must be deselected prior to entering the “sleep” mode. CE

for the duration of t

, CE2, and CE3, must remain inactive

after the ZZ input returns LOW.

ZZREC

Interleaved Burst Address Table (MODE = Floating or V

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00

Second

Address

)

Third

Address

Linear Burst Address Table (MODE = GND)

First

Address

A1,A0 A1,A0 A1,A0 A1,A0

00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10

Second

Address

Third

Address

Fourth

Address

Fourth

Address

Accesses pending when entering the “sleep” mode are not

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min. Max Unit

DDZZ

ZZS

ZZREC

ZZI

RZZI

Truth Table

Operation

Deselect Cycle None H L L X X X L L-H Three-State Continue Deselect Cycle None X L H X X X L L-H Three-State Read Cycle (Begin Burst) External L L L H X L L L-H Data Out (Q) Read Cycle (Continue Burst) Next X L H X X L L L-H Data Out (Q) NOP/Dummy Read (Begin Burst) External L L L H X H L L-H Three-State Dummy Read (Continue Burst) Next X L H X X H L L-H Three-State Write Cycle (Begin Burst) External L L L L L X L L-H Data In (D) Write Cycle (Continue Burst) Next X L H X L X L L-H Data In (D) NOP/WRITE ABORT (Begin Burst) None L L L L H X L L-H Three-State WRITE ABORT (Continue Burst) Next X L H X H X L L-H Three-State IGNORE CLOCK EDGE (Stall) Current X L X X X X H L-H – SNOOZE MODE None X H X X X X X X Three-State

Notes:

1. X = “Don't Care”, 1 = Logic HIGH, 0 = Logic LOW, CE signifies that the desired byte write selects are asserted, see Write Cycle Description table for details.

2. Write is defined by WE

3. When a write cycle is detected, all I/Os are tri-stated, even during byte writes.

4. The DQ and DQP pins are controlled by the current cycle and the OE

= H inserts wait states.

5. CEN

6. Device will power-up deselected and the I/Os in a tri-state condition, regardless of OE

7. OE

is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles.During a read cycle DQs and DQP

is inactive or when the device is deselected, and DQs=data when OE is active.

Snooze mode standby current ZZ > VDD − 0.2V 60 mA Device operation to ZZ ZZ > VDD − 0.2V 2t ZZ recovery time ZZ < 0.2V 2t

CYC

ZZ active to snooze current This parameter is sampled 2t ZZ Inactive to exit snooze current This parameter is sampled 0 ns

[1, 2, 3, 4, 5, 6, 7]

Address

Used CE ZZ ADV/LD WE BWxOE CEN CLK DQ

stands for ALL Chip Enables active. BWx = 0 signifies at least one Byte Write Select is active, BWx = Valid

and BW

. See Write Cycle Description table for details.

[a:d]

signal.

[a:d]

CYC

ns ns

CYC

= Three-state when

Document #: 38-05235 Rev. *C Page 8 of 27

CY7C1370CV25

CY7C1372CV25

Partial Write Cycle Description

Function (CY7C1370CV25)

[1, 2, 3, 8]

Read H X X X X

Write – No bytes written L H H H H

Write Byte a – (DQa and DQPa) LHHHL

Write Byte b – (DQ

and DQPb)LHHLH

Write Bytes b, a L H H L L

Write Byte c – (DQ

and DQPc)LHLHH

Write Bytes c, a L H L H L

Write Bytes c, b L H LL L H

Write Bytes c, b, a L H L L L

Write Byte d – (DQ

and DQPd)LLHHH

Write Bytes d, a L L H H L

Write Bytes d, b LLHLH

Write Bytes d, b, a L L H L L

Write Bytes d, c L L L H H

Write Bytes d, c, a L L L H L

Write Bytes d, c, b L L L L H

Write All Bytes L L L L L

Function (CY7C1372CV25) WE

Read H x x

Write – No Bytes Written L H H

Write Byte a – (DQ

Write Byte b – (DQ

and DQPa)LHL

and DQPb)LLH

Write Both Bytes L L L

IEEE 1149.1 Serial Boundary Scan (JTAG)

The CY7C1370CV25/CY7C1372CV25 incorporates a serial boundary scan Test Access Port (TAP) in the BGA package only. The TQFP package does not offer this functionality. This port operates in accordance with IEEE Standard 1149.1-1900, but does not have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note that the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC standard 3.3V or 2.5V I/O logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (V

) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately be connected to V be left unconnected. Upon power-up, the device will come up

through a pull-up resistor. TDO should

Test Access Port–Test Clock

The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this pin unconnected if the TAP is not used. The pin is pulled up internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see the TAP Controller State Diagram. TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the Most Significant Bit (MSB) on any register.

in a reset state which will not interfere with the operation of the device.

Note:

8. Table only lists a partial listing of the byte write combinations. Any combination of BW

is valid. Appropriate write will be done based on which byte write is active.

[a:d]

Document #: 38-05235 Rev. *C Page 9 of 27

+ 18 hidden pages

CIRRUS LOGIC CY7C1370CV25, CY7C1372CV25 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual