Cirrus Logic CS98100-CM Datasheet
CS98100
DVD Processor for Low Cost DVD Players
Features
l 32-Bit RISC Processor, supported by RTOS, C/C++
compilers
l 32-bit DSP capable of AC-3, MPEG, DTS, MP3, and WMA
l Progressive Scan (480p) with 3:2 pull down support or
Interlaced (PAL/NTSC) video encoding, both modes with
Macrovision encoding, via three 10-bit Video DACs
l Serial DVD data interface for direct connection to low cost
(track buffer-less) DVD loader
l Flexible interface connects ATAPI, local bus or
microcontroller-less DVD loaders without external logic
l MPEG decoder supports VCD, VCD 3.0, SVCD, DVD video
standards
l Advanced subpicture unit handles DVD and SVCD, and
PAL<->NTSC scaling
l High quality video scaling for zoom and NTSC/PAL
conversion
l 4-bit multi-region OSD and special video effects
l Simultaneous 8 channels PCM audio output and IEC-958.
l 2-Channel PCM audio input for high-end karaoke
applications
l Three serial control/status ports
l Low-power, ~0.5 W power dissipation
Description
Building on innovative, market-leading technology, Cirrus
Logic presents the most complete DVD processor solution available: CS98100. The CS98100 provides the highperformance typical of Cirrus Logic integrated circuits,
and on-chip integration that allows for seamless integration of functions. Among the integrated functions in this
system-on-chip architecture is
encoder with a triple 10-bit video DAC, allowing for a significant decrease in system cost.
Not only is the CS98100 equipped with an intuitive onscreen display and user interface, but the CS98100 also
offers progressive output, DTS decoding, HDCD support, and MP3 plus WMA decoding. Other advanced
features include karaoke down-mix. The low cost extended feature set makes the CS98100 ideal for both
low-end and high-end system manufacturers.
ORDERING INFORMATION
CS98100-CM 0° to 70° C 208-pin MQFP
a high quality NTSC/PAL
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2002
(All Rights Reserved)
DS552PP4
JUL ‘02
1
TABLE OF CONTENTS
nformation being relied on is current and
bject to the PRC Foreign Trade Law
n this document may be trademarks
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................5
1.1 AC and DC Parametric Specifications ...............................................................................5
1.1.1 Absolute Maximum Rating .................................................................................... 5
1.1.2 Recommended Operating Conditions ...................................................................5
1.1.3 Electrical Characteristics .......................................................................................5
1.2 AC Characteristics .............................................................................................................7
1.2.1 ATAPI Interface .....................................................................................................7
1.2.2 SDRAM Interface .................................................................................................. 8
1.2.3 DVD Serial Interface Timing ................................................................................11
1.2.4 Digital Video Interface Timing .............................................................................12
1.2.5 Digital Audio Interface Timing .............................................................................13
1.2.6 ROM/NVRAM Interface ....................................................................................... 15
1.2.7 Miscellaneous Timings ........................................................................................17
2. TYPICAL APPLICATION ........................................................................................................18
2.1 CS98100 Device Summary .............................................................................................18
3. FUNCTIONAL DESCRIPTION ...............................................................................................20
3.1 RISC Processor ...............................................................................................................20
3.2 DSP Processor ................................................................................................................20
3.3 Memory Control ...............................................................................................................20
3.4 Dataflow Control (DMA) ................................................................................................... 20
3.5 System Control Functions ................................................................................................ 20
3.6 DVD/ATAPI Interface .......................................................................................................21
3.7 Serial DVD Interface ........................................................................................................21
3.8 MPEG Video Decoding .................................................................................................... 21
3.9 Audio Processing .............................................................................................................21
3.10 Video Processing ........................................................................................................... 22
3.11 Video Encoder ...............................................................................................................22
4. MEMORY MAP AND REGISTERS .........................................................................................23
4.1 Processor Memory Map ................................................................................................... 23
CS98100
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product information
describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained
in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express
or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that i
complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent
infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information,
Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus
owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect
to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional
purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material
and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be obtained
from the competent authorities of the Chinese Government if any of the products or technologies described in this material is su
and is to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE
SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names i
or service marks of their respective owners.
Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I
components in a standard I2C system.
2
2
C Patent Rights to use those
4.2 Host Port Memory Map .................................................................................................... 23
4.3 Internal IO Space Map ..................................................................................................... 24
4.4 CS98100 Register Space ................................................................................................ 24
5. PIN DESCRIPTIONS .............................................................................................................. 37
6. PIN ASSIGNMENTS ............................................................................................................... 38
6.1 Miscellaneous Pins .......................................................................................................... 46
6.2 Serial Interface ................................................................................................................ 47
6.3 SDRAM Interface ............................................................................................................. 48
6.4 ROM/NVRAM Interface ................................................................................................... 49
6.5 Digital Video Output Interface .......................................................................................... 50
6.6 Audio Output/Input Interface ............................................................................................ 51
6.7 Host Master/ATAPI Interface ........................................................................................... 52
6.8 DVD I/O Channel Interface .............................................................................................. 53
6.9 DVD Serial Data Interface ............................................................................................... 54
6.10 Video Encoder Interface ................................................................................................ 55
6.11 General Purpose Input/Output (GPIO) .......................................................................... 56
6.12 Power and Ground ........................................................................................................ 57
7. 208 PIN MQFP PACKAGE SPECIFICATIONS ...................................................................... 58
LIST OF FIGURES
CS98100
Figure 1. ATAPI Interface Timing Diagram..................................................................................... 7
Figure 2. SDRAM Refresh Transaction........................................................................................... 8
Figure 3. SDRAM Burst Read Transaction..................................................................................... 9
Figure 4. SDRAM Burst Write Transaction ..................................................................................... 9
Figure 5. CS98100 SDRAM Read and Write................................................................................ 10
Figure 6. CS98100 DVD Serial Interface Timing Diagram............................................................ 11
Figure 7. CS98100 Digital Video Interface Timing Diagram ......................................................... 12
Figure 8. Digital Audio In Timing Diagram .................................................................................... 13
Figure 9. Digital Audio Out Timing Diagram.................................................................................. 14
Figure 10. ROM/NVRAM Reading Timing .................................................................................... 15
Figure 11. ROM/NVRAM Write Timing ......................................................................................... 16
Figure 12. Miscellaneous Timings................................................................................................. 17
Figure 13. CS98100 Application ................................................................................................... 18
Figure 14. CS98100 Pin Layout.................................................................................................... 37
Figure 15. CS98100 208-Pin MQFP Package Drawing................................................................ 58
LIST OF TABLES
Table 1. ATAPI Interface Characteristics........................................................................................ 7
Table 2. SDRAM Interface Characteristics ..................................................................................... 8
Table 3. CS98100 DVD Interface Characteristics......................................................................... 11
Table 4. CS98100 Digital Video Interface Characteristics............................................................ 12
Table 5. Digital Audio In Characteristics....................................................................................... 13
Table 6. Digital Audio Out Characteristics .................................................................................... 14
Table 7. RAM/NVROM Characteristics......................................................................................... 15
Table 8. Miscellaneous Timing Characteristics............................................................................. 17
Table 9. Memory Map - RISC Processor...................................................................................... 23
Table 10. Host Port Memory Map................................................................................................. 23
Table 11. Internal IO Space Map.................................................................................................. 24
Table 12. CS98100 Register Map and Blocks.............................................................................. 24
Table 13. CS98100 Registers....................................................................................................... 25
3
CS98100
Table 14. Pin Type and Direction Legend.....................................................................................37
Table 15. Pin Assignments............................................................................................................38
Table 16. Miscellaneous Interface Pins.........................................................................................46
Table 17. Serial Interface Pin Assignments ..................................................................................47
Table 18. SDRAM Interface Pin Assignments...............................................................................48
Table 19. ROM/NVRAM Interface Pin Assignments ..................................................................... 49
Table 20. Video Output Interface Pin Assignments.......................................................................50
Table 21. Audio Output Interface Pin Assignments.......................................................................51
Table 22. Host Master Interface Pin Assignments........................................................................ 52
Table 23. DVD I/O Channel Interface Pin Assignments................................................................53
Table 24. DVD Serial Data Interface Pin Assignments................................................................. 54
Table 25. Video Encoder Interface Pin Assignments....................................................................55
Table 26. General Purpose I/O Interface Pin Assignments...........................................................56
Table 27. Power and Ground........................................................................................................57
4
1. CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS
(AGND, DGND=0V, all voltages with respect to 0V)
1.1.1 ABSOLUTE MAXIMUM RATING
Symbol Description Min Max Unit
CS98100
VDD
VDD
V
I
I
I
I
O
T
SOL
T
VSOL
T
STOR
T
AMB
P
total
IO
CORE
Power Supply Voltage on I/O ring -0.5 4.6 Volts
Power Supply Voltage on core logic and PLL -0.5 2.5 Volts
Digital Input Applied Voltage (power applied) -0.5 5.5 Volts
Digital Input Forced Current -10 10 mA
Digital Output Forced Current -50 50 mA
Lead Soldering Temperature 260
Vapor Phase Soldering Temperature 235
Storage Temperature (no power applied) -40 125
Ambient Temperature (power applied) 0 70
o
C
o
C
o
C
o
C
Total Power consumption 2 W
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to
the device. Cirrus Logic recommends that CS98000 devices operate at the settings described in the next
table.
1.1.2 RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
Supply Voltage, IO V
Supply Voltage, core and PLL V
Ambient Temperature (power applied) T
1.1.3 ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units
Power Supply
Supply Voltage, IO V
Supply Voltage, core and PLL V
Supply Current, IO I
Supply Current, core and PLL I
Digital Pins
Input Voltage, High V
Input Voltage, Low V
DD
DD
DD
DD
Normal Operating 45 mA
Normal Operating 210 mA
IH
IL
DD
DD
AMB
3.0 3.3 3.6 Volts
1.62 1.8 1.98 Volts
0 25 70
o
C
3.0 3.3 3.6 Volts
1.62 1.8 1.98 Volts
2.2 Volts
0.8 Volts
5
CS98100
Parameter Symbol Conditions Min Typ Max Units
Input Current I
Input Pull up/down resistor R
Output Voltage, High V
Output Voltage, Low V
High-Z-state Leakage I
IN
I
OH
OL
OZ
Analog Video Pins
Full Scale Current I
Output Voltage Range V
DAC to DAC matching
1
Output Voltage Range V
FS
IO
MAT 2 %
out
Differential Gain DG 1 %
Differential Phase DP 0.5 deg
Signal to Noise SNR 74 dB
Chrominance AM Noise AM 80 dB
Chrominance PM Noise PM 75 dB
1.
Only applies each set of three.
V
= V
IN
DD
or V
SS
-1 +1 µA
75 KΩ
@ buffer rating 2.4 Volts
@ buffer rating 0.4 Volts
V
= VSS or V
OUT
DD
-1 +1 µA
RL = 37.5 Ω 34 mA
RL = 37.5 Ω 1.28 Volts
RL= 37.5Ω 1.28 Volts
6
CS98100
1.2 AC CHARACTERISTICS
(TA= 25°C; VDD_PLL=VDD_CORE=1.8 V±10%, VDD_IO=3.3 V±10%)
1.2.1 ATAPI Interface
The CS98100 can interface with ATAPI-type slave loader gluelessly. Figure1 illustrates a read ATAPI
transaction and a write ATAPI transaction. PIO mode 4 is implemented for sufficient data transfer rate between ATAPI device and the CS98100.
See Table1 for the ATAPI symbols and characterization data.
Symbol Description Min Typ Max Unit
t
acyc
t
aavr
t
ah
t
arww
t
arec
t
awsu
t
awh
t
ardsu
t
arddh
t
ardts
t
arsu
t
arh
1
1
Cycle Time 87 ns
Address Valid to HMRD-/HMWR- Setup 7 ns
Address Hold from HMRD-/HMWR Setup 8 ns
H_RD/H_WR Pulse Width 58 ns
H_RD/H_WR Recovery Time 19 ns
H_WR Data Setup 20 ns
H_WR Data Hold 4 ns
H_RD Data Setup 20 ns
H_RD Data hold 0 ns
H_RD Data three-state 7 ns
H_RDY Setup Time 14 ns
H_RDY Hold Time 0 ns
H_A[2:0] ,
H_CS[3:0]
H_RD/H_WR
H_D[15:0](WRITE)
H_D[15:0](READ)
H_RDY(deasserted
before tarsu)
H_RDY(asserted
before tarsu)
Table 1. ATAPI Interface Characteristics
1.
Values are guaranteed by design only
t aavr
Figure 1. ATAPI Interface Timing Diagram
tarsu
tarww
tacyc
tardsu
tarh
tarddh
t ah
tarec
tawhtawsu
tardts
7
CS98100
1.2.2 SDRAM Interface
The CS98100 interfaces with either SDRAM or SGRAM, for high data bandwidth transfer. Figure5 and
Table2 show the interface pin timing. Figure2 shows the refresh cycle performed by the CS98100.
Figure3 shows a burst read (length = 8) transaction, while Figure4 shows a burst write (length=8) trans-
action. In both Figure3 and Figure4, CAS latency is programmed to 3.
Symbol Description Min Typ Max Unit
t
mco
t
mper
t
mdow
t
mhw
t
msur
t
msurd
t
mhr
t
mhrd
1
1
1
Output Delay from DR_CKO active edge 9 ns
DR_CKO Period 11 12.2 ns
DR_D[31:0] delay from DR_CKO 9.1 ns
DR_D[31:0] valid time after DR_CKO 1.5 ns
DR_D[31:0] setup to DR_CKO 3.9 ns
1
DR_D[31:0] setup to DR_CKO with delay 4.3 ns
DR_D[31:0] hold time after DR_CKO 1.85 ns
DR_D[31:0] hold time after DR_CKO with
1.3 ns
delay
1.
Delay is programmable by selecting the DRAM_Input_Speed bit of the Command Register(0x000)
DR_CKO
DR_A[11:0]
DR_BS_N
DR_RAS_N
DR_CAS_N
DR_WE_N
DR_D[31:0]
DR_DQM_[3:0]
DR_AP
Table 2. SDRAM Interface Characteristics
Figure 2. SDRAM Refresh Transaction
8
DR_CKO
CS98100
DR_A_[11:0]
DR_CKE
DR_RAS_N
DR_CAS_N
DR_WE_N
DR_D[31:0]
DR_DQM[3:0]
DR_CKO
DR_A_[11:0]
DR_CKE
DR_RAS_N
R0
C0
C1
C2
C3 C4 C5 C6 C7
D0 D1 D2
0F
Figure 3. SDRAM Burst Read Transaction
R0
C0
C1
C2
C3 C4 C5 C6 C7
D3
D4 D5 D6 D7
F
DR_CAS_N
DR_WE_N
DR_D[31:0]
DR_DQM[3:0]
D0
D1 D2
D3
D4 D5 D6 D7
0F
Figure 4. SDRAM Burst Write Transaction
F
9
DR_CKO
DR_RAS_N,DR_CAS_N
DR_WE_N,DR_AP,DR_DQM[3:0],
DR_CKE,DR_A[11:0]
DR_D[31:0](WRITE)
DR_D[31:0](READ)
tmpertmco
tmdow
CS98100
tmhw
tmsur
tmhr
Figure 5. CS98100 SDRAM Read and Write
10
1.2.3 DVD Serial Interface Timing
Figure6 and Table3 illustrate the signal timing for the DVD serial interface input pins.
Symbol Description Min Typ Max Unit
t
dsckper
t
dsckl
t
dsckh
t
dsdsu
t
dsdhd
t
dscdsu
t
dscdhd
1
DVDS_CLK Period 33 ns
1
DVDS_CLK Low Time 40 50 %
1
DVDS_CLK High Time 40 50 %
DVDS_DATA Setup to DVDS_CLK active edge 4 ns
DVDS_DATA Hold after DVDS_CLK active edge 0 ns
DVDS_VLD,DVDS_SOS Setup to DVDS_CLK 3 ns
DVDS_VLD,DVDS_SOS Hold after DVDS_CLK 0 ns
Table 3. CS98100 DVD Interface Characteristics
1.
Values are guaranteed by design only
t
dsckper
CS98100
DVDS_CLK
(Input)
DVDS_DATA
(Input)
DVDS_VLD, DVDS_SOS
(Input)
t
dsckl dsckh
t
t
dsdsu
t
dscdsu
t
dsdhd
t
dscdhd
Figure 6. CS98100 DVD Serial Interface Timing Diagram
11
CS98100
1.2.4 Digital Video Interface Timing
Figure7 illustrates the signal timing for the digital video interface pins. The clock is without a polarity to
show the clock may be inverted by register programming. This also illustrates that data is clocked out on
both clock edges in progressive mode. The data order is Cr,Y0,Cb,Y1, and the sync outputs may be programmed as active high or active low.
Symbol Description Min Typ Max Unit
t
t
t
1
vocper
covo1
covo2
CLK27_O period 37.037 ns
2
VDAT[7:0] delay from CLK27_O -10 10 ns
2
Vsync/Hsync delay from CLK27_O -10 10 ns
Table 4. CS98100 Digital Video Interface Characteristics
1.
Values are guaranteed by design only
2.
It is recommanded that the output data should be taken at the opposite edge of the CLK27_O.
Tvocper
CLK27_O
(Output)
VDAT[7:0]
(Output)
VSYNC/HSYNC (Output)
Figure 7. CS98100 Digital Video Interface Timing Diagram
Tcovo1
Tcovo2
12
CS98100
* Active clock edge is programmable. Timing is referenced from active edge.
1.2.5 Digital Audio Interface Timing
Figure8 and Figure9 illustrate the signal timing for the digital audio pins. The bi-directional AUD_XCK
pin clocks at 8x the frequency of the AUD_BCK pin. The AUD_BCK pin outputs at 32x or 48x of the
sample frequency, and transitions on the falling edge of the AUD_XCK pin. AUD_BCK is shown without
polarity to indicate the polarity is programmable.
Symbol Description Min Typ Max Unit
t
slri
t
sdi
thsdi AIN_DATA hold time after AUD_BCK active edge 1 - ns
*AUD_BCK (Output)
AIN_LRCK setup to AUD_BCK active edge 25 - ns
AIN_DATA setup to AUD_BCK active edge 25 - ns
Table 5. Digital Audio In Characteristics
AIN_LRCK (Input)
AIN_DATA (Input)
t
lrts
t
sdsus
Figure 8. Digital Audio In Timing Diagram
t
sdhs
13
CS98100
Symbol Description Min Typ Max Unit
t
1
axch
1
taxcl
t
axper
t
odbck
t
odbck
t
aoper
t
2
odlr
t
2
odsd
1.
Values are guaranteed by design only
2.
It is recommanded that the output data should be taken at the opposite edge of the AUD_BCK.
AUD_XCLK High Time (AUD_XCLK is Input/Output) 40 50 %
AUD_XCLK Low Time (AUD_XCLK is Input/Output) 40 50 %
AUD_XCLK period (Input/Output) 27 ns
AUD_BCK delay from AUD_XCLK(output) active
10 ns
edge
AUD_BCK delay from AUD_XCLK(input) active
21 ns
edge
AUD_BCK period 216 ns
AUD_LRCK delay from AUD_BCK active edge -10 10 ns
AUD_D[3:0] delay from AUD_BCK active edge -10 10 ns
Table 6. Digital Audio Out Characteristics
AUD_XCLK(Input/Output)
AUD_BCK(Output)
* AUD_BCK(Output)
AUD_LRCK(Output)
AUD_DO[3:0] (Output)
t
axper
t
odsd
t
axch
t
odlr
t
aoper
t
axcl
t
odbck
14
* Active clock edge is programmable. Timing is referenced from active edge.
Figure 9. Digital Audio Out Timing Diagram
1.2.6 ROM/NVRAM Interface
Symbol Description Min Typ Max Unit
t
rc
t
cds
t
ods
t
ads
t
aws
t
cws
t
wp
t
wdo
t
dh
Read Cycle Time 98 ns
CE to Data Setup 80 ns
OE to Data Setup 70 ns
Address to Data Setup 90 ns
Address to WE setup (Write) 20 ns
CE to WE setup (Write) 5 ns
WE Pulse Width (Write) 160 ns
CE to Data Output (Write) -5 ns
WE to Data Hold (Write) 10 ns
Table 7. RAM/NVROM Characteristics
Note:Read timing based on 10.5 ns memory clock and 4 programmed wait states.
CS98100
Address
M_A[11:0],
M_D[27:16]
NVM_CE_N
NVM_OE_N
(M_AP)
M_D[7:0]
NVM_WE_N
t
rc
t
cds
t
ods
t
ads
Figure 10. ROM/NVRAM Reading Timing
15
Address
M_A[11:0],
M_D[27:16]
NVM_CE_N
t
CS98100
aws
NVM_WE_N
M_D[7:0]
NVM_OE_N
(M_AP)
t
cws
t
wdo
t
wp
Figure 11. ROM/NVRAM Write Timing
t
wdh
16
1.2.7 Miscellaneous Timings
Symbol Description Min Typ Max Unit
1
txclper
trstl RST_N Low Pulse Width 1000 ns
tgph GPIO PW High 50 ns
tgpl GPIO PW Low 50 ns
1.
XTLCLK must meet the requirement of external the video encoder for correct chroma (27 MHz ± 1 KHz).
XTLCLK period 37.037 ns
Table 8. Miscellaneous Timing Characteristics
XTLCLOCK
RESET-N
xccper
t
trstl
CS98100
GPIO
tgph
Figure 12. Miscellaneous Timings
tgpl
17
2. TYPICAL APPLICATION
Figure13 shows an example of a complete high-end DVD solution using the CS98100.
CS98100
Audio
Front Panel
Audio
ADC
IR
DVD Loader
(IO Channel,
ATPAI or
Serial)
Figure 13. CS98100 Application
ROM/
FLASH
1/
-1MB
2
27M XTAL
CS98100
SDRAM
4-8MB
2.1 CS98100 Device Summary
RISC-32
• Powerful 32-bit RISC processor
• Optimizing C compiler and source level debugger
• Big or little endian data formats supported
• MAC multiply/accumulate in two cycles with
C support.
(4)Audio
DACs
Power
Reg.
Audio-
Up to 8 Channels
S/PDIF
Composite Video
S-Video
Component Video
Switch
Power
communication
• 32-bit timers for I/O and other uses, with programmable interval rates
• Both hardware and software interrupts on data
or debug
• Performance monitors which measures DRAM
bandwidth, usage, and RSK performance
• 4 Kbyte instruction cache, 2 Kbyte data cache.
• Single cycle instructions run at 90 MHz.
DSP-32
• Powerful 24/32-bit DSP processor
• 24-bit fixed point logic, with 54-bit accumulator.
• Single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic.
• 8 Kbyte instruction cache, 12 Kbyte program
visible local memory
• Single cycle instructions run at 90 MHz.
SYSTEM CONTROLS
• Include several hardware lockable semaphore
registers
• General-purpose registers for inter-processor
18
• Built in PLLs generate all required clocks from
27 MHz input clock.
• Memory Controller
• Supports SDRAM, and SGRAM, from 2
MBytes to 32 MBytes.
• Supports multiple banks of FLASH and ROM
up to 32 MBytes.
• 32-bit data bus for DRAM, 8 or 16-bit data bus
for ROM.
DATA FLOW ENGINE
• Two DMA controllers – local memory based
and direct memory-to-memory
• 2432 bytes of internal memory, DMA to/from
main RAM into local SRAM.
• Supports endian conversion and byte, short,
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