Cirrus Logic CS98000-CM Datasheet

DVD On-a-Chip Solution

CS98000

Features

l Powerful Dual 32-bit RISCs >160 MIPS
l Software based on popular RTOS, C/C++
l MPEG video decoder supports DVD, VCD,

VCD 3.0, and SVCD standards

l Video input with Picture-in-Picture and zoom
l 8-bit multi-region OSD w/vertical flicker filter
l Universal subpicture unit for DVD and SVCD
l PAL<->NTSC Scaling and Transcoding
l Supports SDRAM and FLASH memories
l Powerful 32-bit Audio DSP >80 MIPS
l Decodes: AC-3, DTS, MPEG Stereo
l Plays MP3 CDs
l Karaoke echo mix and pitch shift
l Optional 3-D Virtual, bass & treble control
l Up to 8-channel PCM output
l IEC-60958/61937 Out: AC-3, DTS, MPEG
l Multi-Mode Serial Audio I/O: I2S & AC-Link
l AV Bus or ATAPI interface or DVD/CD/HD
l GPIO support for all common sub-circuits

Description

Overall the CS98000 Crystal DVD Processor is tar­geted as a market specific consumer entertainment
processor that empowers new product classes with
the inclusion of a DVD player as a fundamental fea­ture. You can use this integrated circuit with all the
other Crystal mixed signal data converters, DSPs,
and the CS98000’s high quality factory firmware to
rapidly conceptualize, design, and market cutting­edge Internet age products such as:

• DVD A/V Mini-Systems

• DVD Players

• DVD Receivers

• Car/SUV Entertainment Units

ORDERING INFORMATION

CS98000-CM 0° to 70° C 208-pin

RISC-1

I-Cache D-Cache

MMU

Filter

MPEG Decoder

VLC Parser

RAM MoCo

Video Processor

On-Screen Display

Picture-in-Picture

Video/Graphics Display

MAC

Video Input

Scaler

IDCT

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

RISC-2

I-Cache D-Cache

MMU

Clock Manager

Dataflow Engine

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

MAC

DMA / BitBlit
SRAM Buffer

External I/Os

Remote Input

GPIOs

Copyright  Cirrus Logic, Inc. 2000

Memory Controller

SDRAM Control

FLASH Control

Subpicture Decode

Scaler

System Controls

STC

Interrupts

Registers

SDRAM

(All Rights Reserved)

32- Bit DSP

I-Cache

X,Y Data

Memory

CPU / MAC

Audio I/O

PCM Out

PCM In

XMT958

A/V Bus
ATAPI-IDE
Local Bus

NOV ‘01

DS525PP2

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................5

1.1 AC AND DC PARAMETRIC SPECIFCATIONS .................................................................5

1.1.1 ABSOLUTE MAXIMUM RATING ..........................................................................5

1.1.2 RECOMMENDED OPERATING CONDITIONS ...................................................6

1.1.3 ELECTRICAL CHARACTERISTICS ....................................................................6

1.2 DC CHARACTERISTICS ................................................................................................... 7

1.2.1 ATAPI Interface .....................................................................................................7

1.2.2 SDRAM Interface .................................................................................................. 8

1.2.3 ROM/NVRAM Interface ......................................................................................10

1.2.4 Video Output Interface ........................................................................................11

1.2.5 Video Input Interface ...........................................................................................12

1.2.6 Audio Input Interface ...........................................................................................13

1.2.7 Audio Output Interface ........................................................................................14

1.2.8 AC97/CODEC Interface ......................................................................................15

1.2.9 Miscellaneous Interface Timing ...........................................................................16

2. TYPICAL APPLICATION ........................................................................................................17

3. FUNCTIONAL DESCRIPTION ...............................................................................................18

3.1 Block Diagram ..................................................................................................................18

3.2 CS98000 Device Details ..................................................................................................18

3.2.1 RISC-32 Processors ...........................................................................................18

3.2.2 Powerful 24/32-Bit DSP ......................................................................................18

3.2.3 System Controls ..................................................................................................18

3.2.4 Memory Controller ...............................................................................................19

3.2.5 Data Flow Engine ................................................................................................ 19

3.2.6 MPEG Video Decoder .........................................................................................19

3.2.7 System Synchronization ......................................................................................19

3.2.8 Audio Interface .................................................................................................... 19

3.2.9 Video Input ..........................................................................................................19

3.2.10 External Interface .............................................................................................. 19

3.2.11 Video Processor ................................................................................................19

3.2.12 Sub-Picture Processor ......................................................................................19

3.2.13 System Functions ..............................................................................................20

3.3 RISC Processor ...............................................................................................................20

3.4 DSP Processor ................................................................................................................20

3.5 Memory Control ...............................................................................................................20

CS98000

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information de­scribes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this
document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied).
Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All prod­ucts are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and
limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale
of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus
Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus
Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization
with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic web site
or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The
names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which
may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found

Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those
components in a standard I2C system.

2

at http://www.cirrus.com

.

CS98000

3.6 Dataflow Control (DMA) ................................................................................................... 20

3.7 System Control Functions ............................................................................................... 21

3.8 DVD/ATAPI Interface ....................................................................................................... 21

3.9 MPEG Video Decoding .................................................................................................... 21

3.10 Audio Processing ........................................................................................................... 21

3.11 Soft Modem ................................................................................................................... 22

3.12 Video ............................................................................................................................. 22

4. MEMORY MAP ....................................................................................................................... 22

4.1 Processor Memory Map .................................................................................................. 22

4.2 Host Port Memory Map .................................................................................................... 22

4.3 Internal I/O Space Map .................................................................................................... 22

5. REGISTER DESCRIPTION .................................................................................................... 24

5.1 CS98000 Register Space ................................................................................................ 24

6. PIN DESCRIPTION ................................................................................................................. 33

6.1 Pin Assignments .............................................................................................................. 34

6.2 Miscellaneous Interface Pins ........................................................................................... 40

6.3 SDRAM Interface ............................................................................................................. 40

6.4 ROM/NVRAM Interface ................................................................................................... 41

6.5 Video Output Interface ..................................................................................................... 41

6.6 Video Input Interface ....................................................................................................... 42

6.7 Audio Output/Input Interface ............................................................................................ 42

6.8 AC97/CODEC Interface ................................................................................................... 43

6.9 Host Master/ATAPI Interface ........................................................................................... 43

6.10 DVD I/O Channel Interface ............................................................................................ 44

6.11 General Purpose Input/Output (GPIO) .......................................................................... 44

6.12 Power and Ground ........................................................................................................ 45

7. PACKAGE SPECIFICATIONS ............................................................................................... 46

LIST OF FIGURES

Figure 1. ATAPI Transactions - Read and Write............................................................................. 7

Figure 2. SDRAM Refresh Transaction........................................................................................... 8

Figure 3. SDRAM Burst Write Transaction ..................................................................................... 8

Figure 4. SDRAM Burst Read Transaction..................................................................................... 9

Figure 5. SDRAM Timing................................................................................................................ 9

Figure 6. ROM/RVRAM Timing..................................................................................................... 10

Figure 7. Video Output Timing..................................................................................................... 11

Figure 8. Video Input Timing......................................................................................................... 12

Figure 9. Audio Input Timings....................................................................................................... 13

Figure 10. Audio Output Timing.................................................................................................... 14

Figure 11. CODEC Timing............................................................................................................ 15

Figure 12. Miscellaneous Timing .................................................................................................. 16

Figure 13. CS98000 Typical Application....................................................................................... 17

Figure 14. CS98000 Block Diagram.............................................................................................. 18

Figure 15. CS98000 Pinouts......................................................................................................... 33

Figure 16. 208-Pin Package Drawing ........................................................................................... 46

LIST OF TABLES

Table 1. ATAPI Interface Symbols / Characterization Data............................................................ 7

Table 2. SDRAM Interface Symbols and Characterization Data..................................................... 8

Table 3. ROM/NVRAM Interface Symbols and Characterization Data......................................... 10

Table 4. Video Output Interface Symbols and Characterization Data........................................... 11

3

CS98000

Table 5. Video Input Interface Symbols and Characterization Data..............................................12

Table 6. Audio Input Interface Symbols and Characterization Data..............................................13

Table 7. Audio Output Interface Symbols and Characterization Data...........................................14

Table 8. AC97/CODEC Interface Symbols and Characterization Data.........................................15

Table 9. Miscellaneous Interface Symbols and Characterization Data......................................... 16

Table 10. Memory Map-RISC0 Processor ....................................................................................23

Table 11. Host Port Memory Map .................................................................................................23

Table 12. Internal IO Space Map ..................................................................................................23

Table 13. CS98000 Register Map and Blocks ..............................................................................24

Table 14. CS98000 Registers.......................................................................................................24

Table 15. Pin Type Legend...........................................................................................................33

Table 16. 208-Pin Package Assignments .....................................................................................34

Table 17. Miscellaneous Interface Pins.........................................................................................40

Table 18. SDRAM Interface ..........................................................................................................40

Table 19. ROM/NVRAM Interface................................................................................................. 41

Table 20. Video Output Interface ..................................................................................................41

Table 21. Video Input Interface.....................................................................................................42

Table 22. Audio Input/Output Interface .........................................................................................42

Table 23. AC97/CODEC Interface ................................................................................................43

Table 24. Host Master/ATAPI Interface.........................................................................................43

Table 25. DVD I/O Channel Interface............................................................................................44

Table 26. General Purpose I/O Interface ......................................................................................44

Table 27. Power and Ground.......................................................................................................45

4

1. CHARACTERISTICS AND SPECIFICATIONS

1.1 AC AND DC PARAMETRIC SPECIFICATIONS

(AGND, DGND=0V, all voltages with respect to 0V)

1.1.1 ABSOLUTE MAXIMUM RATING

Symbol Description Min Max Unit

VDD
VDD
V

I

I

I

I

O

T

SOL

T

VSOL

T

STOR

T

AMB

P

IO

P

CORE

P

PLL

IO
CORE

Power Supply Voltage on I/O ring -0,5 4.6 Volts
Power Supply Voltage on core logic and PLL -0.5 3.6 Volts
Digital Input Applied Voltage (power applied) -0.5 5.5 Volts
Digital Input Forced Current -10 10 mA
Digital Output Forced Current -50 50 mA
Lead Soldering Temperature - 260
Vapor Phase Soldering Temperature - 220
Storage Temperature (no power applied) -40 125
Ambient Temperature (power applied) 0 70
Power consumption on I/O ring (CL = 35 pF) - 57 mA
Power consumption on the core logic - 620 mA
Power consumption on the PLL logic - 15 mA

CS98000

o

C

o

C

o

C

o

C

CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to
the device. Cirrus Logic recommends that CS98000 devices operate at the settings described in the next
table.

1.1.2 RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

Supply Voltage, IO V
Supply Voltage, core and PLL V
Ambient Temperature(power applied) T

DD
DD

AMB

3.0 3.3 3.6 Volts

2.25 2.5 2.75 Volts
0 25 70

o

C

5

1.1.3 ELECTRICAL CHARACTERISTICS

Parameter Symbol Conditions Min Typ Max Units

Supply Current, IO I
Supply Current, core and PLL I
Input Voltage, High V
Input Voltage, Low V
Input Current I
Input Pull up/down resistor R
Output Voltage, High V
Output Voltage, Low V
Three-state Leakage I
Input Capacitance C
Output Capacitance C
Bidirect Capacitance C

DD
DD

IH

IL

IN

I
OH
OL

OZ

IN

OUT

BID

CS98000

Normal Operating - 45 - mA
Normal Operating - 550 - mA

2.0 - 5.0 Volts

- - 0.8 Volts

V

= V

DD

or V

SS

IN

@ buffer rating 2.4 - - Volts
@ buffer rating - - 0.4 Volts

V

= VSS or V

OUT

DD

-1 - +1 µA

- 75 - KΩ

-10 - +10 µA

- 3 - pF
3 6 pF
3 6 pF

6

CS98000

1.2 DC CHARACTERISTICS

(TA= 25°C; VDD_PLL=VDD_CORE=2.5V±10%, VDD_IO=3.3V±10%)

1.2.1 ATAPI Interface

CS98000 can interface with a ATAPI-type slave loader gluelessly. Figure1 illustrates a read ATAPI trans-
action and a write ATAPI transaction. PIO mode 4 is implemented to enable a sufficient data transfer rate
between ATAPI device and CS98000.

Note: ATAPI interface is a standard administered by the T13 committee that is responsible for all interface standards

relating to the AT Attachment (ATA) storage interface. T13 is a technical committee for the National
Committee on Information Technology Standards (NCITS).See http://www.t13.org/.

Symbol Description Min Typ Max Unit

t

acyc Cycle Time

t

aavr

t

arww

t

arec

t

awsu

t

awh

t

ardsu

t

arddh

t

ardr

t

arsu

t

aipw

t

arls

Address Valid to HMRD-/HMWR- Setup 20 ns
H_RD-/H_WR- Pulse Width 70 ns
H_RD-/H_WR- Recovery Time 25 ns
H_WR- Data Setup 20 ns
H_WR- Data Hold 10 ns
H_RD- Data Setup 20 ns
H_RD- Data hold 5 ns
Read Data Valid to H_RDY Active 0 ns
H_RDY Setup Time 35 ns
H_RDY Pulse Width 1250 ns
H_RDY Assertion to Release 5 ns

1

70 ns

Table 1. ATAPI Interface Symbols / Characterization Data

1.

Values are guaranteed by design only.

H_A[4:0]

H_RD-/H_WR-

H_D[15:0](WRITE)

H_D[15:0](READ)

H_RDY(deasserted

before tarsu)

H_RDY(asserted

before tarsu)

tacyc

taavr

tarsu

tarar

tarww

taipw

Figure 1. ATAPI Transactions - Read and Write

tardr

tardsu

tarec

Dout

tawhtawsu

Din

tarddh

tarls

7

CS98000

1.2.2 SDRAM Interface

CS98000 interfaces with either SDRAM or SGRAM for high data bandwidth transfer. Figure2 shows the
refresh cycle performed by CS98000. Figure3 shows a burst write (length = 8) transaction. Figure4 on

page9 shows a burst read (length = 8) transaction, while Figure5 on page9 shows detailed SDRAM in-

terface timing. In both Figure3 and Figure4, CAS latency is programmed to 3.

Symbol Description Min Typ Max Unit

t

msur

t

mhr

t

mco

tcch M_CKO high time 4.5 ns
tccl M_CKO low time 4.5 ns
t

mper

t

mhw

t

mdow

tmsuw M_D[31:0] valid time prior to M_CKO 4 ns

1.

Values are guaranteed by design only.

M_D[31:0] setup to M_CKO 3 ns
M_D[31:0] hold time after M_CKO 1 ns
M_CKO active edge to Output transition 7 ns

M_CKO Period1

10 12.5 ns
M_D[31:0] valid time after M_CKO 5 ns
M_D[31:0] delay from M_CKO rising edge 5 ns

Table 2. SDRAM Interface Symbols and Characterization Data

M_CKE

M_A_[11:0]

M_BS_N

M_RAS_N

M_CAS_N

M_WE_N

MD[31:0]

M_DQM_[3:0]

M_CKO

M_A_[11:0]

M_BS_N

M_RAS_N

M_CAS_N

M_WE_N

M_D_[31:0]

M_DQM_[3:0]

M_AP

M_AP

Figure 2. SDRAM Refresh Transaction

C1 C2 C3 C4 C5 C6 C7C0R0

D0 D1 D2 D3 D4 D5 D6 D7

Figure 3. SDRAM Burst Write Transaction

8

M_CKO

M_A_[11:0]
M_BS_N

M_RAS_N
M_CAS_N

M_WE_N
M_D_[31:0]

M_DQM_[3:0]

M_AP

CS98000

C1 C2 C3 C4 C5 C6 C7C0R0

D0 D1 D2 D3 D4 D5 D6 D7

Figure 4. SDRAM Burst Read Transaction

tccltcchtmpertmco

M_CKO

M_WE_N,M_AP,M_DQM[3:0],

M_RAS_N,M_CAS_N

M_CKE,M_A[11:0]

M_D[31:0](WRITE)

M_D[31:0](READ)

tmsur

tmhr

Figure 5. SDRAM Timing

tmdow

tmhw

tmsuw

9

1.2.3 ROM/NVRAM Interface

Symbol Description Min Typ Max Unit

t

mper M_CKO period

t

nco

t

nwdo

t

nsur

t

nhw

t

nhr

M_CKO to WE or OE out 15 ns
M_CKO to write data out 10 ns
Data setup to M_CKO 5 ns
Data hold from WE inactive 5 ns
Data hold from OE inactive 1 ns

Table 3. ROM/NVRAM Interface Symbols and Characterization Data

1.

Values are guaranteed by design only.

CS98000

1

10 12.5 ns

10

Figure 6. ROM/RVRAM Timing

1.2.4 Video Output Interface

Symbol Description Min Typ Max Unit

t

suvo

t

covo1

t

covo2

t

voch

t

vocl

Vsync/Hsync input setup to CLK27_O 5 ns
VDAT[7:0] delay from CLK27_O transition 10 ns
Vsync/Hsync delay from CLK27_O transition 10 ns

CLK27_O High Time
CLK27_O Low Time

Table 4. Video Output Interface Symbols and Characterization Data

1.

Values are guaranteed by design only

CLK27_O

(Output)

VDAT[7:0]

(Output)

1

1

Tvocl Tvoch

CS98000

14.8 18.5 22.2 ns

14.8 18.5 22.2 ns

Tcovo1

Tcovo2

VSYNC/HSYNC (Output)

VSYNC/HSYNC (Input)

Tsuvo

Figure 7. Video Output Timing

11

CS98000

1.2.5 Video Input Interface

Symbol Description Min Typ Max Unit

.

t

suvi

t

hvi

t

vich

t

vicl

1.

VIN_D[7:0] set up to VIN_CLK 5 ns
VIN_D[7:0] hold time after VIN_CLK rising edge 2 ns

VIN_CLK High Time
VIN_CLK Low Time

1

1

14.8 18.5 22.2 ns

14.8 18.5 22.2 ns

Table 5. Video Input Interface Symbols and Characterization Data

Active clock edge is programmable. Timing is referenced from active edge

VIN_CLK

VIN_D[7-0]

VIN_HSNC,VIN_VSNC,
VIN_FLD

tvicl

tvich

tsuvi thvi

Figure 8. Video Input Timing

12

1.2.6 Audio Input Interface

CS98000

Symbol

t

aicl

t

aich

t

aiper

t

stlr

t

lrts

t

sdsus

t

sdhs

AIN_BCK Low Time1,
AIN_BCK High Time
AIN_BCK period

1, 2

Time form AIN_LRCK transition to AUD_BCK active edge 5 - ns
Time form AIN_LRCK transition to AIN_BCK active edge 2 - ns
AIN_DATA setup to AIN_BCK transition 5 - ns
AIN_DATA hold time after AIN_BCK transition 2 - ns

Description Min Typ Max Units

2

1, 2

Table 6. Audio Input Interface Symbols and Characterization Data

1.

Values are guaranteed by design only

2.

Active clock edge is programmable. Timing is referenced from active edge

AIN_BCK (Input)

14 ns
14 ns

162.7 ns

t

aiper

t

aich

t

lrts

t

stlr

t

aicl

AIN_LRCK (Input)

AIN_DATA (Input)

t

sdsus

t

sdhs

Figure 9. Audio Input Timings

13

CS98000

1.2.7 Audio Output Interface

Symbol Description Min Max Units

1, 2

2

4.5 - ns

4.5 - ns
13 ns
14 - ns
14 ns

162.7 ns

- 2

- 2

- 2

- 2

t

axper

t

axch

t

axcl

t

axper

t

aoch

t

aocl

t

aoper

t

sdm

t

sdm

t

lrds

t

adsm

AUD_XCLK High Time (AUD_XCLK is Input/Output)1,
AUD_XCLK Low Time (AUD_XCLK is Input/Output)
AUD_XCLK period (Input/Output)
AUD_BCK High Time for Master mode
AUD_BCK Low Time for Master mode
AUD_BCK period (Output)

1, 2

1, 2

1, 2

1, 2

AUD_BCK delay from AUD_XCLK transition
AUD_BCK delay from AUD_XCLK transition
AUD_LRCK delay from AUD_BCK transition
AUD_D[3:0] delay from AUD_BCK transition

Table 7. Audio Output Interface Symbols and Characterization Data

1.

Values are guaranteed by design only

2.

Active clock edge is programmable. Timing is referenced from active edge

ns
ns
ns
ns

AUD_XCLK(Input/Output)

AUD_BCK(Output)

AUD_BCK(Output)

AUD_LRCK(Output)

AUD_DO[3:0] (Output)

t

axch

t

sdm

t

aoperl

t

aoch

t

lrds

t

adsm

Figure 10. Audio Output Timing

t

axcl

t

aocl

14