Cirrus Logic CS89712-CB Datasheet

CS89712

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Features

l ARM720T (ARM7 TDMI) processor

– 8 Kbytes of four-way set-associative cache – MMU with 64-entry TLB – Write Buffe r – Thumb code support enabled

l Dynamically clocked at 18, 36, 49 or 74 MHz l 10 Mbit Ethernet Controller with integrated PHY l Comprehensive Suite of Software Drivers l On-Chip Transmit and Receive RAM Buffers l 10BASE-T Port with Analog Filters provides

automatic polarity detection and correction

l Programmable Transmit Features:

– Automatic Re-transmission on Collision – Automatic Padding and CRC Generation

l Programmable Receive Features:

– Early Interrupts for Frame Pre-Processing – Automatic Rejection of Erroneous Packets

Description

The low-power high-perform ance CS89712 is de signed for ultra-low-power com munic ation appl icati ons suc h as VoIP telephones, industrial control, data acquisition, special purpose servers and RF to Ethernet bridges. The core-logic functi onality of the device is built around a n ARM720T processor with 8 Kbytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like embedded Linux.

The CS89712 Ethernet port includes on-chip RA M and 10BASE-T transmit and receive filters.

ORDERING INFO

CS89712-CB 0 to 70° C

256 Ball PBGA 17x17 mm

3.6864 MHZ

32.768 KHZ

NPOR, RUN,

RESET, WAKEUP

BATOK, EXPWR

PWRFL, BATCHG

EINT[1-2], FIQ,

MEDCHG

FLASHING LED DRIVE

PORTS A, B, D (8-BIT)

PORT E (3-BIT)

KEYBD DRIVERS (0–7)

BUZZER DRIVE

DC-TO-DC

SSI (ADC)

INTERFACE

DAI / SSI / ADC

INTERFACE

PLL

32.768-KHZ OSCILLATOR

STATE CNTRL

POWER MANAGEMENT

INTERRUPT

CONTROLLER

RTC

GPIO

PWM

SSI1 (ADC)

DAI

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com

10BASE-T ETHERNET

SSI2

CODE

ARM720T

ARM7TD

8-KBYTE CACHE

MMU

WRITE

BUFFER

TIMER

ON-CHIP

BOOT ROM

EPB BUS

INTERNAL DATA BUS

MEMORY CO NT RO L LER

EXPANSION

SDRAM CNTRL

INTERNAL ADDRESS BUS

LCD

CONTROLLER

ON-CHIP SRAM

48K BYTES

EPB

CL-PS6700 INTFCE.

CONTROL

ICE-JTAG

UART UART

IrDA

D[0-31]

PB[0:1], NCS[4:5] EXPCLK, WORD,

NCS[0:3], EXPRDY , WRITE

MOE, MWE, SDCLK, SDQM[0:1], SDRAS, SDCAS

A[0-27], DRA[0-14]

TES T AND DEVELOPMENT

LCD DRIVE

LED AND PHOTODIODE

ASYNC INTERFACE 1

ASYNC INTERFACE 2

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

FEB ‘01

DS502PP2

Table Of Contents

1. OVERVIEW ............................................................................................................................... 4

2. FUNCTIONAL DESCRIPTION ................................................................................................. 7

2.1 CPU Core ............................................................................................................................7

2.2 State Control ....................................................................................................................... 7

2.3 Power-Up Sequence .........................................................................................................10

2.4 Resets ...............................................................................................................................10

2.5 Ethernet Port Reset and Initialization ................................................................................ 11

2.6 Ethernet EEPROM Configurations .................................................................................... 12

2.7 Clocks ...............................................................................................................................16

2.8 Interrupt Controller ............................................................................................................17

2.9 Boot ROM .........................................................................................................................21

2.10 Memory Map ...................................................................................................................21

2.11 Memory and I/O Expansion Interface .............................................................................. 23

2.12 SDRAM Controller ...........................................................................................................23

2.13 SDRAM Initialization .......................................................................................................26

2.14 CL-PS6700 PC Card Interface ........................................................................................26

2.15 Endianness .....................................................................................................................29

2.16 Internal UARTs and SIR Encoder ................................................................................... 30

2.17 Synchronous Serial Interfaces ........................................................................................31

2.18 LCD Controller ................................................................................................................39

2.19 Timer Counters ...............................................................................................................41

2.20 Real-Time Clock ..............................................................................................................43

2.21 Dedicated LED Flasher ...................................................................................................43

2.22 PWM Interfaces ...............................................................................................................43

2.23 Ethernet Port Architecture ............................................................................................... 44

2.24 Ethernet Port Functional Description ..............................................................................45

2.25 Programming the EEPROM ............................................................................................46

2.26 Ethernet LEDs ................................................................................................................. 48

2.27 Media Access Control Engine .........................................................................................48

2.28 Encoder/Decoder (ENDEC) ............................................................................................53

2.29 10BASE-T Transceiver ................................................................................................... 54

2.30 Basic Transmit Operation ................................................................................................ 56

2.31 Basic Receive Operation ................................................................................................. 56

2.32 Managing Interrupts & Status Queue .............................................................................. 57

2.33 Basic Receive Operation ................................................................................................. 57

2.34 Receive Frame Address Filtering .................................................................................... 63

2.35 Transmit Operation .........................................................................................................66

2.36 Full Duplex Considerations .............................................................................................69

2.37 Auto-Negotiation Considerations .................................................................................... 69

CS89712

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

Preliminary product inf o rmation describes products whi c h are i n production, but for whi ch f ul l char act er i zat i on da t a i s not yet available. Advance p rodu ct i nformation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reli able. However , t he infor mation is subje ct to chang e without noti ce and is provi d ed “AS IS” withou t warran ty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the pro perty of Cirrus Logi c, Inc. and implie s no licen se under pat ents, copyright s, tr ademarks, or trade secr ets. No part of this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electro nic, mechanical, photographic, or otherwise) without the pr i or writ ten consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or di sk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.

2 DS502PP2

CS89712

3. REGISTER SET ...................................................................................................................... 70

3.1 Internal Registers .............................................................................................................. 70

3.2 Accessing Ethernet Port Registers ................................................................................... 73

3.3 Ethernet Port Internal Memory Map .................................................................................. 77

3.4 I/O Port Data Registers ..................................................................................................... 78

3.5 System Control Registers ................................................................................................. 79

3.6 Interrupt Registers ............................................................................................................ 89

3.7 Expansion Memory Configuration Registers ..................................................................... 92

3.8 Timer / Counter Registers ................................................................................................. 95

3.9 Miscellaneous Registers ................................................................................................... 95

3.10 UART Registers .............................................................................................................. 98

3.11 LCD Registers ............................................................................................................... 100

3.12 SSI Register .................................................................................................................. 103

3.13 End Of Interrupt Locations ............................................................................................ 104

3.14 State Control Registers ................................................................................................. 105

3.15 SS2 Registers ............................................................................................................... 106

3.16 DAI Registers ................................................................................................................ 106

3.17 Ethernet Bus Interface Registers .................................................................................. 117

3.18 Ethernet Port Status/Control Registers ......................................................................... 117

4. TEST & DEBUG MODES ..................................................................................................... 137

4.1 Entering test modes ........................................................................................................137

4.2 Boundary Scan ............................................................................................................... 139

4.3 In-Circuit Emulation ......................................................................................................... 140

5. MECHANICAL INFORMATION .......................... ....... ...... ...... ....... ...... ....... ...... ....... .............. 142

5.1 256-PBGA Pin Diagram .................................................................................................. 142

5.2 256-Ball PBGA Ball Listing ............................................................................................. 143

5.3 External Signal Functions .......................................................................................... 147

5.4 Output Bi-Directional Pins ............................................................................................... 151

5.5 256 PBGA Package Dimensions .................................................................................... 153

6. ELECTRICAL/THERMAL INFO ........................................................................................... 154

6.1 Absolute Maximum Ratings ............................................................................................ 154

6.2 DC Characteristics .......................................................................................................... 154

6.3 AC Characteristics .......................................................................................................... 157

6.4 I/O Buffer Strength & Characteristics .............................................................................. 169

7. ORDERING INFORMATION .............................................................. ....... ...... ..................... 170

DS502PP2 3

1. Overview

CS89712

CRYSTAL CRYSTAL

PC CARD

SOCKET

SDRAM

EXTERNAL MEMOR YMAPPED EXPANSION

ADDITIONAL I/O

CL-PS6700

PC CARD

CONTROLLER

× 16

FLASH

× 16

FLASH

BUFFERS

LATCHES

ETHERNET

CRYSTAL

× 16

FLASH

× 16

FLASH

AND

MOSCIN RTCIN CS[4]

PB0 EXPCLK

D[31:0] A[27:0]

SDQM[3:0] SDCS0

SDCS1

SDCAS

SDRAS

NCS[0] NCS[1]

MOE WRITE

CS[n] WORD

CS[2] CS[3]

EXTL1 EXTL2

DD[3:0]

CL1 CL2

COL[7:0]

PA[7:0]

PB[7:0]

PD[7:0] PE[2:0]

POR PWRFL BATOK

EXTPWR BATCHG

CS89712

RUN

WAKEUP

DRIVE[1:0]

FB[1:0]

SSICLK

SSITXFR SSITXDA SSIRXDA

LEDDRV

PHDIN

RxD1/2

TxD1/2

DSR

CTS

DCD

ADCCLK

ADCCS

ADCOUT

ADCIN

SMPCLK

RXD-

RXD+

TXD-

TXD+

LCD MODULE

KEYBOARD

POWER

SUPPLY UNIT

AND

COMPARATORS

DC-TO-DC

CONVERTERS

CODEC/SSI2/

DAI

IR LED AND

PHOTODIODE

2× RS-232

TRANSCEIVERS

ADC

DIGITIZER

ETHERNET

TRANSFORMER

INPUT

BATTERY

Figure 1. A CS89712–Based System

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CS89712

The CS89712 contains a single-chip embedded controller designed to be used in low-cost and ultra-low-power applications. Operating at 74 MHz, the CS89712 delivers about 66 Dhrystone

2.1 MIPS sustained (74 MIPS peak). The CS89712 contains the following features:

• ARM720T processor with:

- ARM7TDMI CPU core (supporting the Thumb instruction set and with enhanced multiplier) running at a dynamic clock speeds of 18, 36, 49, or 74 MHz

- Advanced power management

- Memory Management Unit compatible with the ARM710 core (and a 64-entry translation lookaside buffer) with added support for Windows CE

- 8 kbytes of unified instruction/data cache with a four-way set associative controller

- Write buffer

- JTAG, core debug and full embedded ICE

• Full 10BaseT Ethernet port, with all the analog & digital circuitry needed for a c omplete Ethernet circuit, having:

- Media Access Control (MAC) IEEE 802.3

compliant full-duplex engine. It handles all aspects of Ethernet frame transmission and reception, including: collision detection, preamble generation and detection, and CRC generation and test. Features include automatic retransmission on collision, and automatic padding of transmitted frames.

- 4 kbyte page of on-chip memory, eliminat-

ing external memory chips.

- serial EEPROM interface allowing config-

uration information storage for automatic load at power-up.

It provides on-chip LED drivers for link status, bus status, and Ethernet line activity.

- 10BASE-T transceiver including drivers, receivers, and analog filters, for direct connection to low-cost isolation transformers.

- very low noise emission, shortening EMI testing and qualification time.

• 48k bytes of on-chip SRAM sharable between the LCD controller and general applications

• Low power operation. Typical power dissipated is 270 mW at 74 MHz in the Operating State and 160 mW in the Idle State (clock to the C PU stopped, everything else running), with <150 uW in the Standby State (realtime clock ‘on’, everything else stopped). The Ethernet block has a Software Suspend state, disabling the receiver and dropping current to the microampere range.

• Advanced audio decoder / decompression supports multiple audio decompressi on alg orit hms at all standard sample & bit rates. MPEG 1, 2, and 2.5 layer 3 audio decoding is supported, including ISO compliant MPEG 1 and 2 layer 3 support. Adaptive bit rates are supported.

• Up to 64 MHz of SDRAM can operate at up to

36.864 MHz with 16- or 32-bit wide accesses.

• ROM / SRAM / FLASH Memory controller decodes up to 5 separate memory segments each up to 256 Mbytes. Each segment can be configured as 8, 16, or 32 bits wide with page-mode access support and programmable access times. Supports removable FLASH card interface for addition of expansion FLASH modules.

• 27 general-purpose I/O bits; three 8-bit and one 3-bit port support scanning keyboard matrix.

• Digital Audio Interface (DAI) for interfacing to CD-quality DACs and CODECs.

- A Manchester encoder/decoder, clock recovery circuit, and 10BASE-T transceiver.

DS502PP2 5

• Interrupt controller.

• IrDA 115.2 kbps SIR protocol controller.

CS89712

• LCD controller interfaces directly to a singlescan panel monochrome LCD. Panel width size is programmable from 32 to 1024 pixels in 16pixel increments. Video frame buffer size programmable up to 128 kbytes with 1, 2, or 4 bits per pixel supports 15-level grayscale operation.

• Programmable frame buffer address allows a system with only internal SRAM for memory.

• On-chip boot ROM programmed with serial load boot sequence.

• Two 16-bit general purpose timer counters.

• 32-bit Real-Time Clock and comparator.

• Dedicated LED flasher pin driven from the RTC with programmable duty ratio (multiplexed with a GPIO pin).

• Two 16550 type UARTs:

- support bit rates up to 115.2 kbps

- contain two 16-byte FIFOs for TX and RX

- UART1 supports modem control signals

• Two synchronous serial interfaces for Microwire (128 kbps) or SPI peripherals such as ADCs, one supporting both master/slave mode and the other supporting master mode only.

• PWM interface provides two 96 kHz clocks with programmable 1/16 to 15/16 duty cycle for driving a DC to DC converter.

• An interface to one or two Cirrus Logic CLPS6700 PC Card controller devices to support two PC Card slots.

• Oscillator and phase-locked loop (PLL) to generate the core clock speeds of 18.432 MHz,

36.864 MHz, 49.152 MHz, and 73.728 MHz from an external 3.6864 MHz crystal.

• A low-power 32.768 kHz oscillator.

• Suite of software drivers for immediate use with most industry standard network operating systems. In addition, complete evaluation kits and manufacturing packages significantly reduce production cost and time.

• Commercial 0 - 70C operating temperature.

The CS89712 design is optimized for low power dissipation and is fabricated on a fully static

0.25 micron CMOS process. It is available in a

256-ball PBGA package. A maximum configured system using the CS89712

is shown in Figure 1. This system assumes all of the DRAMs and ROMs are 16-bit wide devices. The keyboard may be connected to more GPIO bits than shown to allow greater than 64 keys, however these extra pins will not be wired into the WAKEUP pin functionality. Note that only one of the CODEC, SSI2, or DAI interfaces may be used at a time.

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CS89712

2. FUNCTIONAL DESCRIPTION

2.1 CPU Core

The ARM720T consists of an ARM7TDMI 32-bit RISC processor, a unified 8 kbyte cache, and a memory management unit (MMU). The cache is four-way set associative organized as 512 lines with each line being 16 bytes. The cache is directly connected to the ARM7TDMI, and therefore caches the virtual address from the CPU. When the cache misses, the MMU translates the virtual address into a physical address. A 64-entry translation lookaside buffer (TLB) is utilized to speed the address translation process and reduce bus traffic necessary to read the page table. The MMU saves power by only translating cache misses.

See the ARM720T Data sheet for a complete description of the various logic blocks that make up the processor, as well as all internal registers.

2.2 State Control

The CS89712 supports the following Power Management States: Operating, Idle, and Standby (see

Figure 2). There is also a state called the Doze

State, however it is a temporary execution state. The normal program execution state i s th e Operat ing State, which is a full performance state where all of the clocks and peripheral logic are enabled. The Idle State is the sam e as the Operating State

with the exception of the CPU clock being halted, and only an external interrupt will return it back to the Operating State. The Standby State has the lowest power consumption of the three states. By selecting this mode the main oscillator shuts down, leaving only the Real-Time Clock and its associated logic powered. When the CS89712 is in Standby all power and ground pins should remain connected to power and ground in order to have a proper system wake-up. The only state that Standby can transition to is the Operating State.

2.2.1 Standby State

The Standby State equates to the system being switched "off" (i.e., no display, and the main oscillator is shut down). The PLL will be shut down.

In the Standby State, all the system memory and state is maintained and the system time is kept upto-date. The PLL/on-chip oscillator or external oscillator is disabled and the system is static, except for the low-power watch crystal (32 kHz) oscillator and divider chain to the RTC and LED flasher. The RUN signal is driven low, therefore this signal can be used externally in the system to power down other system modules.

Whenever the CS89712 is in the Standby State, the external address and data buses are forced low internally by the RUN signa l. This i s do ne to preve nt peripherals that are powered down from draining

Interrupt or r ising wakeup

Standby

Write to standby location, power fail, or user reset

nPOR, power fail, or user reset

Idle

Figure 2. State Diagram

DS502PP2 7

Operating

Write to halt location

CS89712

Address (W/B) Operating Idle Standby

SDRAM Control On On SELFREF Off N/A UARTs On On Off Reset Reset LCD FIFO On On Reset Reset Reset LCD On On Off Reset Reset ADC Interface On On Off Reset Reset SSI2 Interface On On Off Reset Reset DAI Interface On On Off Reset Reset CODEC On On Off Reset Reset Timers On On Off Reset Reset RTC On OnOnOnOn LED Flasher On On On Reset Reset DC-to-DC On On Off Reset Reset CPU On Off Off Reset Reset Interrupt Control On On On Reset Reset PLL/CLKEN Signal On On Off Off Off

Table 1. Peripheral Status in Different Power Management States

nPOR

RESET

nURESET

RESET

current. Also, the internal peripheral’s signals get set to their Reset State.

When first powered, or reset by the nPOR (Power On Reset, active low) signal, the CS89712 is forced into the Standby State. This is known as a cold reset, and when leaving the Standby State after a cold reset, external wake up is the only way to wake up the device. When leaving the Standby State after non-cold reset conditions (i.e., the software has forced the device into the Standby State), the transition to the Operating State can be caused by a rising edge on the WAKEUP input signal or by an enabled interrupt. Normally, when entering the Standby State from the Operating State, the software will leave some interrupt sources enabled.

Note: The CPU cannot be awakened by the TINT,

WEINT, and BLINT interrupts when in the Standby State.

Typically, software writes to the Standby internal memory location to cause the transition from the Operating State to the Standby State. Before enter-

ing the Standby State, if external I/O devices (such as the CL-PS6700s connected to nCS[4] or nCS[5]) are in use, the software must ensure that they ar e idle before writing to the Standby State location.

Before entering the Standby State, the software must properly disable the DAI. Failing to do so will result in higher than expected power consumption in the Standby State, as well as unpredictable operation of the DAI. The DAI ca n be r e-enabled afte r transitioning back to the Operating State.

The system can also be forced into the Standby State by hardware if the nPWRFL or nURESET inputs are forced low. The only exit from the Standby State is to the Operating State.

The system will only transition to the Operating State from the Standby State under the following conditions: when the nPWRFL input pin is high, when the nEXTPWR input pin is low, or when the BATOK input pin is high. This prevents the system from starting when the power supply is inadequate

8 DS502PP2

CS89712

(i.e., the main batteries are low), corresponding to a low level on nPWRFL or BATOK.

From the Standby State, if the WAKEUP signal is applied with no clock except the 32 kHz clock running, the CS89712 will be initialized into a state where it is ready to start and is waiting for the CPU to start receiving its clock. The CPU will still be held in reset at this point . After the first cloc k is applied, there will be a delay of about eight clock cycles before the CPU is enabled. This delay allows the CPU clock to settle.

2.2.1.1 UART in Standby State

During the Standby State, the UARTs are disabled and cannot detect any activity (i.e., start bit) on the receiver. If this functionality is required then this can be accomplished in software by the following method:

1) Permanently connect the RX pin to one of the active low external interrupt pins.

2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the UART is enabled.

3) Send a preamble that consists of one start bit, 8 bits of zero, and one stop bit. This will cause the CS89712 to wake and execute the enabled interrupt vector.

The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the start of the pream ble, the timing of the sample point will be off-center during the preamble byte. However, the next byte transmitted will be correctly aligned. Thus, the actual first real byte to be received by the UART will be correct.

2.2.2 Idle State

If in the Operating State, the I dle State can be entered by writing to a special internal memory location (HALT) in the CS89712. If an interrupt occurs, the CS89712 will return immediately back to the

Operating State and execute the next instruction. The WAKEUP signal can not be used to exit the Idle State. It is only used to exit the Standby State.

In the Idle State, the device functions just like it does when in the Operating State. However, the CPU clock is halted while it wa its for an event such as a key press to generate an interrupt. The PLL always remains active in the Idle State.

2.2.3 Keyboard Interrupt Wakeup

For the case of the keyboard interrupt, the following options are available and are selectable according to bits 1 and 3 of the SYSCON2 register (refer to Section 3.5.2 for register details).

• If the KBWEN bit (SYSCON2 bit 3) is set low, then a keypress will cause a transition from a power saving state only if the keyboard inter rupt is non-masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is high).

• When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the “Keyboard Direct Wakeup’ mode. In this mode, the interrupt request may not get serviced. If the interrupt is masked (i.e., the interrupt mask register 2 (INTMR2 bit 0) is low), the processor simply starts re-executing code from where it left off before it entered the power saving state. If the interrupt is non-masked, then the processor will service the interrupt.

• When the KBD6 bit (SYSCON2 bit 1) is low, all 8 Port A inputs are OR’ed together to produce the internal wakeup signal and keyboard interrupt request. This is the default reset state.

• When the KBD6 bit (SYSCON2 bit 1) is high, only the lowest 6 bits of Port A are OR’ed together to produce the internal wakeup signal and keyboard interrupt request. The two most significant bits of Port A are available as GPIO when this bit is set high.

DS502PP2 9

CS89712

When both KBWEN and INTMR2 bit 0 are low, the device can be awakened only by the external WAKEUP pin or another enabled interrupt source. The keyboard interrupt capability allows use of a polled and/or interrupt-driven keyboard routine.

Notes:The keyboard interrupt is NOT deglitched.

2.2.4 Ethernet Port Software Suspend

The Ethernet port power features work in a different manner than detailed above. Suspend modemay be entered via software. During this mode, all internal Ethernet circuits are shut off except the I/O Base Address register (Ethernet Port offset address 0020h) and the SelfCTL register.

To enter Suspend mode, the SWSuspend bit (SelfCTL Register, bit 8) is set. To exit SW Suspend, software must write to the CS89712 Ethernet (used only to wake the Ethernet port, the W rite data is ignored). Upon exit, the CS89712 Ethernet performs a complete reset, and then goes through a normal initialization procedure.

2.3 Power-Up Sequence

The following sequence should be followed to ensure proper start up. If any of the timing sequences recommended below are violated, then the part may not start up properly, requiring a hard reset to recover.

1) Upon power, the signal nPOR must be held active (LOW) for a minimum of 100us, after V has become settled.

2) After nPOR goes HIGH, the CS89712 will enter the Standby State (and only this state). In this state, the PLL and CPU are not enabled. The only method that can be used to allow the CS89712 to exit the Standby State into the Operating State is by the WAKEUP signal going active (HIGH).

Note: It is not a requirement to use the nURESET

signal. If not used, the nURESET signal must be HIGH, and it must have gone HIGH prior to nPOR going HIGH. This is

due to the fact that nURESET is latched into the device by the rising edge of nPOR. When nURESET is LOW on the rising edge of nPOR, it can force the device into one of its Test Mode states.

3) After nPOR goes HIGH, the WAKEUP signal cannot be detected as going HIGH, until after at least two seconds. After two seconds, the WAKEUP signal can become active, and it must be HIGH for at least 125 us.

4) Before the WAKEUP signal is detected internally, it must go through a deglitching circuit. This is why is must be active for at least 125us. Then the PLL gets enabled. WAKEUP is ignored immediately after waking up the system. It also ignores it while in the Idle or Operating State. It can constantly toggle with no affect on the device. It will only be read again if nPOR goes low and then high again, or if software has forced the device back into the Standby State.

5) A maximum of 250 msec will pass before the CPU starts to fetch the first instruction.

2.4 Resets

There are three asynchronous resets to the CS89712: nPOR (Power On Reset), nPWRFL, and nURESET. If an y of these are a ctive, a system reset is generated internally. This will reset all internal registers in the CS89712 except the RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be preserved through a user reset or power fail condition.

NOTE: The Ethernet Port has different reset conditions

and considerat ions than describ ed in this section. Refer to the following section for resetting the Ethernet Port.

Any reset will also reset the CPU and cause it to start execution at the reset vector when the CS89712 returns to the Operating State.

Three signals are used to internally reset storage elements. These are nPOR, nSYSRES (System Reset) and nSTBY. nPOR is an external signal. nSTBY is equivalent to the external RUN signal.

10 DS502PP2

CS89712

nPOR is the highest priority reset signal. When active (low), it will reset all storage elements in the CS89712. nPOR active forces nSYSRES and nSTBY active. nPOR will only be active after the CS89712 is first powered up and not during any other resets. nPOR active clears all flags in the status register except for the cold reset flag (CLDFLG) bit (SYSFLG, bit 15), which is set.

nSYSRES is generated internally in the CS89712 if either nPOR, nPWRFL, or nURESET are active. It is the second highest priority reset signal, used to asynchronously reset most internal registers. nSYSRES activation forces nSTBY and RUN low, and resets the CS89712 leaving it in the Standby State.

The nSTBY and RUN signals are high when the CS89712 is in the Operating or Idle States and low when in the Standby State. The m a in system c l ock is valid when nSTBY is high. The nSTBY signal will disable any peripheral block that is clocked from the master clock source (i.e., everything except for the RTC). However, when in Snooze State, the LCD controller and the DC to DC converter interface peripherals will NOT be disabled.

In general, a system reset will clear all registers and nSTBY will disable all peripherals that require a main clock, with the exception of the Snooze State operation as described above. The following peripherals are always disabled by a low level on nSTBY: two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI interfaces. In addition, when in the Standby State, the LCD controller and PWM drive are also disabled.

2.5 Ethernet Port Reset and Initialization

Different considerations apply to resetting and initializing the Ethernet Port.

2.5.1 Reset

Three different conditions cause the Ethernet port to reset its Ethernet internal registers and circuits.

2.5.1.1 Power-Up Reset

When power is applied, the Ethernet port maintains reset until the voltage at the supply pins reaches approximately 2.5 V. The Ethernet port comes out of reset once Vcc is greater than approximately 2.5 V and the crystal oscillator has stabilized.

2.5.1.2 Software Initiated Reset

There is a chip-wide reset whenever the RESET bit (SelfCTL Register, Bit 6) is set.

2.5.1.3 Software Suspend

Whenever the Ethernet port enters Software Suspend mode, all registers and circuits are reset. Upon exit, there is a chip-wide reset.

2.5.2 Allowing Time for Reset Operation

After a reset, the Ethernet port goes through a self configuration. This includes calibrating on-chip analog circuitry, and reading EEPROM for validity and configuration. Time required for the reset calibration is typically 10 ms. Software drivers should not access registers internal to the CS89712 Ethernet during this time. When calibration is done, bit INITD in the Self Status Register is set indicating that initialization is complete, and the SIBUSY bit in the same register is cleared indicating the EEPROM is no longer being read.

2.5.3 Initialization

After each reset (except EEPROM Reset), the

CS89712’s Ethernet port checks the sense of the EEDataIn pin to see if an external EEPROM is present. EEDI high indicates presence of an EEPROM and the Ethernet port automatically loads the configuration data stored in the EEPROM into its internal registers (see next section). If EEDI is low, an EEPROM is not present and the Ethernet port resets with the register values in Table 2.

An optional low-cost serial EEPROM can be used to store configuration information that is automati-

DS502PP2 11

CS89712

cally loaded into the Ethernet port after each reset (except EEPROM reset).

The CS89712 Ethernet operates with any of six standard EEPROMs shown in Table 3.

Ethernet Port

Address

0020h 0300h I/O Base Address 0022h XXXX XXXX

0102h 0003h RxCFG Register 0104h 0005h RxCTL Register 0106h 0007h TxCFG Register

0108h 0009h TxCMD Register 010Ah 000Bh BufCFG Register 010Ch Undefined Reserved 010Eh Undefined Reserved

0110h Undefined Reserved

0112h 00013h LineCTL Register

0114h 0015h SelfCTL Register

0116h 0017h BusCTL Register

0118h

Note: I/O base address is unaffected by Software

Suspend mode.

EEPROM Type Size (16-bit words)

‘C46 (non-sequential) 64 ‘CS46 (sequential) 64 ‘C56 (non-sequential) 128 ‘CS56 (sequential) 128 ‘C66 (non-sequential) 256 ‘CS66 (sequential) 256

Table 3. Supported EEPROM Types

Contents

XXXX X100

0019h

Table 2. Default Configuration

Interrupt Number

TestCTL Regi ste r

2.6 Ethernet EEPROM Configurations

2.6.1 EEPROM Interface

The EEPROM interface uses the signals shown in

Table 4.

Ethernet port

EECS EEPROM Chip Select Chip Select EESK 1 MHz EEPROM

EEDO EEPROM Data Out

EEDI EEPROM Data in

Table 4. EEPROM Interface

Ethernet port

Function

Serial Clock output

(data to EEPROM)

(data from EEPROM)

EEPROM

Clock

Data In

Data Out

2.6.2 EEPROM Memory Organization

If an EEPROM is used to store initial configuration information for the Ethernet port, the EEPROM is organized in one or more blocks of 16-bit words. The first block in EEPROM, referred to as the Configuration Block, is used to configure the Ethernet port after reset. An example of a typical Configuration Block is shown in Table 5. Additional blocks containing user data may be stored in the EEPROM. However, the Configuration Block must always start at address 00h and be stored in contiguous memory locations.

2.6.3 Reset Configuration Block

The first block in EEPROM, the Reset Configuration Block, is used to automatically program the Ethernet port with an initial configuration after a reset. Additional user data may also be stored in the EEPROM if space is ava ilable . The additiona l data are stored as 16-bit words and can occupy any EEPROM address space beginning immediately after the end of the Reset Configuration Block up to address 7Fh, depending on EEPROM size. This additional data can only be accessed through software control (refer to Section 2.24 for more information). Address space 80h to AFh is reserved.

12 DS502PP2

Word Address Value Description

FIRST WORD in DATA BLOCK

00h A120h Configuration Block Header.

The high byte, A1h, indicates a ‘C46 EEPROM is attached. The Link Byte, 20h, indicates the number of bytes to be used in this block of configuration data.

FIRST GROUP of WORDS

01h 2020h Group Header for first group of words.

Three words to be loaded, beginning at 0020h in Ethernet Port memory. 02h 0300h I/O Base Address 03h 0003h Interrupt Number 04h 0001h DMA Channel Number

SECOND GROUP of WORDS

05h 502Ch Group Header for second group of words.

Six words to be loaded, beginning at 002Ch in Ethernet Port memory. 06h E000h Memory Base Address - low word

07 000Fh Memory Base Address - high word 08h 0000h Boot PROM Base Address - low word 09h 000Dh Boot PROM Base Address - high word 0Ah C000h Boot PROM Address Mask - low word 0Bh 000Fh Boot PROM Address Mask - high word

THIRD GROUP of WORDS

0Ch 2158h Group Header for third group of words.

Three words to be loaded, beginning at 0158 in Ethernet Port memory. 0Dh 0010h Individual Address - Octet 0 and 1 0Eh 0000h Individual Address - Octet 2 and 3 0Fh 0000h Individual Address - Octet 4 and 5

CHECKSUM Value

10h 2800h The high byte, 28h, is the Checksum Value. In this example, the check-

sum includes word addresses 00h through 0Fh. The hexadecimal sum of

the bytes is D8h, resulting in a 2’s complement of 28h. The low byte, 00h,

provides a pad to the word boundary.

CS89712

Note: FFFFh is a special code indicating that there are no more words in the EEPROM.

Table 5. EEPROM Configuration Block Example

2.6.3.1 Reset Configuration Block Structure

The Reset Configuration Block is a block of contiguous 16-bit words starting at EEPROM address 00h. It can be divided into three logical sections: a header, one or more groups of configuration data

DS502PP2 13

words, and a checksum value. All words in the Reset Configuration Block are read sequentially by the Ethernet port after each reset, start ing with the header and ending with the checksum. Each group of configuration data is used to program an Ether-

CS89712

net Port regis ter (or s et of Ethe rnet Port re giste rs in some cases) with an initial non-default value.

2.6.3.2 Reset Configuration Block Header

The header (first word of the block located at EE PROM address 00h) specifies the type of EEPROM used, if a Reset Configuration block is present, and if so, how many bytes of configuration data are stored in the Reset Configuration Block.

2.6.3.3 Determining the EEPROM Type

The LSB of the high byte of the header indicates the type of EEPROM attached: sequential or nonsequential. An LSB of 0 (XXXX-XXX0) indicates a sequential EEPROM, with a 1 (XXXX-XXX1) indicating non-sequential EEPROM. The Ethernet port functions with either type of EEPROM. The Ethernet port will automatically generate sequential addresses while reading the Reset Configuration Block if a non-sequential EEPROM is used.

2.6.3.4 EEPROM Reset Configuration Block

The read-out of either a binary 101X-XXX0 or 101X-XXX1 from the high byte of the header indicates the presence of configuration data. Any other readout value terminates initialization from t he EEPROM. If an EEPROM is attached but not used for configuration, the high byte of the first word should be programmed with 00h in order to ensure that the Ethernet port will not attempt to read configuration data from the EEPROM.

2.6.3.5 Determining Number of Bytes in the Reset Configuration Block

grammed with a Reset Configuration Block containing 4 bytes of configuration data. This Reset Configuration Block occupies 6 bytes (3 words) of EEPROM space (2 bytes for the header and 4 bytes of configuration data).

2.6.4 Groups of Configuration Data

Configuration data is arranged as groups of words. Each group contains one or more words of data that are to be loaded into Ethernet Port re gisters. The first word of each group is referred to as the Group Header. The Group Header indicates the number of words in the group and the address of the Ethernet Port register where the first data word in the group is to be loaded. Any remaining words in the group are stored in successive Ethernet Port registers.

2.6.4.1 Group Header

Bits F through C of the Group Header specify the number of words in each group that are to be transferred to Ethernet Port registers (see Figure 3 for the format). This value is two less than the total number of words in the group, including the Group Header. For example, if bits F through C contain 0001, there are three words in the group (a Group Header and two words of configuration data).

Bits 8 through 0 of the Group Header specify a 9bit Ethernet Port Address. This address defines the Ethernet Port register that will be loaded with the first word of configuration data from the group. Bits B though 9 of the Group Header are forced to 0, restricting the destination address range to the first 512 bytes of Ethernet Port memory.

The low byte of the Reset Configuration Block header is known as the link byte. The value of the Link Byte represents the number of bytes of configuration data in the Reset Configuration Block. The two bytes used for the header are excluded when calculating the Link Byte value.

For example, a Reset Configuration Block header of A104h indicates a non-sequential EEPROM pro-

14 DS502PP2

2.6.5 Reset Configuration Block Checksum

A checksum is stored in the high byte position of the word immediately following the last group of data in the Reset Configuration Block. (The EEPROM address of the checksum value can be determined by dividing the value stored in the Link Byte

by two.) The checksum value is the 2’s complement of the 8-bit sum (any carry out of eighth bit is

CS89712

ignored) of all the bytes in the Reset Configuration Block, excluding the checksum byte. This sum includes the Reset Configuration Block header at address 00h. Since the checksum is calculated as the

2’s complement of the sum of all preceding bytes in the Reset Configuration Block, a total of 0 should result when the checksum value is added to the sum of the previous bytes.

2.6.6 EEPROM Example

Table 5 shows an example of a Reset Configuration

Block stored in a C46 EEPROM. Note that littleendian word ordering is used, i.e., the least significant word of a multiword datum is located at the lowest address.

2.6.7 EEPROM Read-out

If the EEDI pin is asserted high at the end of reset, the Ethernet port reads the first word of E EPROM data by:

2.6.7.1 Determining EEPROM Size

The Ethernet port determines the size of the EEPROM by checking the sense of EEDI on the tenth rising edge of EESK. If EEDI is low, the EEPROM is a ’C46 or ’CS46. If EEDI is high, the EEPROM is a ’C56, ’CS56, ’C66, or ’CS66.

2.6.7.2 Loading Configuration Data

The Ethernet port reads in the first word from the EEPROM to determine if configuration data is contained in the EEPROM. If configuration data is not stored in the EEPROM, the Ethernet port terminates initialization from EEPROM and operates using its default configuration (See Table 2). If configuration data is stored in EEPROM, the Ethernet port automatically loads all configuration data stored in the Reset Configuration Block into its internal Ethernet Port registers.

2.6.8 EEPROM Read-out Completion

1) Asserting EECS.

2) Clocking out a Read-Register-00h command on EEDO (EESK provides a 1 MHz serial clock signal).

3) Clocking the data in on EEDI.

If the EEDI pin is low at the end of the reset signal, the Ethernet port does not perform an EEPROM read-out (uses its default configuration).

First Word of a Group of Words

BADC

Once all the configuration data are transferred to the appropriate Ethernet Port registers, the Ethernet port performs a checksum calculation to verify the Reset Configuration Blocks data are valid. If the resulting total is 0, the read-out is considered valid. Otherwise, the Ethernet port initiates a partial reset to restore the default configuration.

If the read-out is valid, the EEPROMOK bit (SelfST register, bit A) is set. EEPROMOK is

Number of Words

in Group

Figure 3. Group Header

DS502PP2 15

9-bit PacketPage Address

CS89712

cleared if a checksum error is detected. In this case, the Ethernet port performs a partial reset and is restored to its default. Once ini tializat ion is compl ete (configuration loaded from EEPROM or reset to default configuration) the INITD bit (SelfST register, bit 7) is set .

2.7 Clocks

The clock source is the on-chip PLL, enabled by

strapping Port E pin 2 (PE[2]) low. This pin’s state is latched at the rising edge of nPOR (power-up). After power-up, PE[2] can be used as a GPIO.

The CS89712 contains several separate sections of logic, each clocked according to its own clock frequency requirements. See each peripheral device section for more details. The section below describes the clocking for both the ARM720T and address/data bus.

2.7.1 On-Chip PLL

The ARM720T clock can be programmed to

18.432 MHz, 36.864 MHz, 49.152 MHz, or

73.728 MHz with the PLL running at 147456 MHz, twice the highest possible CPU clock frequency. The PLL uses an external 3.6864 MHz crystal. By default, the address/data buses run at 18.432 MHz.

When the clock frequency is selected to be 36 MHz, both the ARM720T and the address/data buses are clocked at 36 MHz. When the cl ock frequency is selected higher than 36 MHz, only the ARM720T gets clocked at this higher speed. The address/data will be fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the SYSCON3 register. The clock frequency selection does not effect the EPB (external peripheral bus). Therefore, all the periph-

eral clocks are fixed, regardless of the clock speed selected for the ARM720T.

Note: After modifying the CLKCTL[1:0] bits, the next

instruction should always be a ‘NOP’.

2.7.1.1 Characteristics of the PLL Interface

When connecting a crystal to the on-chip PLL interface pins (i.e. MOSCIN and MOSCOUT), the crystal and circuit should conform to the following requirements:

• A 3.6864 MHz fundamental mode crystal should be used.

• A start-up resistor is not necessary, since one is provided internally.

• Start-up loading capacitors may be placed on each side of the external crystal and ground. Their value should be in the range of 10 pF. However, their values should be selected based upon the crystal specifications. The total sum of the capacitance of the traces between the CS89712’s clock pins, the capacitors, and the crystal leads should be subtracted from the crystal’s specifications when determining the values for the loading capacitors.

• The crystal frequency drift should be less than 100 ppm over the operating temperature range.

Alternatively, a digital clock source can be used to drive the MOSCIN pin of the CS89712. With this approach, the voltage levels of the clock source should match that of the VDD supply for the CS89712’s pads (i.e. the supply voltage level used to drive all of the non-VDD core pins on the CS89712). The output clock pin (i.e., MOSCOUT) should be left floating.

16 DS502PP2

CS89712

2.7.2 Dynamic Clock Switching

The clock frequency used for the CPU and the buses is controlled by programming the CLKCTL[1:0] bits in the SYSCON3 register. When this register is written, clock switching logic waits until the clock that is currently in use and the newly programmed clock source are both low, and then switches from the previous clock frequency to the new clock without a glitch on the clocks.

2.7.3 Ethernet Port Clock Oscillator

A 20 MHz quartz crystal or CMOS clock input is required by the Ethernet port. If a CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The clock signal should be 20 MHz ±0.01% with a duty cycle between 40% and 60%. The specifications for the crystal are described in Section 5.3.

2.8 Interrupt Controller

When unexpected events arise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled.

Table 6 shows the priority order of the exceptions.

Priority Exception

Highest Reset

. Data Abort .FIQ .IRQ . Prefetch Abort

Lowest Undefined Instruction,

Software Interrupt

Table 6. Exception Priority Handling

The CS89712 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has t he abil ity to control interrupts from 22 different FIQ and IRQ sources. Of these, seventeen are mapped to the IRQ input and five sources are mapped to the FIQ input. FIQs have a higher priority than IRQs. If two interrupts are received from within the same group (IRQ or FIQ), the order in which they are serviced must be resolved in software. All interrupts are level sensitive; that is, they must conform to the following sequence:

1) The interrupting device (either external or internal) asserts the appropriate interrupt.

2) If the appropriate bit is set in the inte rrupt mask register, then either a FIQ or an IRQ will be as-

EXPCLK

(internal)

RUN

CLKEN

Interrupt /

WAKEUP

Note: t42=0.125 sec. to 0.25 sec.

Figure 4. CLKEN Timing Exiting the Standby State

DS502PP2 17

t42

CS89712

serted by the interrupt controller. (A description for each bit in this register can be found in Section 3.6.1.

3) If interrupts are enabled the processor will jump to the appropriate address.

4) Interrupt dispatch software reads the interrupt status register to establish the source(s) of the interrupt and calls the appropriate interrupt service routine(s).

5) Software in the interrupt service routine will clear the interrupt source by some action specific to the device requesting the interrupt (i.e., reading the UART RX register).

The interrupt service routine may then re-enable interrupts, and any other pending interrupts will be serviced in a similar way. Alternately, it may return to the interrupt dispatch code, which can check for any more pending interrupts and dispatch them ac-

cordingly. The “End of Interrupt” type interrupts are latched. All other interrupt sources (i.e., external interrupt source) must be held active until its respective service routine starts executing. See Section 3.13, “End Of Interrupt Locations” for

more details.

Table 7, Table 8, and Table 9 show the names and

allocation of interrupts in the CS89712.

18 DS502PP2

CS89712

Interrupt Bit in INTMR1 and

INTSR1

FIQ 0 EXTFIQ External fast interrupt input (nEXTFIQ pin) FIQ 1 BLINT Battery low interrupt FIQ 2 WEINT Tick Watchdog expired interrupt

FIQ 3 MCINT Media changed interrupt IRQ 4 CSINT Codec sound interrupt IRQ 5 EINT1 External interrupt input 1 (nEINT[1] pin) IRQ 6 EINT2 External interrupt input 2 (nEINT[2] pin) IRQ 8 TC1OI TC1 underflow interrupt IRQ 9 TC2OI TC2 underflow interrupt IRQ 10 RTCMI RTC compare match interrupt IRQ 11 TINT 64 Hz tick interrupt IRQ 12 UTXINT1 Internal UART1 transmit FIFO empty interrupt IRQ 13 URXINT1 Internal UART1 receive FIFO full interrupt IRQ 14 UMSINT Internal UART1 modem status changed interrupt IRQ 15 SSEOTI Synchronous serial interface 1 end of transfer interrupt

Table 7. Interrupt Allocation in the First Interrupt Register

Name Comment

Interrupt Bit in INTMR2 and

INTSR2

IRQ 0 KBDINT Key press interrupt IRQ 1 SS2RX Master / slave SSI 16 bytes received IRQ 2 SS2TX Master / slave SSI 16 bytes transmitted IRQ 12 UTXINT2 UART2 transmit FIFO empty interrupt IRQ 13 URXINT2 UART2 receive FIFO full interrupt

Table 8. Interrupt Allocation in the Second Interrupt Register

Interrupt Bit in INTMR3 and

INTSR3

FIQ 0 DAIINT DAI interface interrupt

Table 9. Interrupt Allocation in the Third Interrupt Register

DS502PP2 19

Name Comment

CS89712

2.8.1 Interrupt Latencies

2.8.1.1 Operating State

The ARM720T core checks for a low level on its FIQ and IRQ inputs at each instruction boundary. The interrupt latency is there fore directly re lated to the amount of time it takes to complete execution of the current instruction when the interrupt condition is detected. First, there is a one to two clock cycle synchronization penalty. For the case where the CS89712 is operating with a 16-bit external memory system, and the program stored in one wait state FLASH memory, the worst-case interrupt latency is 251 clock cycles. This includes a delay for cache line fills for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addition, the worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x 240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress. This would give a worst-case interrupt latency of about 3.4 µs for 74 MHz operation. For operation at different frequencies and/or with 32 bit wide external memory, the latency will change accordingly.

For the nMEDCHG signal, this figure is substantially increased by the maximum time required to pass through the deglitcher, approximately 125 µs (2 cycles of the 16.384 kHz clock derived from the RTC oscillator). This results in an absolute worstcase latency of approximately 128 µs. Refer to

Table 10 for a summary.

2.8.1.2 Idle State

When leaving the Idle State as a result of an interrupt, the CPU clock is restarted after approximately two clock cycles. However, there is st ill potentially up to a 251 clock latency as described in the first section above, unless the code is written to include at least two single cycle instructions immediately after the write to the IDLE register (in which case the latency drops to a few microseconds). This is important, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.

2.8.1.3 Standby State

In the Standby State, the latency will depend on whether the system clock is shut down and if the FASTWAKE bit in the SYSCON3 register is set. If the system is configured to run from the internal PLL clock, then the PLL will always be shut down when in the Standby State. In this case, if the FASTWAKE bit is cleared, then there will be a latency of between 0.125 sec to 0.25 sec. If the FASTWAKE bit is set, then there will be a latency of between 250 µsec to 500 µsec.

Whenever the CS89712 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This prevents de-powered peripherals from draining current. Also, the inter nal pe-

ripheral’s signals are set to their Reset State.

2.8.1.4 Snooze State

All the serial data transfer peripherals included in the CS89712 (except for the master-only SSI1) have local buffering to ensure a reasonable interrupt latency response requirement for the OS of < 1 ms. This assumes that the design data rates do not exceed the data rates described in this specifica tion. If the OS cannot meet this requirement, there will be a risk of data over/underflow occurring.

20 DS502PP2

In Snooze State, the latency will be reduced to the same as for the Idle State described above. This is true at any frequency because the PLL or exte rnal clock source is not stopped. All clocks except the minimum required for LCD refresh from the internal SRAM are disabled to save further power.

To drastically reduce the potential worst ca se latency when leaving Snooze State to a few microseconds, ensure that the code contains two single cycle

CS89712

instructions immediately after the write to the SNOOZE register location.

2.8.1.5 Doze State

Since Doze State can be considered a preliminary state between Snooze State and Operating State, the only requirement for existing this state into the Operating State is for a few instructions to be executed. Therefore, the latency is based solely upon the time required to execute these instructions.

Table 10 summarizes the five external interrupt

sources and their effect on the processor interrupts.

2.9 Boot ROM

The 128 bytes of on-chip Boot ROM contain an instruction sequence that initializes the device and then configures UART1 to receive 2048 bytes of serial data that will then be placed in the on-chip SRAM. Once the download is complete, execution jumps to the start of the on-chip SRAM. This would allow, for example, code to be downloaded

to program system FLASH during a product’s manufacturing process. See Section , “Appendix B:

Boot Code” for details of the ROM Boot Code with comments to describe the stages of execution.

Selection of the Boot ROM option is determined by the state of the nMEDCHG pin during a power on reset. If nMEDCHG is high while nPOR is active, then the CS89712 will boot from an external memory device connected to CS[0] (normal boot mode). If nMEDCHG is low, then the boot will be from the on-chip ROM. Note that in both cases, following the de-assertion of nPOR, the CS89712 will be in the Standby State and require a low-to-high transition on the external WAKEUP pin in order to actually start the boot sequence.

The effect of booting from the on-chip Boot ROM is to reverse the decoding for all chip selects internally. Table 11 shows this decoding. The control signal for the boot option is latched by nPOR, which means that the remapping of addresses and bus widths will continue to apply until nPOR is asserted again. After booting from the Boot ROM, the contents of the Boot ROM can be read back from address 0x0000.0000 onwards, and in normal state of operation the Boot ROM contents can be read back from address range 0x7000.0000.

2.10 Memory Map

The lower 2 GByte of the address space is allocated to memory. The 512 MBytes of address space from

Interrupt

nEXTFIQ Not de glitched; must be

nEINT1–2 Not deglitched Worst-case 3.4 µsec

nMEDCHG Deglitched by 16 kHz

DS502PP2 21

Input State Operating State

Worst-case 3.4 µsec active for 251 clock cycles to ensure detection

clock; must be active for at least 125 µs to be detected

at 74 MHz

Worst-case latency

of 128 µsec at 74

MHz

Table 10. External Interrupt Source Latencies

Latency

Idle State

Latency

Worst-case 251 clocks: if only single cycle instructions, less than 1 µsec

As above As above

Worst-case 80 µsec: if only single cycle instructions, 125 µsec

Including PLL / osc. settling time, ~

0.25 sec when FASTWAKE = 0, or

approx. 500 µsec when FASTWAKE = 1

As above

Standby State Latency

0xC000.0000 to 0xDFFF.FFFF is allocated to

Address Range Chip Select

0000.0000–0FFF.FFFF CS[7] (Internal only)

1000.0000–1FFF.FFFF CS[6] (Internal only)

2000.0000–2FFF.FFFF nCS[5]

3000.0000–3FFF.FFFF nCS[4]

4000.0000–4FFF.FFFF nCS[3]

5000.0000–5FFF.FFFF nCS[2]

6000.0000–6FFF.FFFF nCS[1]

7000.0000–7FFF.FFFF nCS[0]

Table 11. Chip Select Address Ranges After Boot From

On-Chip Boot ROM

SDRAM. The 1.5 GByte, less 8 kbytes for internal registers, is not accessible in the CS89712. The

CS89712

MMU should be programmed to generate an abort exception for access to this area.

Internal peripherals are addressed through a set of internal registers from address 0x8000.0000 to 0x8000.3FFF.

Table 12 shows how the 4-Gbyte address range of

the ARM720T processor (as configured within this chip) is mapped. The memory map shown assumes that two CL-PS6700 PC Card controllers are connected. If this functionality is not required, then the nCS[4] and nCS[5] memory is available. The external boot ROM is not fully decoded (i.e., the boot code will repeat within the 256 Mbyte space from 0x7000.0000 to 0x8000.0000).

When booted from on chip boot ROM, the SRAM is fully decoded up to 128 kbytes. Access to any location above this range will wrap within the range.

Address Contents Size

0xF000.0000 Reserved 256 Mbytes 0xE000.0000 Reserved 256 Mbytes 0xD000.0000 Reserved 256 Mbytes 0xC000.0000 SDRAM 64 Mbytes

0x8000.4000 Unused ~1 Gbyte 0x8000.2000 Internal registers 8 kbytes 0x8000.0000 Internal registers 8 kbytes 0x7000.0000 Boot ROM (nCS[7]) 128 bytes 0x6000.0000 SRAM (nCS[6]) 48k bytes 0x5000.0000 PCMCIA-1 (nCS[5]) 4 x 64 Mbytes 0x4000.0000 PCMCIA-0 (nCS[4]) 4 x 64 Mbytes

0x2000.0000-0x2000.02FF Expansion (nCS[2]) 0x2000.0300-0x2000.030F Ethernet Port (on nCS[2])

0x2000.0310-0x2FFF.FFFF Expansion (nCS[2]) cont.

22 DS502PP2

0x3000.0000 Expansion (nCS[3]) 256 Mbytes

0x1000.0000 ROM Bank 1 (nCS[1]) 256 Mbytes 0x0000.0000 ROM Bank 0 (nCS[0]) 256 Mbytes

256 Mbytes

Table 12. CS89712 Memory Map in External Boot Mode

CS89712

2.11 Memory and I/O Expansion Interface

Six separate linear memory or expansion segments are decoded by the CS89712, two of which can be reserved for two PC Cards, each interfacing to a separate single CL-PS6700 device. Each segment is 256 Mbytes in size. Two additional segments (in addition to these six) are dedicated to the on-chip SRAM and ROM. The on-chip ROM space is fully decoded, and the SRAM space is decoded up to the maximum size of the video frame buffer programmed in the LCDCON register (128 kbytes). Beyond this address range the SRAM space is not fully decoded (i.e., any accesses beyond 128 kbyte range get wrapped around to within 128 kbyte range). Any of the six segments are configured to interface to a conventional SRAM-like interface, and can be individually programmed to be 8-, 16-, or 32-bits wide, to support page mode access, and to execute from 1 to 8 wait states for non-sequential accesses and 0 to 3 for burst mode accesses. The zero wait state sequential access feature is designed to support burst mode ROMs. For writable memory devices which use the nMWE pin, zero wait state sequential accesses are not permitted and one wait state is the minimum which should be programmed in the sequential field of the appropriate MEMCFG register. Bus cycles can also be extended using the EXPRDY input signal.

Page mode access is accomplished by setting SQAEN = 1, enabling accesses of one random address followed by three sequential addresses, etc., while keeping nCS asserted. These sequential bursts can be up to four words long before nCS is released to allow DMA and refreshes to take place. This can significantly improve bus bandwidth to devices such as ROMs which support page mode. When SQAEN = 0, all accesses to m emory are by random access without nCS being de-asserted between accesses. Again nCS is de-asserted after four consecutive accesses to allow DMA.

Bits 5 and 6 of the SYSCON2 register independently enable the interfaces to the CL-PS6700 (PC Card slot drivers). When either of these interfaces are enabled, the corresponding chip select (nCS4 and/or nCS5) becomes dedicated to that CL-PS6700 interface. The state of SYSCON2 bit 5 determines the function of chip select nCS4 (i.e., CL-PS6700 interface or standard chip select functionality); bit 6 controls nCS5 in a similar way. There is no interaction between these bits.

For applications that require a display buffer smaller than 48k bytes, the on-chip SRAM can be used as the frame buffer.

Before entering the Snooze State, the SRAM at 0x6000.0000 must be updated, under program control, with data to be displayed during the Snooze State. In a system using the on-chip SRAM as the frame buffer in normal operation, Snooze State can be entered without requiring any data transfer first, assuming data is stored in the on-chip SRAM in 1bit -per-pixel format.

The width of the boot device can be chosen by selecting values of PE[1] and PE[0] during power on reset. The inputs in Table 13 are latched by the rising edge of nPOR to select the boot option.

PE[1] PE[0] Boot Block

(nCS0)

0 0 32-bit 0 1 8-bit 1 0 16-bit 1 1 Undefined

Table 13. Boot Options

2.12 SDRAM Controller

The SDRAM controller provides all the connections to directly interface to up to two banks of SDRAM, and the width of the memory interface is programmable from 16 to 32 bits wide. Both banks have to be of the same width. Each of the two banks supported can be up to 256 Mbits in size. The sig-

DS502PP2 23

CS89712

nals nRAS nCAS, and nWE are provided for SDRAM. Two chip selects are provided for supporting up to 2 rows of SDRAMs. The SDRAM devices are put into self-refresh mode when the SDRAM controller is put into standby. The SDRAM clock is halted as well.

The controller supports read, write, refresh, precharge and mode register write requests to the SDRAM. Data is transferred to and from the SDRAM as unbroken quad accesses (either quad word or for 16 bit memory, quad halfword), which is a convenient data packet size for the ARM cache line fills. For the CPU to read smaller than a quad access, the SDRAM controller will discard t he extra data. For CPU writes smaller than a quad access, the SDQM pins (SDRAM data byte mask selects) are used to force the SDRAMs to ignore invalid data. For CPU access sizes lar ger than a qu ad access, multiple quad accesses are issued to the SDRAM.

The SDRAM controller can access a total memory size of 2-64 Mbytes. Each individual SDRAM should be NEC or compatible SDRAM memory in sizes of 16-256 Mbits, arranged as shown in

Table 14 and Table 15.

Chip selects for row 1 SDRAMs should be connected to nSDCS[0]. If row 2 is used, these devices should connect to nSDCS[1].

For 32-bit memory access, four SDQM data byte mask selects are provided to control individual byte lanes within each row. For 16-bit memory access only, SDQM[1:0] are used. For a 32-bit memory access configuration with each row containing two 16-bit wide SDRAMs, the high order SDRAM should have UDQM (upper SDQM) connected to SDQM[3] and LDQM (lower SDQM) connected to SDQM[2]. The low order SDRAM follows the same convention: USDQM is connected to SDQM[1], and LDQM is connected to SDQM[0].

Memory address line multiplexing is done internally so that the address mapping is contiguous.

Table 16 indicates how the SDRAM address pins

are connected to the CPU’s address pins. Note that small SDRAM devices will not use all of these pins. For example, A[12:11] may not be required. However, the bank select pins BA[1:0], are required by all SDRAMs. Smaller devices may only have one bank, so BA1 may not be needed.

Arrangement of SDRAMs

SDRAM details

Density

(Mbits)

16 4 818

64 4 81 8

128 4

24 DS502PP2

Width

(bits) CRDCRDCRDCRDCR D

8414

16 2 1 2

8 41442 8 16 212224 32 111122

8 41 4

Table 14. SDRAM Configurations (SDRAM 32-Bit Memory Interface)

(C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs)

4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes

16 21222 4

256 4

8 16 21 2

Table 14. SDRAM Configurations (SDRAM 32-Bit Memory Interface)

SDRAM Details Arrangement of SDRAMs

(C = # Columns of SDRAM, R = # Rows of SDRAM, D = # of SDRAMs)

2 Mbytes 4 Mbytes 8 Mbytes 16 Mbytes 32 Mbytes 64 Mbytes

CS89712

Density

(Mbits)

16 4 414

64 4 414428

128 4 414

256 4

Width

(bits)

8 212

16 111

8 212224

16 111122

8 212224

16 111122

8 212

16 111122

CRDCRDCRDCRDCRDCRD

Table 15. SDRAM Configurations (SDRAM 16-Bit Memory Interface)

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CS89712

SDRAM Address

Pins

A0. A1. A2. A3. A4. A5. A6. A7. A8. A9. A10. A1 1. A12. BA0. BA1.

Table 16. SDRAM Address Pin Connections

CS89712 Pin Names

a27/dra0 a26/dra1 a25/dra2 a24/dra3 a23/dra4 a22/dra5 a21/dra6 a20/dra7 a19/dra8 a18/dra9 a17/dra10 a16/dra11 a15/dra12 a14/dra13 a13/dra14

2.13 SDRAM Initialization

The SDRAM is initialized in the power-on sequence as follows:

3) Once the precharge is complete, and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well. (Only required for NEC SDRAM)

4) Eight or more refresh cycles must be performed.

2.14 CL-PS6700 PC Card Interface

Two of the expansion memory areas are dedicated to supporting up to two CL-PS6700 PC Card controller devices. These are selected by nCS4 and nCS5 (must first be enabled by bits 5 and 6 of SYSCON2). For efficient, low power operation, both address and data are carried on the lower 16 bits of the CS89712 data bus. Accesses are initiated by a write or read from the area of memory allocated for nCS4 or nCS5. The memory map within each of these areas is segmented to allow different types of PC Card accesses to take place, for attribute, I/O, and common memory space. The CLPS6700 internal registers are memory mapped within the address space as shown in Table 17.

Note: Due to the operating speed of the CL-PS6700,

this interface is supported only for a processor speed of 18 MHz.

1) To stabilize internal circuits when power is applied, a 200+ µs pause must precede any signal toggling.

2) After the pause, all banks must be precharged using the Precharge command (including the precharge all banks command).

A complete description of the protocol and AC timing characteristics can be found in the CL-PS6700 data sheet. A transaction is initiated by an access to the nCS4 or nCS5 area. The chip select is asserted, and on the first clock, the upper 10 bits of the PC Card address, along with 6 bits of size, space, and slot information are put out onto the lower 16 bits

Access Type Addresses for CL-PS6700 Interface 1 Addresses for CL-PS6700 Interface 2

Attribute 0x4000.0000–0x43FF.FFFF 0x5000.0000– 0x53FF.FFFF I/O 0x4400.0000–0x47FF.FFFF 0x5400.0000–0x57FF.FFFF Common memory 0x4800.0000–0x4BFF.FFFF 0x5800.0000–0x5BFF.FFFF CL-PS6700 registers 0x4C00.0000–0x4FFF.FFFF 0x5C00.0000–0x5FFF.FFFF

Table 17. CL-PS6700 Memory Map

26 DS502PP2

CS89712

of the CS89712’s data bus. Only word (i.e., 4-byte) and single-byte accesses are supported, and the slot field is hardcoded to 11, since the slot field is defined as a ‘Reserved field’ by the CL-PS6700. The chip selects are used to select the device to be accessed. The space field is made directly from the A26 and A27 CPU address bits, according to the decode shown in Table 18. The size field is forced to 11 if a word access is required, or to 00 if a byte access is required. This avoids the need to configure the interface after a reset. On the second clock cycle, the remaining 16 bits of the PC Card address are multiplexed out onto the lower 16 bits of the data bus. If the transaction selected is a CL-PS6700 register transaction, or a write to the PC Car d (assuming there is space available in the CL-PS6700’s internal write buffer) then the access will continue on the following two clock cycles. During these following two clock cycles the upper and lower halves of the word to be read or written will be put onto the lower 16 bits of the main data bus.

The ‘ptype’ signal on the CL-PS6700s should be connected to the CS89712’s WRITE output pin. During PC Card accesses, the polarity of this pin changes, and it becomes low to signify a write and high to signify a read. It is valid with the first half word of the address. During the second half word of the address, it is always forced high to indicate to the CL-PS6700 that the CS89712 has initiated either the write or read.

The PRDY signals from each of the two CLPS6700 devices are connected to Port B bits 0 and

1, respectively. When the PC CARD1 or PC CARD2 control bits in the SYSCON2 register are de-asserted, these port bits are available for GPIO. When asserted, these port bits are used as the PRDY signals. When the PRDY signal is de-asserted (i.e., low), it indicates that the CL-PS6700 is busy accessing its card. If a PC CARD access is attempted while the device is busy, the PRDY signal will cause the CS89712’s CPU to be stalled. The CS89712’s CPU will have to wait for the card to become available. DMA transfers to the LCD can still continue in the background during this period of time (as described below). The CS89712 can access the registers in the CL-PS6700, regardless of the state of the PRDY signal. If the CS89712 needs to access the PC CARD via the CL-PS6700, it waits until the PRDY signal is high before initiating a transfer request. Once a request is sent, the PRDY signal indicates if data is available.

In the case of a PC Card write, write s can be posted to the CL-PS6700 device, with the same timing as CL-PS6700 internal register writes. Writes will normally be completed by the CL-PS6700 device independent of the CS89712 processor activity. If a posted write times out, or fails to complete for any other reason, then the CL-PS6700 will issue an interrupt (i.e., a WR_FAIL interrupt). In the case where the CL-PS6700 write buffer is already full, the PRDY signal will be de-asserted (i.e., driven low) and the transaction will be stalled pending an available slot in the buffer. In this case, the CS89712’s CPU will be stalled until the write can

Space Field Value PC CARD Memory Space

00 Attribute 01 I/O 10 Common memory 11 CL-PS6700 registers

Table 18. Space Field Decodi ng

DS502PP2 27

CS89712

be posted successfully. While the PRDY signal is de-asserted, the chip select to the CL-PS6700 will be de-asserted and the main bus will be released so that DMA transfers to the LCD controller can continue in the background.

In the case of a PC Card read, the PRDY signal from the CL-PS6700 will be de-asserted until the read data is ready. At this point, it will be reasserted and the access will be completed in the same way as for a register ac cess. In t he case of a byt e access, only one 16-bit data transfer will be required to complete the access. While the PRDY signal is deasserted, the chip select to the CL-PS6700 will be de-asserted, and the main bus will be released so that DMA transfers to the LCD controller can continue in the background.

The CS89712 will re-arbitrate for the bus when the PRDY signal is reasserted to indicate that the read or write transaction can complete. The CPU will stall until the PC Card access is completed.

select, and data is transferred on the next two clocks if a word read (one clock if a byte read).

There is no support within the CS89712 for detecting time-outs. The CL-PS6700 device must be programmed to force the cycle to be completed (with invalid data for a read) and then generate an interrupt if a read or write access has timed out (i.e., RD_FAIL or WR_FAIL interrupt). The system software can then determine which access was not successfully completed by reading the status registers within the CL-PS6700.

The CL-PS6700 has support for DMA data transfers. However, DMA is supported only by software emulation because the DMA address generator built into the CS89712 is dedicated to the LCD controller interface. If DMA is enabled within the CL-PS6700, it will assert its PDREQ signal to make a DMA request. This can be connected to one

of the CS89712’s external interrupts and be used to interrupt the CPU for servicing the DMA request.

A card read operation may be split into a request cycle and a data cycle, or it may be combined i nto a single request/data transfer cycle. This depends on whether the requested data is available in the internal CL-PS6700 prefetch buffer.

The request portion of the cycle, for a card read, is similar to the request phase for a card write (described above). If the requested data is available in the prefetch buffer, the CL-PS6700 asserts the PRDY signal before the rising edge of the third clock and the CS89712 continues the cycle to read the data. Otherwise, the PRDY signal is de-asserted, and the request cycle is stalled. The CS89712 may then allow the DMA addres s genera tor to gain control of the bus, to allow LCD refreshes to continue. When the CL-PS6700 is ready with the data, it asserts the PRDY signal. The CS89712 then arbitrates for the bus and, once the request is gra nted, the suspended read cycle is resumed. The CS89712 resumes the cycle by asserting the appropriate chip

Each of the CL-PS6700 devices can generate an interrupt PIRQ. Since the PIRQ signal is an open drain on the CL-PS6700 devices, two CL-PS6700 devices may be wired OR’ed to the same interrupt. The circuit can then be connected to one of the CS89712’s active low external interrupt sources. On the receipt of an interrupt, the CPU can read the interrupt status registers on the CL-PS6700 devices to determine the cause of the interrupt.

All transactions are synchronized to the EXPCLK output from the CS89712 in 18.432 MHz mode. The EXPCLK should be permanently enabled, by setting the EXCKEN bit in the SYSCON1 register, when the CL-PS6700 is used. The reason for this is that the PC Card interface and CL-PS6700 internal write buffers need to be clocked after the CS89712 has completed its bus cycles.

A GPIO signal from the CS89712 can be connected to the PSLEEP pin of the CL-PS6700 devices to allow them to be put into a power saving state before the CS89712 enters the Standby State. It is essen-

28 DS502PP2

CS89712

Address (W/B) Data in Memory

(as seen by the

CS89712)

Word + 0 (W) 11223344 44 33 22 11 44 33 22 11 11223344 11223344 Word + 1 (W) 11223344 44 33 22 11 44 33 22 11 44112233 44112233 Word + 2 (W) 11223344 44 33 22 11 44 33 22 11 33441122 33441122 Word + 3 (W) 11223344 44 33 22 11 44 33 22 11 22334411 22334411 Word + 0 (H) 11223344 dc dc 22 11 44 33 dc dc 00001122 00003344 Word + 1 (H) 11223344 dc dc 22 11 44 33 dc dc 22000011 44000033 Word + 2 (H) 11223344 44 33 dc dc dc dc 22 11 00003344 00001122 Word + 3 (H) 11223344 44 33 dc dc dc dc 22 11 44000033 22000011 Word + 0 (B) 11223344 dc dc dc 11 44 dc dc dc 00000011 00000044 Word + 1 (B) 11223344 dc dc 22 dc dc 33 dc dc 00000022 00000033 Word + 2 (B) 11223344 dc 33 dc dc dc dc 22 dc 00000033 00000022 Word + 3 (B) 11223344 44 dc dc dc dc dc dc 11 00000044 00000011

Note: dc = don’t care

Byte Lanes to Memory / Ports / Registers R0 Contents

Big Endian Memory Little Endian Memory

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 Big Endian Little Endian

Table 19. Effect of Endianness on Read Operations

tial that software monitors the appropriate status registers within the CL-PS6700s to ensure that there are no pending posted bus transactions before the Standby State is entered. Failure to do this will result in incomplete PC Card accesses.

2.15 Endianness

The CS89712 uses a little endian configuration for internal registers. However, it is possible to connect the device to a big endian external memory system. The big-endian / little-endian bit in the ARM720T control register sets whether the CS89712 treats words in memory as being stored in big endian or little endian format. Memory is viewed as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second, and so on. In the little endian scheme, the lowest numbered byte in a word is considered to be the least significant byte of the

word and the highest numbered byte is the most significant. Byte 0 of the memory system should be connected to D[7:0] in this case. In the big endian scheme the most significant byte of a word is stored at the lowest numbered byte, and the least significant byte is stored at the highest numbered byte. Therefore, byte 0 of the memory system should be connected to D[31:24]. Load and store are the only instructions affected by the Endianness.

Table 19 and Table 20 demonstrate the behavior of

the CS89712 for read and write operations, including the effect of performing non-aligned word ac cesses. The register definition section defines the behavior of the internal CS89712 registers in the big endian mode in more detail. For further infor-

mation, refer to ARM Application Note 61, “Big

and Little Endian Byte Addressing”.

DS502PP2 29

CS89712

Address

(W/B)

Word + 0 (W) 11223344 44 33 22 11 44 33 22 11 Word + 1 (W) 11223344 44 33 22 11 44 33 22 11 Word + 2 (W) 11223344 44 33 22 11 44 33 22 11 Word + 3 (W) 11223344 44 33 22 11 44 33 22 11 Word + 0 (H) 11223344 44 33 44 33 44 33 44 33 Word + 1 (H) 11223344 44 33 44 33 44 33 44 33 Word + 2 (H) 11223344 44 33 44 33 44 33 44 33 Word + 3 (H) 11223344 44 33 44 33 44 33 44 33 Word + 0 (B) 11223344 44 44 44 44 44 44 44 44 Word + 1 (B) 11223344 44 44 44 44 44 44 44 44 Word + 2 (B) 11223344 44 44 44 44 44 44 44 44 Word + 3 (B) 11223344 44 44 44 44 44 44 44 44 Note: Bold indicates active byte lane.

Contents

Byte Lanes to Memory / Ports / Registers

Big Endian Memory Little Endian Memory

7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24

Table 20. Effect of Endianness on Write Operations

2.16 Internal UARTs and SIR Encoder

The CS89712 contains two built-in UARTs that offers similar functionality to National Semiconduc-

tor’s 16C550A device. Both UARTs can support bit rates of up to 115.2 kbits/s and include two 16byte FIFOs: one for receive and one for transmit.

One of the UARTs (UART1) supports the three modem control input signals CTS, DSR, and DCD. The additional RI input, and RTS and DTR output modem control lines are not explicitly supported but can be implemented using GPIO ports in the CS89712. UART2 has only the RX and TX pins.

UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control). Three interrupts can be generated by UART1: RX, TX, and modem status interrupts. Only two can be generated by UART2: RX and TX. The RX interrupt is asserted when the RX FIFO becomes half full or if the FIFO is non-empty for longer than three character length times with no more charac-

ters being received. The TX interrupt is asserted if the TX FIFO buffer reaches half empty. The modem status interrupt for UART1 is generated if any of the modem status bits change state. Framing and parity errors are detected as ea ch byte is received and pushed onto the RX FIFO. An overrun error generates an RX interrupt immediately. All error bits can be read from the 11-bit wide data register. The FIFOs can also be programmed to be one byte depth only (i.e., like a conventional 16450 UART with double buffering).

The CS89712 also contains an IrDA (Infrared Data Association) SIR protocol encoder as a post-processing stage on the output of UART1. This encoder can be optionally switched into the TX and RX signals of UART1, so that these can be used to drive an infrared interface dire ctly. If the SIR pr otocol encoder is enabled, the UART TXD1 line is held in the passive state and transitions of the RXD1 line will have no effect. The IrDA output pin

30 DS502PP2

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