FEATURES
! IEEE 802.3 compliant 10Base-T and 100Base-X
Physical Interface.
! Media Supported:
— 10Base-T
— 100Base-TX
— 100Base-FX (with optional fiber transceiv erinstalled )
! IEEE 802.3u MII Interface with extended register
support.
! LED indicators for Power, Link Status, Collision,
Full/Half Duplex, Transmit Activity, Receive
Activity, 100 Mb/s Speed, and 10 Mb/s Speed.
! Hardware configurable through jumper settings,
or software configurable through the MII interface.
! Operates from single 5 V supply, or may be
optionally configured for interface to 3.3 V MII.
ORDERING INFORMATION
CS8952-CQ 0° to +70° C 100-pin TQFP
CDB8952 Evaluation Board
CDB8952
Advanced Product Databook
Crystal LAN™ 10Base-T
and 100Base-X Transceiver
Evaluation Board
DESCRIPTION
The CDB8952 EvaluationBoardprovidesaplatformfor
evaluating the CS8952 10Base-T and 100Base-X
Transceiver. It is designedtopluginto a transceivertest
box via a standard 40-pin MII connector. System designers can use the CDB8952 to fully exercise the
CS8952 without the time and expense of custom
prototyping.
Though the CBD8952 is configured from the factory for
5 V operation with the powersupplied from thetest box,
it may also be configured for 3.3 V MII systems.
The CDB8952 may be optionally configured with a fiber
interface module for 100Base-FX testing.
S2 S1
TEST RESET
MII
PHYAD4
PHYAD3
PHYAD2
PHYAD1
PHYAD0
TST1
Y1
RX
LED2
J6
POWER
C4
LNK
LED3
LED8
L2
L1
T1
Transformer
FDX
COL
LED5
LED4
Isolation
U6
HFBR-5103
Fiber
Transceiver
J2
Shielded
RJ45
C46
MII_PWR +5V
J5
HDR15
C27
U4
TP4
HDR34
C28
HDR35
MIIDRV
C26
HDR1
J1
HDR42
TXCLK
S3
AN0
HDR4
AN1
HDR5
TP2
TXS0
HDR6
CDB8952 REV. B EVALUATION BOARD
CS8952
TXS1
TCM
HDR7
LED6
SPD100
HDR43
C1 C3
U2
TX
SPD10
LED1
LED7
TP1
CIRRUS LOGIC ADVANCED P RODUCT DATABOOK
DS206DB2 OCT ‘01
Copyright Cirrus Logic, Inc. 1998
(All Rights Reserved)
CDB8952
Crystal LAN™ 10Base-T and 100Base-X Transceiver
INTRODUCTION
This manual provides information specifically on
the CDB8952 Evaluation board and generally on
any design incorporating the CS8952 Crystal-
TM
LAN
10Base-T and 100Base-X Transceiver.
The reader should have a general knowledge of
hardware design and Ethernet operation.
Background Information
• IEEE Std 802.3u-1995 (ISO/IEC 8802.3:1996)
CSMA/CD Access Method and Physical Layer
Specifications
• IEEE Std 802.3u-1995 Supplement Clause 28
(Auto-
• CS8952 CrystalLAN
Negotiation)
TM
10Base-T and
100Base-X Transceiver Datasheet
Evaluation Kit Contents
The CDB8952 Evaluation Board Kit includes the
following:
Quantity Item
1 CDB8952 Evaluation Board
1 CS8952 Datasheet
1 CDB8952 Reference Manual
1 CDB8952 Kit Packing List
Table 1. Evaluation Kit Contents
J5 - MII Power. When the board is connected to a
system that does not supply power through the MII
connector, +5 V or +3.3 V must be supplied here.
J6 - CS8952 Core Power. +5 V must be supplied
here from either J5 (if +5 V is supplied through the
MII connector) or an external power supply.
J13 - MII Connector (Table 3).
Pin Function Pin Function
1 MII Power 21 MII Power
2 MDIO 22 Ground
3 MDC 23 Ground
4 RXD3 24 Ground
5 RXD2 25 Ground
6 RXD1 26 Ground
7 RXD0 27 Ground
8 RX_DV 28 Ground
9 RX_CLK 29 Ground
10 RX_ER/RXD4 30 Ground
11 TX_ER/TXD4 31 Ground
12 TX_CLK 32 Ground
13 TX_EN 33 Ground
14 TXD0 34 Ground
15 TXD1 35 Ground
16 TXD2 36 Ground
17 TXD3 37 Ground
18 COL 38 Ground
19 CRS 39 Ground
20 MII Power 40 MII Power
Table 3. MII Connector
BOARD CONFIGURATION
I/O Connectors
Configuration Jumpers and Switches
S1 - Board Reset. Depressing this push-button
switch will force the CS8952 into a reset state.
J1 - External TX_CLK. This connector may be
used to supply TX_CLK when HDR42 and HDR43
are set appropriately.
S2 - Test 1 (not populated). This switch is used to
select a factory test mode, and should not be
pressed during normal operation.
J2 - RJ45, Twisted-pair Media (Table 2).
S3 - Physical Address Select. This 5-position
Pin Function
1TD+
2TD3RD+
456 RD78-
Table2.Twisted-pairMedia
CIRRUS LOGIC ADVANCED P RODUCT DATABOOK
2 DS206DB2
switch is used to select the physical address to
which the CS8952 will respond. “Open” or “Off”
will set the corresponding physical address bit to
ZERO, while “Closed” or “On” will set it to ONE.
The CS8952 checks the positions of this switch
only during power-up or reset. If any switch position is changed, a reset or power cycle is required
before the new settings will take effect.
CDB8952
Crystal LAN™ 10Base-T and 100Base-X Transceiver
NOTE: Physical address 00000 is a special broadcast
address. All devices will respond to this address
in addition to theone selected using S3.Setting
S3 to 00000 will cause the CS8952 to set the
ISOLATE bit in the Basic Mode Control Register, isolating itself from all MII signals except
MDC and MDIO. It will remain isolated until this
bit is cleared.
Care should be taken when reading from physical address 00000 when multiple devices
reside on the same MII.
HDR1 - MII Drive Select. When this header is left
open, the CS8952 MII drivers will conform to the
IEEE 802.3u specification. When a shorting cap is
installed, the CS8952 MII drivers will be reduced
to 4mA.
The CS8952 checks the status of HDR1 only during power-on orreset. A reset or power cycle is required before any changes in this jumper setting
will take effect.
HDR4, HDR5 - Auto-Negotiation Select 0 and 1.
These headers are used to select the forced or advertised auto-negotiation modes as indicatedin Table 4.
HDR5
(AN1)
pins 2-3
shorted
pins 1-2
shorted
open pins 2-3
open pins 1-2
open open 100/10 Auto Full/Half
pins 2-3
shorted
pins 2-3
shorted
pins 1-2
shorted
pins 1-2
shorted
HDR4
(AN0) Speed
open 10 Forced Half
open 10 Forced Full
100 Forced Half
shorted
100 Forced Full
shorted
pins 2-3
shorted
pins 1-2
shorted
pins 2-3
shorted
pins 1-2
shorted
Table 4. Auto-Negotiation Select
10 Auto Half
10 Auto Full
100 Auto Half
100 Auto Full
Forced/
Auto
Full/Hal
fDuplex
The CS8952 checks the status of HDR4 and HDR5
only during power-on or reset. A resetor power cy-
cle is required before any changes in these jumper
settings will take effect.
HDR6, HDR7 - Transmit Slew Rate Select 0 and 1.
These headers are used to select the rise and fall
times of the 100BASE-TX transmitter output
waveform as indicated in Table 5.
HDR7
(TXSLEW1)
pins 2-3 shorted pins 2-3 shorted 0.5 ns
open pins 2-3 shorted 1.0 ns
pins 1-2 shorted pins 2-3 shorted 1.5 ns
pins 2-3 shorted open 2.0 ns
open open 2.5 ns
pins 1-2 shorted open 3.0 ns
pins 2-3 shorted pins 1-2 shorted 3.5 ns
open pins 1-2 shorted 4.0 ns
pins 1-2 shorted pins 1-2 shorted 4.5 ns
Table 5. Transmit Slew Rate
HDR6
(TXSLEW0)
Rise/Fall
Time
HDR15 - Table 6 describes the effect of shorting
the listed pin pairs.
HDR34 - Test 0. This header is forfactory test purposes only, and should be left open for normal operation.
HDR35 - Test 1. This header is forfactory test purposes only, and should be left open for normal operation.
HDR42 - TX_CLK Source Select. This header, in
conjunction with HDR43, is used to select the
TX_CLK source. When pins 1 and 2 are selected,
TX_CLK is supplied from theCS8952CLK25 output. When pins 2 and 3 are shorted, TX_CLK is
supplied externally from J1. When no shorting cap
is installed, HDR43 must be configured so that
TX_CLK is an output from the CS8952.
NOTE: No shorting cap should be installed on this
header when TX_CLK is configured as an output (see HDR43).
HDR43 - TX_CLK Mode Select. (Table 7)
The CS8952 checks the status of HDR43 only dur-
ing power-on or reset. A reset or power cycle is required before any changes in this jumper setting
will take effect.
CIRRUS LOGIC ADVANCED P RODUCT DATABOOK
DS206DB2 3
CDB8952
Crystal LAN™ 10Base-T and 100Base-X Transceiver
Pins Function Description
1-2 Low Power Start The CS8952 will enter a low power mode following reset. Only the circuitry
necessary to maintain media impedance and the MII Serial Management
Interface will be operational. The CS8952 checks the status of these pins only
during power-on or reset. A reset or power cycle is required before any changes
in this jumper setting will take effect.
3-4 MII Receive Enable MII signals RXD[3:0], RX_CLK, RX_DV, and RX_ER are tristated.
5-6 Power Down The CS8952 is forced into a low power mode. Only the circuitry necessary to
maintain media impedance will be operational.
7-8 CRS Mode Control The CRS pin will be asserted for receive activity only. The CS8952 checks the
status of these pins only during power-on or reset. A reset or power cycle is
required before any changes in this jumper setting will take effect.
9-10 Bypass Scrambler The scrambler and descrambler are bypassed, and NRZI FX mode is enabled.
The CS8952 checks the status of these pins only during power-on or reset. A
reset or power cycle is required before any changes in this jumper setting will
take effect.
11-12 Bypass 4B/5B Coders The 4B5B encoder and decoder are bypassed and 5-bit code groups are used.
RX_ER is used as the fifth receive bit, and TX_ER as the fifth transmit bit. The
CS8952 checks the status of these pins only during power-on orreset. A reset or
power cycle is required before any changes in this jumper setting will take effect.
13-14 Bypass Symbol
Alignment
15-16 Loopback The CS8952 will be placed in loopback mode. When operating in 100 Mb/s
17-18 MII Isolate The CS8952 will exit from reset with all MII signals tristated except MDIO and
19-20 10BASE-T Serial Mode If the CS8952 is in 10 Mb/s mode, data is transferred serially on RXD0 and
4B5B coders, scramblers, and NRZI coders are all bypassed, and the CS8952
will make no attempt to identify code-group boundaries. Data on RXD[4:0] and
TXD[4:0] may contain bits from two code groups. The CS8952 checks the status
of these pins only during power-on or reset. A reset or power cycle is required
before any changes in this jumper setting will t ake effect.
mode, the loopback will be inside the PMD block, and scrambled NRZI data will
be routed directly to the NRZI input port on the descrambler. When in 10 Mb/s
mode, the CS8952 will perform a local ENDEC loopback.
MDC. The CS8952 checks thestatus of these pins only during power-on or reset.
A reset or power cycle is required before any changes in this jumper setting will
take effect.
TXD0, and the full MII interface is disabled. When the CS8952 is in 100Mb/s
mode, shorting these pins has no effect. The CS8952 checks the status of these
pins only during power-on or reset. A reset or power cycle is required before any
changes in this jumper setting will take effect.
Table 6. Effect of shorting the l isted pin pairs
HDR43 TX_CLK pin CLK25 pin
pins 1-2 shorted input 25 MHz clock
open input not used
pins 2-3 shorted output not used
Table 7. TX_CLK Mode Select
NOTE: When TX_CLK is an input, a shorting cap must
installed on HDR42 to supply TX_CLK to the
CS8952 (see HDR42).
CIRRUS LOGIC ADVANCED P RODUCT DATABOOK
4 DS206DB2
LED Indicators
LED1 - Transmitter Active Indicator.
LED2 - Receiver Active Indicator.
LED3 - Link OK Indicator.
LED4 - Full Duplex Indicator.
LED5 - Collision Indicator.
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