Cirrus Logic CS8920A-CQ Datasheet

CS8920A

Advanced Product Databook

FEATURES

■ Single-Chip IEEE 802.3 Ethernet Controller with

Direct ISA-Bus Inte rface

■ Implements Industry-Standard Plug and Play

■ Full Duplex Operation

■ Auto-Negotiation of Full and Half duplex Modes

■ Recognizes Received Magic Packet™ Frames and

Requests the Processor to Power Up

■ Supported by Complete Family of Device Drivers

■ Efficient PacketPage™ Architecture Operates in

I/O and Memory Space, and as DMA Slave

■ On-Chip RAM Buffers Transmit & Receive Frames

■ 10BASE-T Port with Internal Analog Filters

■ AUI Port for 10BASE2, 10BASE5 and 10BASE-F

■ Programmable Receive Features:

— StreamTransfer™ for Reduced CPU Overhead
— Auto-Switch Between DMA and On-Chip Memory
— Early Interrupts for Frame Pre-Processing

■ Four LED Drivers for Link Status, Full Duplex, and

LAN Activity

■ Small 144-pin TQFP package, and minimal exter-

nal components (transformer, crystal and
optional EEPROM)

ORDERING INFORMATION

Contact Cirrus to check on the availability of CS8920A
for use in ISA for m-fact or adapte r- card app lic ation s.
CS8920A-CQ

CDK8920A Developer's Kit

0 to 70É C 144-pin TQFP

&U\VWDO/$1

TM

ISA

Plug-and-Play Ethernet

Controller

DESCRIPTION

The CS8920A is a low-cost Ethernet LAN Control­ler optimized for Industry Standard Architecture
(ISA) Personal Computers. Its highly-integrated
design eliminates the need for costly external com ­ponents required by other Ethernet controllers.

In addition to high integration, the CS8920A offers
a broad range of performance features and config­uration options. Its unique PacketPage
architecture automatically adapts to changing net­work traffic patterns and available system
resources. The result is increased system efficien­cy and minimized CPU overhead.

The CS8920A is available in a thin 144-pin TQFP
package ideally suited for small form-factor, cost­sensitive Ethernet applications, such as desktop
and portable motherboards. With the CS8920A,
system engineers can design a complete Plug­and-Play Ethernet circuit that occupies less than

2.0 square inches (14 sq. cm) of board space.

Crystal LAN is a trademark of Cirrus Logic, Inc.
Magic Packet is a trademark of Advanced Micro Devices, Inc.

EEPROM

CS8920 ISA Ethernet Controller

LED

EEPROM

Control

ISA
Bus

I
S
A

Logic

&

Plug

and

Play

Memory

Manager

RAM

802.3
MAC

Engine

and Auto

Negotiation

SEP ‘97 DS238PP2

Control

Copyright  Cirrus Logic, I nc. 1997

(All Rights Reserv ed)

20 MHz

XTAL

Clock

Encoder/

Decoder

&

PLL

Power

Manager

10BASE-T

RX Filters &

Receiver

10BASE-T

TX Filters &

Transmitter

AUI

Transmitter

AUI

Collision

AUI

Receiver

RJ-45 10BASE-T

Attachment

Unit

Interface

(AUI)

CS8920A

CONTENTS

1.0 INTRODUCTION

1.1 General Description . . . . 4

1.2 System Applications . . . . 5

1.3 Key Features and Benefits . . . 5

1.4 Enhancements Made in CS8920A . 8

2.0 PIN DESCRIP TION

2.1 Pin Diagram . . . . . . 9

2.2 Pin Description . . . . . . 10

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview . . . . . . . 14

3.2 ISA Bus Interface . . . . . 15

3.3 Reset and Initialization . . . . 16

3.4 Plug and Play . . . . . . 18

3.5 Configuration with EEPROM . . 19

3.6 Programming the EEPROM . . 23

3.7 Boot PROM Operation . . . . 24

3.8 Low-Power Modes . . . . . 25

3.9 LED Outputs . . . . . . 26

3.10 Media Access Control (MAC) . . 27

3.11 Encoder/Decoder (ENDEC) . . 33

3.12 10BASE-T Transceiver . . . . 34

3.13 Attachment Unit Interface (AUI) . 37

3.14 External Clock Oscillator . . . 38

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview . . . . 39

4.2 PacketPage Memory Map . . . 40

4.3 Bus Interface Registers
Product Identification Code . . 42

DMA Start of Frame . . . . 43

DMA Frame Count . . . . 43

RxDMA Byte Count . . . . 43

EEPROM Command . . . . 44

EEPROM Data . . . . . 44

Receive Frame Byte Counter . . 44

4.4 Status and Control Registers . . 45

4.4.1 Status/Control Bit Definitions 46

4.4.2 Status/Control Register Summary 47

4.5 Status/Control Register Details
(0) Interrupt Status Queue . . 50
(3) Receiver Configuration (RxCFG) 51
(4) Receiver Event (RxEvent) . 52
(5) Receiver Control (RxCTL) . 53
(7) Transmit Configuratio n (TxCFG) 5 4
(8) Transmit Event (TxE vent) . 55
(9) Transmit Command (TxCM D) 56

(B) Buffer Configuration (BufCFG) 57
(C) Buffer Event (BufEvent) . . 59
(D) Advance In ter ru pt C on tro l

and Status (ADVintCTL/ST) . 60
(10) Rece ive Miss Coun ter ( RxM ISS) 61
(12) Trans. Collision Count (TxCOL) 61
(13) Line Control (LineCTL) . . 62
(14) Line Status (LineST) . . . 63
(15) Self Control (SelfCTL) . . 64
(16) Self Status (SelfST) . . . 65
(17) Bus Control (BusCTL) . . 66
(18) Bus Status (BusST) . . . 67
(19) Test Control (TestCTL) . . 68
(1C) AUI Time Domain Reflectometer 6 9
(1D) Auto Negotiation Control

(AutonegCTL) . . 70
(1E) Auto Negotiation Status

(AutonegST) . . 71

4.6 Initiate Transmit Register
Transmit Command (TxCMD) . 72
Transmit Length (TxLength) . . 73

4.7 Address Filter Regi sters
Logical Address Table (hash table) 74
Individual Address (IEEE address) 74

4.8 Plug n Play Resource Registers . 75

4.9 Receive and Transmit Frame Locatio ns 80

4.10 8 and 16-bit Transfers . . . . 80

4.11 Memory Mode Operation . . . 81

4.12 I/O Space Operation . . . . 83

5.0 OPERATION

5.1 Servicing the Interrupt Status Queue 86

5.2 Basic Receive Operation . . . 88

5.3 Receive Frame Address Filtering . 95

5.4 Rx Missed and Collision Counters . 98

5.5 Receive DMA . . . . . . 98

5.6 Auto-Switch DMA . . . . . 103

5.7 StreamTransfer . . . . . . 106

5.8 Transmit Operation . . . . . 108

5.9 Full Duplex Considerations . . . 115

5.10 System Wakeup with Wakeup Frames 115

6.0 TEST MODES

6.1 Boundary Scan Test . . . . . 121

7.0 ABSOLUTE MAXIMUM RATINGS . 125
Recommended Operating Conditions . 125

8.0 OPERATING CONDITIONS . . . 125

2 DS238PP2

9.0 DC CHARACTERISTICS

Crystal . . . . . . . . 125

Power Supply . . . . . . 125

Digital Inputs/Outputs . . . . 126

10BASE-T Interface . . . . 127

AUI Interface . . . . . . 127

9.1 CAPACITANCE . . . . . 127

10.0 SWITCHING CHARACTERISTICS

ISA Bus Timing . . . . . 128

10BASE-T Timing . . . . . 132

AUI Timing . . . . . . . 133

Boot PROM Timing . . . . 135

EEPROM Timing . . . . . 135

11.0 10BASE-T WIRING DIAGRAM . . 136

12.0 AUI WIRING DIAGRAM . . . . 137

CS8920A

13.0 CRYSTAL OSCILLATOR . . . . 137

14.0 PHYSICAL DIMENSIONS . . . . 138

15.0 GLOSSARY . . . . . . . . 139

DS238PP2 3

CS8920A

1.0 INTRODUCTION

1.1 General Description

The CS8920A is a single-chip, ISA Plug-and­Play, full-duplex, Ethernet solution,
incorporating all of the analog and digital cir­cuitry needed for a complete Ethernet
circuit. Major functional blocks include: indus­try-standard plug-and-play protocol engine, a
direct ISA-bus interface, an 802.3 MAC engine
with auto-negotiation and wake-up frame recog­nition capability, integrated buffer memory; a
serial EEPR OM interface, and a complete an alog
front end with both 10BASE-T and AUI.

Plug and Play

The CS8920A implements Plug and Play in ac­cordance with the Intel/Microsoft Plug and Play
ISA Specification Version 1.0a, allowing inter­rupts, DMA channels, IO base address, memory
base address, and optional BootPROM address
to be selected dynamically, by either a system
BIOS, an operat ing syste m or an appl ication pro­gram such as the Configuration Manager. The
CS8920A supports 11 interrupts and 3 DMA
channels.

frames on chip, eliminating the need for com­plex, inefficient memory management schemes.
The on-chip bu ffer manager supports full-duplex
operation.

802.3 Ethernet MAC Engine

The CS8920A’s Ethernet Media Access Control
(MAC) engine is fully compliant with the IEEE

802.3 Ethernet stand ard (ISO/IEC 8802-3, 1993),
and supports full-duplex operation. The full-du­plex mode may be entered by a command from
the host, or vi a auto-negotiation using link-p ulse
signaling.

Magic Packet Frames

The MAC machine recognizes Magic Packet
frames, and can send a wakeup signal to a sys­tem power management chip via a dedicated
control line or vi a an interrup t pin.

EEPROM Interface

The CS8920A provides a simple serial
EEPROM interface that allows configuration in­formation to be stored in EEPROM, and then
loaded auto matically at power-up.

Direct ISA-Bus Interface

The CS8920A has a direct ISA-bus interface
with full 24 mA driv e capability. The CS8920A
operates in either 24-bit memory space, 16-bit
I/O space, or with external DMA controllers
(three 16-bit channels), providing maximum de­sign flexibilit y.

Complete Analo g Front End

The CS8920A’s analog front end incorporates a
Manchester encoder/decoder, clock recovery cir­cuit, 10BASE-T transceiver, and complete
Attachment Unit Interface (AUI). It provides
manual and automatic selection of either
10BASE-T or AUI, and offers three on-chip
LED drivers for link status, bus status, an d Eth-

Integrated Memory

The CS8920A incorporates a 4-Kbyte page of
on-chip memory, eliminating the cost and board
area associate d with external memor y chips. Un­like most other Ethernet controllers, the
CS8920A buffers entire transmit and receive

4 DS238PP1

ernet line ac tivity.

The 10BASE-T transceiver includes drivers, re­ceivers, and analog filters, allowing direct
connection to low-cost isolation transformers. It

supports 100, 120, and 150 Ω shielded and un­shielded cabl es, extende d cable len gths.

CS8920A

EEPROM

I

S

A

20 MHz

XTAL

CS 8920A

Figure 1.1. Complete Ethernet Motherboard Sol ution

The AUI port provides a direct interface to
10BASE-2, 10BASE-5 and 10BASE-FL net­works, and is capable of driving a full 50-meter
AUI cable.

1.2 System Applications

The CS8920A is designe d to work well in either
motherboard o r adapter app lications.

Motherboard LANs

The CS8920A requires the minimum number of
external components needed for an Ethernet
node, allowing a complete Ethernet circuit that
occupies as little as 2.0 square inches of PCB

area (Figure 1.1). In addition, the CS8920A’s
power-saving features make it a perfect fit for
power-sensitive p ortable and desktop PCs. Moth­erboard design op tions includ e:

(2.0 sq. in.)

RJ-45 10B ASE - T

use of the CS8920A without an attached
EEPROM.

Plug-and-Play Ethernet Adapter Cards

The CS8920A’s highly efficient StreamTrans-

TM

fer

and Auto-Switch DMA options, make it
an excellent choice for high-performance, low­cost, ISA adapter cards (Fig. 1.2). The
CS8920A’s wide rang e of configuration options,
listed belo w, allow engineers to desig n Ethernet
solutions that meets their particular system re­quirements.

• A Boot PROM can b e added to support disk-

less appli cations.

• The 10BASE-T transmitter and receiver im-

pedance can be adjusted to sup port 100, 120,
or 150 Ω twisted pair cables.

• The EEPROM, used to store node-specific

information, such as the Ethernet Individual

• On-chip LED ports can be used for either

optional LEDs, o r as programmable outputs.

Address, can be eliminated by storing infor­mation in the syst em CMOS.

• The 20 MHz crystal oscillator may be re-

1.3 Key Features and Benefits

Very Low Cost

placed by a 20 MHz clo ck signal.

The CS8920A is designed to provi de the lowest-

Note: while operation of the CS8920A is possi­ble without the use of an attached EEPROM,
special design considerations are required. Fur-

cost Ethernet solutions avai lable for ISA desktop
motherboards, portable motherboards, and
adapter car ds. Cost-s aving feat ures inclu de:

thermore, some of the CS8920A functions, such
as Plug and Play capabilities and wakeup frame
recognition are not possible without an attached

• Integrated RAM eliminates the need for ex-

pensive external memory chips.

EEPROM. Please contact Crystal’s CS8920A
technical support for more information on the

DS238PP1 5

CS8920A

• On-chip 10BASE-T filters allow desig ners to

use simple isolation transformers instead of
more costly filter/tra nsformer packages .

• The serial EEPROM port, used for configu-

ration and initialization, eliminates the need
for expensive s witches and j umpers.

• The CS8920A is designed to be used on a

2-layer circuit board instead of a more ex­pensive multi-layer boa rd.

• The CS8920A-based solution offers the

smallest footprint available, saving valuable
printed circuit board area.

• A set of certifie d software dri vers is av ailable

at no charge, eliminating the need for costly
software development.

High Performance

The CS8920A is a ful l 16-bit Ethernet controller
designed to provide optimal system performance
by minimizing time on the ISA bus and CPU
overhead per frame. It offers equal or superior
performance for less money when compared to

other Ethernet control lers. The CS8920A’s Pack­etPage architecture allows software to select
whichever access method is best suited to each
particular CPU/ISA-bus configuration. When

compared to olde r I/O-sp ace design s, P acketPage
is faster, simpler and more efficient.

To boost performance further, the CS8920A in­clude several key features that increase
throughput and l ower CPU overhead, including:

• StreamTransfer cuts up to 87% of interrupts

to the host CPU duri ng large block trans fers.

• Auto-Switch DMA allows the CS8920A to

maximize throughput while minimizing
missed frames.

• Early interrupts allow the host to preprocess

incoming frames.

• On-chip buffering of full frames cuts the

amount of host bandwidth need ed to manage
Ethernet traffic.

Low Power and Lo w Noise

For low power needs, the CS8920A offers three
power-down options: Hardware Standby, Hard­ware Suspend, and Software Suspend. In
Standby mode, the chip is powered down with
the exception of the 10BASE-T receiver, which
is enabled to listen for link activity. In either
Hardware or Software Suspend mode, the re-

LED

RJ-45

Attachment

Unit

Interface

(AUI)

’245

Boot PROM

EEPROM

20 MHz

XTAL

CS8920A

Figure 1.2. Full-Featured ISA Adapter Solution

6 DS238PP1

CS8920A

EEPROM

93C56

CS

DO

CLK

ISA

BUS

SA[0:14]

SD[0:7]

20 MHz

4.7 k

135 136

XTAL1 XTAL2 SLEEP TEST RES

16

15
8

141

7
6

142

57

28
29
90
89
83
52
91

114

44
43
92

75
76
77
78
79

106

34
33
32
30
31

16
17
14
15

9

10

EECS
EEDATAIN

EEDATAOUT
EESK

LA[17:23]
BALE
SA[0:16]
MEMW

MEMR

IOW
IOR
REFRESH

SBHE

AEN

RESET
MEMCS16
IOCS16

IOCHRDY
SD[0:15]
IRQ3

IRQ4

IRQ5
IRQ6
IRQ7
IRQ9
IRQ10
IRQ11

IRQ12
IRQ14
IRQ15
DRQ5
DACK5
DRQ6
DACK6

DRQ7

DACK7

1
4
3

DI

2

7

17

Ω

116

115

CS8920A

BSTATUS/HCI

LINKLED/HC0

Ω

4.99 k

131

RXD-

RXD+

TXD-

TXD+

DO-

DO+

CI-

CI+

DI-

DI+

EWAKE

LANLED

LOCALLED

CSOUT

, 1%

130

129

126

125

122
121
120
119
118
117

39.2

113

3

140

139

5

8

24.3

Ω, 1%

24.3

Ω, 1%

Ω

, 1%

680

Ω

680

Ω

680

Ω

Boot-PROM

27C256

20

CE

22

OE

100

68 pF

PD[0:7]

Ω, 1%

39.2 Ω, 1%

39.2

0.1

µ

F

10 BASE T

Isolation

Transforme r

1

1:1

3
6

1:

8

2

Ω

, 1%

5 V

19

1

2

.1 µF

39.2 Ω, 1%

0.1 µF

74LS245
OE
DIR

16

14
11

10
9

.1 µF

AUI Isola tion
Transformer

1

1:1

2
4

1:1

5
7

1:1

8

12 V

16
15 3
13
12
10

9

6

3
2

1

10

9
2

12

5
6

RJ45

15 pin D

Figure 1.3. Typica l Connection Diagram

DS238PP1 7

CS8920A

ceiver is disabled and power consumption drops
to the micro-Amp range.

In addition, the CS8920A has been designed for
very low noise emission, thus shortening the
time required for E MI testing and qual ification.

Complete Support

The CS8920A comes with a suite of software
drivers for immediate use with most industry
standard network operating systems. In addition,
complete evaluation kits and manufacturing
packages are available, significan tly reducing the
cost and time required to produce new Ethernet
products.

1.4 Enhancements Made in CS8920A

The functional enhancements made to the
CS8920A includ e the following:

To support software compatibility with existing
device drivers, the CS8920A’s Product Identifi­cation Code register has the same Product ID
Number as the CS8920. The CS8920A’s revi­sion numb er has been incremented.

The CS8920A has added the EWAKE pin to the
boundary scan.

The FDX_LED pin of the CS8920 has been re d­fined as the local-LAN-activity LED on the
CS8920A. The LOCALLED will light when
one of two event s occurs:

• the CS8920A tran smits onto the network, or

• the CS8920A receives a frame from the net-

work and that frame is addressed to this

station (i.e., the frame’s address passes the
CS8920A’s address filt er).

The Plug and Play standard provide s for an Aux­illary Key which is normally used for testing
purposes or to program the EEPROM. The
CS8920A will respond to the Auxillary Key at
any time. The CS8920 responded to the Auxil­lary Key only if Plug and Pl ay was enabled , or if
the CS8920 had det ected that the EEPROM co n­tained a bad CRC value. This meant that the
CS8920 would ignore the Auxillary Key in no n­Plug and Play mode as long as the CRC was
valid.

8 DS238PP1

2.0 PIN DE SCRIPTION

2.1 Pin Diagram

EESK

EECS

144

143

142

141

1

2

EWAKE

ASUB1

LOCALLED

EEDO

EEDI

CSOUT

DRQ7

DACK7

DVSS1
DVDD1
DSUB1

DRQ6

DACK6

DRQ5

DACK5

SD15
SD14

SD13

SD12

DVDD2

DVSS2

SD11

SD10

SD9
SD8

MEMW

MEMR

IRQ14

IRQ15
IRQ12

IRQ1 1

IRQ10

3

4

5
6

7

8

9

10

11

12

13

14

15

16

17
18
19
20

21

22

23

24

25

26

27
28
29

30

31
32

33

34

35

36

LANLED

140

CS8920A

ASUB2

ASUB3

LINKLED/HC0

139

138

ASUB4

XTAL2

XTAL1

AVDD1

134

137

136

135

133

RXD+

AVSS1

RES

RXD-

129

132

131

130

CS8920A

144-Pin

TQFP

AVSS2

AVDD2

127

128

(Q)

CI-

DI-

TXD-

TXD+

AVSS3

AVDD3

DO-

DO+

120

126

122

125

124

123

121

CI+

119

118

DI+

117

SLEEP

TEST

RESET

BSTATUS/HC1

116

115

114

113

112

111

110

109

108

107
106

105

104

103

102
101

100

99
98
97
96

95

94
93

92

91
90

89

88

87

86

85

84
83
82

81

80

79

78
77

76
75
74

73

IRQ2 /I R Q 9

SD7

SD6

SD5

SD4
DVDD5

DVSS5

SD3
SD2
SD1
SD0

DSUB3

DVDD4
DVSS4

IOCHR DY

AEN
IOW

IOR

SA16

SA15

SA14

SA13

SA12
REFRESH
SA11

SA10

SA9

IRQ7

IRQ6
IRQ5

IRQ4
IRQ3

37

38

39

40

41

42

43

444546

MCS16

IOCS16

47

484950

LA17

LA18

LA19

LA20

525354

51

LA21

LA22

LA23

SBHE

DSUB2

555657

BAL E

DVSS3

DVDD3

58

SA0

61

59

60

SA1

SA2

SA3

626364

SA4

SA5

SA6

65

SA7

66

SA8

67

6869707172

DS238PP2 9

CS8920A

2.2 Pin Description

ISA Bus Interface

Symbol Pin Number Type Description

SA0-SA8
SA9-SA11
SA12-SA16

LA17-LA23 45-51 I Latchable Address Bus: Address decoding for the buffered version of the

BALE 57 I Buffered Address Latch Enable: Rising edge signals the CS8920A to

SD0-SD3
SD4-SD7
SD8-SD11
SD12-SD15

RESET 114 I Reset: Active-high asynchronous input used to reset the CS8920A. Must

AEN 91 I Address Enable: When TEST is high, the active-high AEN input indicates

MEMR 29 I Memory Read: Active-low input indicates that the host is executing a

MEMW 28 I Memory Write: Active-low input indicates that the host is executing a

MCS16 44 OD24 Memory Chip Select 16: Open-drain, active-low output generated by the

REFRESH 83 I Refresh: Active-low input indicates to the CS8920A that a DRAM refresh

IOR 89 I I/O Read: When IOR is low and a valid address is detected, the CS8920A

IOW 90 I I/O Write: When IOW is low and a valid address is detected, the

58-66
80-82
84-88

96-99

102-105

27-24
21-18

I System Address Bus: Address decoding for the ISA addresses including

Boot PROM and memory addres ses. SA0-SA15 a re used for I/O read/wr ite
operations. SA0-SA16 are used in for Memory read and write operations.

upper ISA address bits. Used for early address decode. Latched on the
trailing edge of the BALE signal.

decode the LA17:LA23. The trailing edge of BALE is used to latc h the
address and hold it for the duration of the current bus cycle.

B24 System Data Bus: Bi-directional 16-bit System Data Bus used to transfer

data between the CS8920A and the host.

be stable for at least 400 ns before the CS8920A recognizes the signal as
a valid reset.

to the CS8920A that the system DMA controller has control of the ISA bus.
When AEN is high, the CS8920A will not respond t o an IO or Memory
space access.

Memory Read operation.

Memory Write operat ion.

CS8920A when it recognizes an address on the ISA bus that corresponds
to its assigned Memo ry space (CS8920A must be in Memory Mode with
the MemoryE bit (Registe r 17, BusCTL, Bit A) set f or MCS16 to go active).
Tri-stated when not active.

cycle is in progress. W hen REFRESH is low, MEMR, MEMW, IOR, IOW,
DMACK0, DMACK1, and DMACK2 are ignored.

outputs the contents of the selected 16-bit I/O register onto the System
Data Bus. IOR is ignored if REFRESH is low.

CS8920A writes the data on the System Data Bus into the selected 16-bit
I/O register. IOW is ignored if REFRESH is low.

Pin Types:

dI = Dif ferential Input Pair I = Inp ut G = Ground

dO = Differe ntial Output Pa ir O = Output ts = Tri-State

B = Bi-Directional with Tri-State Output P = Power w = Internal Weak Pullup

OD = Open Drain Output

Digital outputs are followed by drive in mA (Example: OD24 = Open Drain Output with 24 mA drive).

10 DS238PP2

CS8920A

ISA Bus Interface (continued)

Symbol Pin Number Type Description

IOCS16 43 OD24 I/O Chip Select 16-bit: Open-drain, active-low output generated by the

CS8920A when it recognizes an address on the ISA bus that
corresponds to its assigned I/O space. Tri-stated when not active.

IOCHRDY 92 OD24 I/O Channel Ready: When driven low, this open-drain, active-h igh

output extends I/O Read and Memory Read cycles to the CS8920A. This
output is functional when th e IOCHRDYE bit in the Bus Control r egister
(Register 17) is clear. This pin is always tri-stated when the IOCHRDYE
bit is set.

SBHE 52 I System Bus High Enable: Active-low input indicates a data transfer on

the high byte of the System Data Bus (SD8-SD15). After a hardware or
software reset, provide a HIGH to LOW and then a LOW to HIGH
transition on SBHE signal before any IO or memory access isdone to the
CS8920A. *

IRQ2/IRQ9
IRQ3-IRQ7
IRQ10-IRQ12
IRQ14-IRQ15

DRQ5
DRQ6
DRQ7

DACK5
DACK6
DACK7

106
75-79
34-32
30-31

16
14

9

17
15
10

O24ts Interrupt Request: Active-high output indicates the presence of an

interrupt event. The pin goes low after the host reads a non-zero value
from the Interrupt Status Queue (ISQ).

O24ts DMA Request: Active-high, tri-stateable output used by the CS8920A to

request a DMA transfer. Only one DMA Request output is used (one is
selected during configuration). All non-selected DMA Request outputs
are pla ced in a hig h-i mped anc e st ate.

I DMA Acknowledge: Active-low input indicates acknowledgment by the

host of the corresponding DMA Request output.

EEPROM and Boot PROM Interface

Symbol Pi n Number Type Description

EESK 142 O4 EEPROM Serial Clock: Serial clock used to clock data into or out of the

EEPROM.
EECS 1 41 O4 EEPROM Chip Select: Active-high output used to select the EEPROM.
EEDI 7 Iw EEPROM Data In: Serial input used to receive data from the EEPROM.

Connects to the DO pin on the EEPROM. EEDI is also used to sense the

presence of the EEPROM.
EEDO 6 O4 EEPROM Data Out: Serial output used to send data to the EEPROM.

Connects to the DI pin on the EEPROM. When TEST is low, this pin

becomes the output for the Boundary Scan Test.
CSOUT 8 O4 Chip Select for External Boot PROM: Active-low output used to select

an external Boot PROM when the CS8920A decodes a valid Boot PROM

memory address.
Pin Types:

dI = Dif ferential Input Pair I = Inp ut G = Ground

dO = Differe ntial Output Pa ir O = Output ts = Tri-State

B = Bi-Directional with Tri-State Output P = Power w = Internal Weak Pullup

OD = Open Drain Output

Digital outputs are followed by drive in mA (Example: OD24 = Open Drain Output with 24 mA drive).
* For operation of the CS8920A in 16 bit mode, a transition on the

software reset .

SBHE line is required after a hardware or

DS238PP2 11

10BASE-T Interface

Symbol Pin Number Type Description

TXD+
TXD-

RXD+
RXD-

125
126

129
130

dO 10BASE-T Transmit: Differential output pair drives 10 Mb/s

Manchester-encoded data to the 10BASE-T transmit pair.

dI 10BASE-T Receive: Differential input pair re ceives 10 Mb/s

Manchester-encoded data from the 10BASE-T receive pair.

Attachment Unit Interface (AUI)

Symbol Pin Number Type Description

DO+
DO-

DI+
DI-

CI+
CI-

121
122

117
118

119
120

dO AUI Data Out: Differential output pair drives 10 Mb/s

Manchester-encoded data to the AUI transmit pair.

dI AUI Data In: Differential input pair receives 10 Mb/s Manchester-encoded

data from the AUI receive pair.

dI AUI Collision In: Differe ntial input pair c onnects to the AUI collision pai r.

A collision is indicated by the presence of a 10 MHz +/ -15% signal with
duty cycle no worse than 60/40.

CS8920A

Pin Types:

dI = Dif ferential Input Pair I = Inp ut G = Ground

dO = Differe ntial Output Pa ir O = Output ts = Tri-State

B = Bi-Directional with Tri-State Output P = Power w = Internal Weak Pullup

OD = Open Drain Output

Digital outputs are followed by drive in mA (Example: OD24 = Open Drain Output with 24 mA drive).

12 DS238PP2

CS8920A

General Pins

Symbol Pin Number Type D escr ipti on

XTAL1
XTAL2

SLEEP 116 I W H ardware Sleep: Active-low input used to enable the two hardware sleep

EWAKE 3 O4w Wakeup Signal: The CS8920A asserts EWAKE high when a wakeup

LINKLED
or
HC0

BSTATUS
or
HC1

LANLED 140 OD10 LAN Activity LED: During normal operation, this active-low output goes

LOCALLED 5 OD10 Local Activity LED: During normal operation, this active-low output goes

TEST 115 IW T est En able : Active-low input used to put the CS8920A in Boundary Scan

RES 131 I

DVDD1 ­DVDD5

DVSS1 ­DVSS5

DSUB1 ­DSUB3

AVDD1 ­AVDD3

AVSS1 ­AVSS7

AVSS1 ­AVSS4

Pin Types:

dI = Dif ferential Input Pair I = Inp ut G = Ground

dO = Differe ntial Output Pa ir O = Output ts = Tri-State

B = Bi-Directional with Tri-State Output P = Power w = Internal Weak Pullup

OD = Open Drain Output

Digital outputs are followed by drive in mA (Example: OD24 = Open Drain Output with 24 mA drive).

135
136

139 OD10 Link Good LED or Host Controlled Output 0: When the HCE0 bit of the

113 OD10 Bus Status or Host Controlled Output 1: When the HCE1 bit of the Self

12, 22,

55, 94, 101

11, 23, 56 ,

93, 100

13, 54,

95

133, 128,

123

4, 124, 127,

132, 134,

137, 138

4, 134,

137, 138

I/O Crystal: A 20 MHz crystal should be connected across these pins. If a

crystal is not used, a 20 MHz signal should be connected to XTAL1 and
XTAL2 should be left open. (See section 9.0 and 13.0.)

modes: Hardware Suspend and Hardware Standby. (See section 3.8.)

frame is detected on the Ethernet receiver.

Self Control register (Register 15) is clear, this active-low output is low
when the CS8920A detects the presence of valid link pulses. When the
HCE0 bit is set, the host may drive this pin low by setting the HCBO in the
Self Control register.

Control register (Register 15) is clear, this active-low output is low when
receive activity causes an ISA bus access. When the HCE1 bit is set, the
host may drive this pin low by setting the HCB1 in the Self Control register.

low f or 6 ms w hene ver th ere is a rece ive pac ket, a tran smi t pa cke t, or a
collision. During Hardware Standby mode, th is output is driv en low when
the receiver detects network activity.

low for 6 ms whenever there is either a receive packet addressed to this
node, or a transmit packet.

Test mode. For normal operation, this pin should be high or left open.
Reference Resistor: This input should be connected to a 4.99 KΩ +/-1%

resistor needed for biasing of internal analog circuits.

P Digital Power: Provides 5 V +/- 5% power to the digital circuits of the

CS8920A.

G Digital Ground: Provides ground reference (0V) to the digital circuits of the

CS8920A.
Provide additional ground references (0V) to digital circuits of the CS8920A.

P Analog Power: Provides 5 V +/- 5% power to the analog circuits of the

CS8920A.

G Analog Ground: Provide ground reference (0V) to the analog circuits of the

CS8920A.

Provided additional ground references (0V) to analog circuits of the
CS8920A.

DS238PP2 13

CS8920A

3.0 F UNCTIONAL DESCRIPTION

3.1

Overview

During normal operati on, the CS8920A perfo rms
two basic functions: Ethernet packet transmis­sion and reception. Before transmission or
reception is poss ible, the CS8920A must be co n­figured.

Configuration

The CS8920A must be configured for packet
transmission and reception at power-up or reset.
Various parameters must be writt en into its inter­nal Configuration and Control registers such as
Memory Base Address; Ethernet Physical Ad­dress; what frame types to receive; and which
media interface to use. Configuration data can
either be written to the CS8920A by the host
(across the ISA bus), or loaded automatically
from an external EEPROM. Operation can begin
after configurati on is comple te.

memory, either as a Memory o r I/O space opera­tion.

In the second phase of packet transmission, the
CS8920A converts the frame into an Ethernet
packet, then transmits it onto the network. The
second phase begins wit h the CS8920A transmit­ting the preamble and Start-of-Frame delimiter
as soon as the pro per number of bytes have been
transferred into its transmit buffer (5, 381, 1021
bytes or full frame, depen ding on configuration).
The preamble and Start-of-Frame are followed
by the Destination Address, Source Address,
Length field and LLC data (all supplied by the
host). If the frame is less than 64 bytes, includ­ing CRC, the CS8920A adds pad bits if
configured to do so. Finally, the CS8920A ap­pends the prope r 32-bit CRC value.

Section 5.8 provides a detailed description of
packet transm ission.

Packet Reception

Sections 3.1 and 3.3 describe the configuration
process in de tail. Section 4.4 provides a detailed
description of the bits in the Configuration and
Control Registers.

Packet Trans mission

Packet transmission occurs in two phases. In the
first phase, the host moves the Ethernet frame

into the CS8920A’s buffer memory. The first
phase begins with the host issuing a Transmit
Command. This informs the CS8920A that a
frame is to be transmitted and tells the chip
when (i.e. after 5, 381, or 1021 bytes have been
transferred or after the full fra me has been trans­ferred to the CS8920A) and how the frame
should be sent (i.e. with o r without C RC, with or
without pad bits, etc.). The host follows the
Transmit Command with the Transmit Length,
indicating how much buffer space is required.
When buffer space is available, the host writes
the Ethernet frame into the CS8920A’s internal

Like packet transmission, packet reception oc­curs in two phases. In the first phase, the
CS8920A receives an Ethernet packet and stores
it in on-chip memory. The first phase begins
with the receive frame passing through the ana­log front end and Manchester decoder where
Manchester dat a is converted to NRZ data. Next,
the preamble and Start-of-Frame delimiter are
stripped off and the receive frame is sent t hrough
the address filter. If the frame’s Destination Ad­dress matches the criteria programmed into the
address filter, the packet is stored in the
CS8920A’s internal memory. The CS8920A then
checks the CRC, and depending on the configu­ration, informs the processor that a frame has
been rece ived.

In the second phase, the host transfers the re­ceive frame across the ISA bus and into host
memory. Receive frames can be transferred as
Memory space operations, I/O space operations,
or as DMA ope rations using h ost DMA. In addi-

14 DS238PP2

CS8920A

tion, the CS8920A provides the capability to
switch between Memory or I/O operation and
DMA operation by usi ng Auto-Switch DMA and
StreamTransfe r.

Sections 5.2 through 5.7 provide a detailed de­scription of packet reception.

Reset/Boot/Sle ep

Nine resets can be activated on the CS8920A.
Three are activated by the V

power supply

CC

line; one is activated when the EEPROM fails
checksum; one is activated on a Plug and Play
instruction; one is activated when RESET is set;
and three ar e activated with sleep modes.

A sleep mode disabl es the CS8920A (completel y
or partially) to reduce power consumption. "Sus­pend" describes the CS8920A in the completely
disabled mode. "Standby" describes the
CS8920A in the partially disabled mode when
most of its circuits except the receiver are dis­abled. The CS8920A can be "Awakened" when
the receiver detects an d receives line activity.

After reset, p acket transmis sion and rece ption are
disabled. Either an external EEPROM must be
used to start the CS8920A, or the host must di­rectly set up registers using Plug and Play
protocols.

The CS8920A is o ptimized for 16-bit data trans­fers, operating in either Memory space, I/O
space, or as a DMA slave.

Note that ISA-bus operation below 8 MHz
should use the CS8920A’s Receive DMA mode
to minimize missed frames. See Sectio n 5.5 for a
descriptio n of Receive DMA operation .

Memory Mode Operation

When configured for Memory Mode operation,
the CS8920A’s internal RAM is mapped into a
contiguous 4-Kbyte block of host memory, pro­viding the host with direct access to the
CS8920A’s internal registers and frame buffers.
The host initiates Read operations by driving the
MEMR pin low and Write operations by driving
the

MEMW pin low.

For additional in formation about Memory Mode,
see Section 4. 11.

I/O Mode Operation

When configured for I/O Mode operation, the
CS8920A is accessed through eight, 16-bit I/O
ports that are mapped into sixteen contiguous
I/O locatio ns in the host sys tem’s I/O space. I/O
Mode is the default configuration for the
CS8920A and is always enabled.

Contact Crystal’s CS8920A technical support for
more information regarding the use of the
CS8920A without an external EEPROM.

For an I/O Read or Write opera tion, the AEN pin
must be low, and the 16-bit I/O address on the
ISA System Address bus (SA0 - SA15) must
match the address space of the CS8920A. For a

3.2

ISA Bus Interface

Read,

IOR must be low, and for a Write, IOW

must be low.

The CS8920A provides a direct interface to I SA
buses running at clock rates from 8 to 11 MHz.
Its on-chip bus drivers are capable of delivering

For additional information about I/O Mode, see

Section 4.12.
24 mA of drive current, allowing the CS8920A
to drive the ISA bus directly, without added ex-

Interrupt Req uest Signals

ternal "glue lo gic".

The CS8920A has eleven interrupt request out-

put pins that can be connected directly to any

DS238PP2 15

CS8920A

eleven of the ISA bus Interrupt Request signals.
Only one interrupt output is used at a time. The
interrupt output is selected during initialization
by writing the interrupt number (0 to 10) into
PacketPage Memory base + 0370h; or, the inter­rupt output can be accessed through t he Plug an d
Play resource register 0070h. Unused interrupt
request pins are placed in a high-impedance
state. The selected interrupt request pin goes
high when an enabled interrupt is triggered. The
pin goes low after the Interrupt Status Queue

(ISQ) is read as all 0’s (see Section 5.1 for a
description of the ISQ).

CS8920A Interrupt
Request Pin

IRQ3(Pin 75) IRQ3 0003h
IRQ4 (Pin 76) IRQ4 0004h
IRQ5 (Pin 77) IRQ5 0005h
IRQ6(Pin 78) IRQ6 0006h
IRQ7(Pin 79) IRQ7 0007h
IRQ9(Pin 106) IRQ9 0009h
IRQ10(Pin 34) IRQ10 000Ah
IRQ11(Pin 33) IRQ11 000Bh
IRQ12(Pin 32) IRQ12 000Ch
IRQ14(Pin 30) IRQ14 000Eh
IRQ15 (Pin 31) IRQ15 000Fh

ISA Bus
Interrupt

Packe t Pa ge
base + 0370h*

during initi alization by writi ng the number of the

desired channel (0, 1 or 2) into PacketPage

Memory base + 0374h. Unused DMA pins are

placed in a high-impedance state. The selected

DMA request p in goes high when th e CS8920A

has received frame s to transfer to the hos t mem-

ory via DMA. If the DMABurst bit (register 17,

BusCTL, Bit B) is se t, the pin goes low after the

DMA operation is complete. If the DMABurst

bit is clear, the pin goes low 32 µs after the st art

of a DMA transfer.

The DMA pin pairs are arranged on the

CS8920A to facilitate board layout. Crystal rec-

ommends the configuration in Table 3.2 when

connecting these pins to th e ISA bus.

For a description of DMA mode, see Section

CS8920A DMA
Signal (Pin #)

DRQ5 (16) DRQ5 0000h
DAC K 5 ( 17 ) DAC K 5
DRQ6 (14) DRQ6 0001h
DAC K 6 ( 15 ) DAC K 6
DRQ7 (9) DRQ7 0002h
DAC K 7 ( 10 ) DAC K 7

ISA DMA
Signal

PacketPage
base + 0374h

Table 3.1. Interrupt Assignments

Table 3.1 presents one possible way of connect­ing the interru pt request pins to the ISA bus that
utilizes common ly available interrupts and facili­tates board layo ut.

*When in PnP mode, the in terrupt request ou tput
is accessed throu gh the resource register 0370h.

DMA Signals

The CS8920A interfaces directly to the host
DMA controller to provide DMA transfers of re­ceive frames from CS8920A memory to host
memory. The CS8920A has three pa irs of DMA
pins that can be connected directly to the three
16-bit DMA channels of the ISA bus. Only one
DMA channel is used at a time. It is selected

Tab le 3.2. DMA Assignments

5.5.

3.3

Reset and Initialization

3.3.1 Reset

Nine different conditions cause the CS8920A to

reset its i nternal registers and circuit s.

External Reset, or ISA Reset: There is a chip-

wide reset whenever the RESET pin is high for

at least 40 ns . During a chip-wide reset, al l cir-

cuitry and registers in the CS8920A a re reset.

Power-Up Reset: When power is applied, the

CS8920A mainta ins reset until the voltage at t he

supply pins reaches approximately 2.5 V. The

CS8920A come s out of reset on ce Vcc is greater

16 DS238PP2

CS8920A

than approximately 2.5 V and the crystal oscill a­tor has stabili zed.

Power-Down Reset: If the supply voltage drops
below approximately 2.5 V, there is a chip-wide
reset. The CS8920A comes out of reset once the
power supply returns to a level greater than ap­proximately 2.5 V and the crystal oscillator has
stabilized.

EEreset: There is a chip-wide reset if the
CS8920A detects an EEPROM checksum error.
(see Section 3 .1).

Software Initiated Reset: There is a chip-wide
reset whenever the RESET bit (Register 15,
SelfCTL, Bit 6) is set. The Plug and Play card
select number, Plug and Play Rd Data port,
PnP_disable bit, IO base address register, mem­ory base address register, interrupt register, and
DMA register are preserved. The digital logic is
reset, but the an alog cir cuits are no t.

Magic Packet Frame Genera ted Reset: In power

down mode, with WakeupEn=1, the CS8920A

won’t reset completely unless the reset signal it

detects is followed by 6

MEMR cycles. The
Magic Packet frame generated reset ensures the
CS8920A resets only when it receives a true
power up reset signal.

3.3.2 Allowing Time for Reset Operat ion

After a reset, the CS8920A goes through a self
configuration. This includes calibrating on-chip
analog circuit ry, and reading EEPROM for valid­ity and configuration. Time required for the reset
calibration is typically 10 ms. Software drivers
should not access registers internal to the
CS8920A during this time. When calibration is
done, bit INITD in the Self St atus Register (reg­ister 16) is set indicating that initialization is
complete, and the SIBUSY bit in the same regis­ter is cleared indicating the EEPROM is no
longer being read or programmed.

Hardware (HW) Standby or Suspend: The
CS8920A goes though a chip-wide reset when­ever it enters or exits either HW Standby mode
or HW Suspend mode (see Sectio n 3.8 for more
information about HW Stan dby and Suspen d).

Software (SW) Suspend: Whenever the
CS8920A en ters SW Suspend mode, all registers
and circuits are reset except for th e ISA I/O Base
Address register (located at PacketPage base +
0360h) and the SelfCTL register (Register 15).
Upon exit, there is a chip-wide reset (see Sec tion

3.8 for more informati on about SW Suspend).

PnP Initiated Reset: Writing a one (setting
bit[0]) to the Plu g and Play Config Control reg­ister (address 0x02 ) causes all digital registers to

be reset, including the CS8920A’s Card select
Number and Plug and Play Read Data Port ad­dress. At the e nd of the reset, t he CS8920A will
attempt to read configuration information from
EEPROM. The analog circuits are not reset.

3.3.3 Bus Reset Considerations

The CS8920A reads 3000h from IObase+0Ah
after the reset, until the software writes a non­zero value at IObase+0Ah. The 3000h address
can be used as part of the CS8920A signature
when the system scans for the CS8920A. See
Section 4.1 2, I/O Space Op eration.

After a reset, the ISA bus outputs IRQx and
DRQx are tri-stated, thus avoiding any interrupt
or DMA channel conflicts on the ISA bus at
power-up time.

Initializati on

After each reset (except EEPROM Reset), the
CS8920A checks the sense of the EEDI pin to
see if an external EEPROM is present. If EEDI
is high, an EEPROM is present and the
CS8920A automatically loads the configuration
data stored in the EEPROM into its internal reg­isters (see next section). If EEDI is low, an

DS238PP2 17

CS8920A

EEPROM is not present and the CS8920A
comes out of reset with th e default configuration
shown in Table 3.3.

A low-cost serial EEPROM can be used to store
configuration information that is automatically
loaded into t he CS8920A aft er each reset ( except
EEPROM reset). The u se of an EEPROM is op-

PacketPage
Address

0360h 0000h I/O Base Address*
0370h XXXX XXX X

0374h XXXX XXX X

0026h 0000h DMA Start-of-Frame Offset
0028h X000h DMA Frame Count
002Ah 0000h DMA Byte Count
0348h XXX0 0000h Memory Base Address
0340h XXX0 0000h Boot PROM Base

0343h XXX0 0000h Boot PROM Address Mask
0102h 0003h Register 3 - RxCFG
0104h 0005h Register 5 - RxCTL
0106h 0007h Register 7 - TxCFG
0108h 0009h Register 9 - TxCMD
010Ah 000Bh Register B - BufCFG
010Ch 000Dh Register D - Advint CTL/ST
010Eh Undefined Reserved
0110h Undefined Reserved
0112h 0013h Register 13 - LineCTL
0114h 0015h Register 15 - SelfCTL
0116h 0017h Register 17 - BusCTL
0118h 0019h Register 19 - TestCTL
011Ch 001Dh Register ID - AutoNeg CTL

* I/O base address is unaffected by SW Suspend mode.

Register
Contents

0000 0000

XXXX XX11

Register
Description

Interrupt Number

DMA Channel

Address

Table 3.3. Defa ult Configuration

EEPROM Type Size (16-bi t words)

’C46 (non-sequential) 64
’CS46 (sequential) 64
’C56 (non-sequential) 128
’CS56 (sequential) 128
’C66 (non-sequential) 256
’CS66 (sequential) 256

Table 3.4. Supp orted EEPROM Typ es

tional and is not required for all applications
(e.g. motherboard designs). However, while op­eration of the CS8920A is possible without the
use of an att ached EEPROM, special d esign con­siderations are required. Furthermore, some of
the CS8920A functions, such as Plug and Play
capabilities and wakeup frame recognition are
not possibl e without an atta ched EEPROM. Con-

tact Crystal’s CS8920A technical support for
more information on the use of the CS8920A
without an at tached EEPROM.

The CS8920A operates with any of six standard
EEPROM’s shown in Table 3.4. To work in a
PNP system, the CS8920A requires at least a
128 word EPROM.

3.4

Plug & Play

Plug and Play is a standard mechanism, devel­oped by Intel and Microsoft, that provides an
automatic config uration capability for ISA cards.
System resources such as interrupts, memory ad­dresses, and IO ports are assigned to Plug and
Play compatible devices by the Plug and Play
configuration mecha nism.

The CS8920A fully supports Plug and Play and
allows the complete configuration of the ISA in­terface by the Plug and Play compatible
operating system software or BIOS. Refer to the
Plug and Play ISA Specification for detailed in­formation about the innerworkings of Plug and
Play.

Plug and Play Configuration Process

The Plug and Play configuration process deter­mines the resource requirements of the Plug and
Play devices in a system and assigns non-con­flicting resources to these cards. The
configuration process goes through several
phases:

18 DS238PP2

CS8920A

• A reset signal on the system bus places all

Plug and Play cards into a mode in which
they are all waiting for configuration to be­gin.

• A special key is writte n to all all of the PNP

cards to initi alize them for select ion.

• A special series of reads is performed that

allows a single card to be selected. The se­lected card is given a system identifier, called
the card select number (CSN). The configu­ration software then determines the resource
requirements of the card. Fi nally, the selected
card is placed into a slee p mode. The rem ain­ing cards are individually selected and
assigned a CS N and their resource need s de­termined.

• The configuration software then selects an

individual card using the CSN, assigns non­conflicting resources to the card, and then
enables the card for normal oper ation. This is
repeated for each of the Plug and Play cards
until all of the cards have been configured
and enabled.

Plug and Play Auxi liary Key

The CS8920A wil l respond to a special auxilia ry
key at any time. The auxiliary initiation key is
normally used for testing/debug purposes. Two
bytes of 00 should pro ceed the initiation or aux­iliary key. This auxiliary initiation key is listed
below in hexadecimal:

6A, B5, DA, 6D, B6, 5B, 2D, 16
0B, 05, 02, 01, 80, C0, 60, 30
18, 0C, 06, 83, 41, 20, 90, 48
24, 12, 89, C4, E2, F1, F8, FC

Plug and Play Device IDs

The Plug and Play device ID is a unique identi­fier that is used by the operating system to
associate the Plug and Play card with its device

CS8920A Pin
(Pin #)

EECS
(Pin 141)

EESK
(Pin 142)

EEDO
(Pin 6)

EEDI
(Pin 7)

Table 3.5. EEPROM Interface

CS8920A Func tion EEPROM

Pin

EEPROM Chip
Select

1 MHz EEPROM Seri al
Clock output

EEPROM Data Out
(data to EEPROM)

EEPROM Data In (data
from EEPROM)

Chip Select

Clock

Data In

Data Out

driver. Microsoft administers the assignment of
these device IDs. Contact Microsoft to receive a
unique device ID.

3.5

Configuration with EEPROM

EEPROM Interface

The interface to the EEPROM consists of the
four signals shown in Table 3.5

EEPROM Memory Organization

EEPROM is used to store initial configuration
information for the CS8920 A. The EEPROM is
organized in one or more blo cks of 16-bit words.
The first block in EEPROM, referred to as the
Configuration Block, is used to configure the
CS8920A after reset. An example of a typical
Configuration Block is shown in Table 3.6 . Ad­ditional user data may also be stored in the
EEPROM if space is available. The additional
data are stored as 16-bit words and can occupy
any EEPROM address space beginning immedi­ately after the end of the Reset Configuration
Block up to address 7Fh, depending on
EEPROM size. This additional data can only be
accessed through software control (refer to Sec­tion 3.6 for more information on accessing the
EEPROM). Address space 80h to AFh is re­served

DS238PP2 19

CS8920A

Reset Configuration B lock

The first block in EEPROM, referred to as the
Reset Configuration Block, is used to automat­ically program the CS8920A with an initial
configuration after a reset. It is a block of con­tiguous 16-bit words starting at EEPROM
address 00h. The Reset Configuration Block ca n
be divided into three logical sections: a header,
one or more grou ps of configuration data words,
and a checksum value. All of the words in the
Reset Configuration Block are read sequentially
by the CS8920A after each reset, starting with
the header and ending with the checksum. Each
group of configuration da ta is used to program a
PacketPage register (or set of PacketPage regis­ters in some cases) with an initial non-default
value.

Reset Configuration Block Header: The header
(first word of the block located at EEPROM ad­dress 00h) specifies the type of EEPROM used,

whether or not a Reset Configuration block is

present, if t he CS8920A’s Plug and Play support
is enabled or disabled, and how many bytes of
data are stor ed in the Re set Configurati on Block.

Determining the EEPROM Type: The LSB of
the high byte of the header i ndicates the type of
EEPROM attached: sequential or no n-sequential.
An LSB of 0 (XXXX-XXX0) indicates a se­quential EEPROM. An LSB of 1 (XXXX­XXX1) indicates a non-sequential EEPROM.
The CS8920A works equally well with either
type of EEPROM. The CS8920A will automat­ically generate sequential addresses while
reading the Reset Configuration Block if a non­sequential E EPROM is used.

Checking EEP ROM for presence of Reset Con­figuration Block: The readout of either a binary

101X-XXX0 or 101X-XXX1 (X = do not care)
from the high byte of the header indicates the
presence of configuration data. Any other read-

Word Address Value Description

FIRST WORD in DATA BLOCK
00h B112h Configuration Block Header.

The high byte, B1h, indicates a ’C56 EEPROM (non-sequential) is attached
and Plug and Play is disabled. The Link Byte, 12h, indica tes the nu mbe r of

bytes of configuration data in this block.
FIRST GROUP of WORDS
01h 2158h Group Header for first group of words.

Three words to be loaded, beginning at 0158h in PacketPage memory.
02h 0100h Individual address, bits[39-32], bits[47-40]
03h 0302h Individual address, bits[23-16], bits[31-24]
04h 0504h Individual address, bits[7-0], bits[15-8]
SECOND GROUP of WORDS
05h 0360h Group Header for second group of words.

One word to be loaded at 360h in PacketPage memory.
06h 0003h IO Base address = 300h
THIRD GROUP of WORDS
07h 0330h Group Header for third group of words.

One word to be loaded at 330h in PacketPage memory.
08h 0001 Set adapter’s activate bit (make active on reset w/o PnP).
CHECKSUM Value
09h 1B00h The high byte, 1Bh, is the checksum value. The checksum includes word

addresses 00h through 08h. The hexadecimal sum of the bytes is E5h,

resulting in a 2’s complement of 1Bh. The low byte, 00h, provides a pad to

the word boundary.

Tabl e 3.6. EEPROM Configuration Block Example

20 DS238PP2

CS8920A

out value terminates initialization from the
EEPROM. If an EEPROM is attached but not
used for configuration, Crystal recommends that
the high byte of the first word be programmed
with 00h in order to ensure that the CS8920A
will not attempt to read configuration data from
the EEPROM.

Setting Plug And Play Support Enabled/dis­abled: Setting bit four of the high byte of the

header disables the CS8920A’s Plug and Play
support. Clearing this bit leaves Plug and Play
support enabled (default). For example, a value
of 1011-XXXX (X = do not care) for the high
byte disables Plug and Play support while a
value of 1010-XXXX leaves Plug and Play en­abled.

Determining Number of Bytes in the Reset
Configuration Block: The low byte of th e Reset

Configuration Blo ck header is known as the link
byte. The value of the Link Byte represents the
number of bytes o f configuration data in the Re­set Configuration Block. The two bytes used for
the header are excluded when calculating the
Link Byte value.

For example, a Reset Configuration Block
header of A112h indicates a non-sequential
EEPROM programmed with eighteen (12h)
bytes of configuration data. The CS8920A’s
Plug and Play support is enabled. The Reset
Configuration Block occupies twenty bytes (10
words) of EEPROM space (2 bytes for the
header and 18 b ytes of configuratio n data).

Groups of Configuratio n Data

remaining words in the group are stored in suc­cessive PacketPage registers.

Group Header: Bits F through C of the Group
Header specify the number of words in each
group that are to be transferred to PacketPage
registers (see Figure 3.1). This value is two less
than the total number of wo rds in the group, in­cluding t he Group Head er. For example, if bits F
through C c ontain 0001, there are three words in
the group (a Group Header and two words of
configuration dat a).

First Word of a Group of Words

103

25

FE

Number of Words

in Group

Figure 3.1. Group Header

C

00

9

B

AD

8

10-bit PacketPage Address

476

Bits 9 through 0 of the Group Header specify a
10-bit PacketPage Address. This address defines
the PacketPage register that will be loaded with
the first word of configuration data from the
group. Bits B and A of the Group Header are
forced to 0, restricting the destination address
range to the first 10 24 bytes of PacketPage me m­ory.

Configuration data are arranged as groups of
words. Each group contains one or more words

Figure 3.1 shows the format of the Group

header.
of data that are to be loaded into PacketPage reg­isters. The first word of each group is referred to

Reset Configuratio n Block Check sum

as the Group Header. The Group Header indi­cates the number of words in the group and the
address of the PacketPage register into which th e
first data word in the group is to be lo aded. Any

DS238PP2 21

A checksum is stored in the high byte position

of the word immediately foll owing the last group

of data in the Reset Configuration Block. (The

CS8920A

EEPROM address of the ch ecksum value can be
determined by dividing the value stored in the
Link Byte by two). The checksum value is the

2’s complement of the 8-bit sum (any carry out
of eighth bit is ignored) of all the bytes in the
Reset Configuration B lock, excluding the check­sum byte. This sum includes the Reset
Configuration Block header at address 00h.
Since the c hecksum value is calculated as the 2’s
complement of the sum of all the preceding
bytes in the in the Reset Configuration Block, a
total of 0 sho uld result when the checksum value
is added to the sum of the previous bytes.

EEPROM Examp le

Tabl e 3.6 shows an example of a Reset Configu­ration Block stored in a ’C56 (non-sequential)
EEPROM. The B112h value in the header dis­ables Plug and Play support and specifies
eighteen bytes of configuration data follow.
Note that litt le-endian word ord ering is used, i.e.,
the least significan t word of a multi-word datum
is located at th e lowest address.

EEPROM Readout

If the EEDI pin is asserted high at the end of

reset, the CS8920A reads the first word of

EEPROM data by:

1. Asserting EECS

2. Clocking out a Read-Register-00h command

on EEDO (E ESK provides a 1 MHz se rial clock

signal)

3. Clocking th e data in on EEDI.

If the EEDI pin is low at the end of the reset

signal, the CS8920A does not perform an

EEPROM readout (uses its default configura-

tion).

Determining EEPROM Size: The CS8920A de-

termines the size of the EEPROM by checking

the sense of EEDI on the tenth rising edge of

EESK. If EEDI is low, the EEPROM is a ’C46

or ’CS46. If EEDI is high, the EEPROM is a

’C56, ’CS56, ’C66 , or ’CS66.

Loading Configuration Data: The CS8920A

reads in the first word from the EEPROM to de-

termine if c onfiguration data are contai ned in the

AD7 - AD0 used with ’C56,

’CS56, ’C66 and ’CS66

F

EXDXCXB

X

Bit Name Description
[F:B] Reserved
[A] ELSEL External Logic Sel ect: When clear, the EECS pin is used to select the EEPROM. When set,

the ELCS pin is used to select the external LA decode circuit.
[9:8] OB1, OB0 Opcode: Indicates what command is being executed (see next section).
[7:0] A D7 to AD0 EE PROM Address: Address of EEPROM word being accessed.

A

9

8

X ELSEL OB1 OB0

AD7 AD6

Figure 3.2. EEPROM Command Register Format

22 DS238PP2

5476

AD5 AD 4

AD5 - AD 0 used with

’C 46 and ’ C S4 6

1

032

AD1 AD 0AD3 AD 2

CS8920A

EEPROM. If configuration data are not stored in
the EEPROM, the CS8920A terminates initiali­zation from EEPROM and operates using its
default configuration (See Table 3.3). Note: the
default configuration leaves the CS8920A in a
PnP inactive state; it can then only be accessed
through the PnP configuration and data ports. If
configuration data are stored in EEPROM, the
CS8920A automatically loads all configuration
data stored i n the Reset Configurati on Block into
its inter nal PacketPage regist ers.

EEPROM Readout Completion

Once all the con figuration dat a are transferred to
the appropriate PacketPage registers, the
CS8920A adds the sum of the data by tes it read

to the 2’s complement checksum at the end of
the configuration data to verify the Reset Con­figuration Block’s data are valid. If the resulting
total is 0, the readout is c onsidered valid. Other­wise, the CS8920A initiates a partial reset to
restore the de fault configuration .

If the readout is valid, the EEPROMOK bit
(Register 16, SelfST, bit A) is set. EEPROMOK
is cleared if a checksum error is detected . In this
case, the CS8920A performs a partial reset and
is restored to its default. Once initialization is

complete (configuration loaded from EEPROM
or reset to d efault configuration) the INITD bit is
set (Register 16, SelfST, bit 7).

3.6

Programming the EEPROM

After initialization, the host can access the
EEPROM through the CS8920A by writing one
of seven commands to the EEPROM Command
register (PacketPage base + 0040h). Figure 3.2
shows the format of the EEPROM Command
register.

EEPROM Commands

The seven commands used to access the
EEPROM are: Read, Write, Erase, Erase/Write
Enable, Erase/Write Disable, Erase-All, and
Write-All. They a re descri bed i n Table 3.7.

EEPROM Command Exe cution

During the execution of a command, the two Op­code bits, followed by six bits of address (for a
’C46 or ’CS46) or eighth bits of address (for a
’C56, ’CS56, ’C66 or ’CS66), are shifted out of
the CS8920A, into the EEPROM. If the com­mand is a Write, the data in the EEPROM Data
register (PacketPage base + 0042h) follows. If

Command Opcode

(bits 9, 8)

Read Register 1,0 word address yes all
Write Register 0,1 word address yes all 10 ms
Erase Register 1,1 word address no all 10 ms
Erase/Write Enable 0,0 XX11-XXXX no ’CS46, ’C46

Erase/Write Disable 0,0

0,0

Erase-All Registers 0,0

0,0

Write-All Registers 0,0

0,0

Table 3.7. EEPROM Comman ds

DS238PP2 23

EEPROM Address
(bits 7 to 0)

11XX-XXXX no ’CS56, ’C56, ’CS66, ’C66
XX00-XXXX no ’CS46, ’C46
00XX-XXXX no ’CS56, ’C56, ’CS66, ’C66
XX10-XXXX no ’CS46, ’C46 10 ms
10XX-XXXX no ’CS56, ’C56, ’CS66, ’C66 10 ms
XX01-XXXX yes ’CS46, ’C46 10 ms
01XX-XXXX yes ’CS56, ’C56, ’CS66, ’C66 10 ms

Data EEPROM T yp e Executi on Time

25 µs

9 µs
9 µs
9 µs
9 µs

CS8920A

the command is a Read, the d ata in the specified
EEPROM location is written into the EEPROM
Data register. If the command is an Erase or
Erase-All, no data is transferred to or from the
EEPROM Data register. Before issuing any com­mand, the host must wait for the SIBUSY bit
(Register 16, SelfST, bit 8) to clear. After each
command has been issued, the host must wait
again for SI-BUSY to clear.

Enabling Ac cess to th e EEPROM

The Erase/Write Enable command provides pro­tection from accidental writes to the EEPROM.
The host mus t write an Erase/W rite Enable com­mand before it attempts to write to or erase any
EEPROM memory location. Once the host has
finished altering the co ntents of the EEPROM, it
must write an Erase/Write Disable command to
prevent unwanted modification of the E EPROM.

Writing and Erasing t he EEPROM

To write data to the EEPROM, the host must
execute the following s eries of com mands:

1. Iss ue an Eras e/Write Enab le command.

CS8920A

CSOUT
(Pin 17)

SA(0:14)

20
22

27C256

CE

OE

19

74LS245

OE
DIR

B1

.
.
.

B8

A1

.
.
.

A8

SD(0:7)

ISA

BUS

Figure 3.3. Boot PROM Connection Diagram

network server. This is typically done for a disk­less workstation.

Accessing the Boot PR OM

The CS8920A provides address decoding cir­cuitry to generate a chip select for a Boot
PROM. When the address on the ISA bus match
the address loaded into the Boot PROM base ad­dress register and qualified by Boot PROM
address mask register. The CS8920A generates a
chipselect signal for the Boot PROM.

2. Loa d the data i nto the EEPROM Data register.

Configuring the CS89 20A for Boot PROM
Operation

3. Iss ue a Writ e comma nd.
Figure 3.3 show how the CS8920A should be

4. Iss ue an Erase/Wr ite Disable c ommand.

connected to the Boot PROM and ’245 driver.
To co nfigure the CS8920A’s internal registers for

During the Eras e command, the CS8 920A writes
FFh to the spec ified EEPROM location. During
the Erase-All command, the CS8920A writes
FFh to all locat ions.

Boot PROM operation, the Boot PROM Base
Address must be loaded into the Boot PROM
Base Address register (PacketPage bas e + 0340h)
and the Boot PROM Address Mask must be
loaded into th e BootPROM Address Mask regis­ter (PacketPage base + 0343h). T he Boot PROM
Base Address provides the starting location in

3.7

Boot PROM Operation

host memory where the Boot PROM is mapped.
The Boot PROM Address Mask indicates the

The CS8920A supports an optio nal Boot PROM
used to store code for remote booting from a

size of the attached Boot PROM and is limited
to 4-Kbyte increments. The lower 12 bits of the
Address Mask are ign ored and shoul d be 000h.

24 DS238PP2

CS8920A

As an example, to configur e the CS8920A to use
a 16-Kbyte (128-Kbit) PROM mapped into host
memory at a starting address of D0000h, write
0D00h to the BootPROM Base Address register
and write 0FC0h into the BootPROM Address
Mask register. (The mask value for a 16-Kbyte
PROM is 0FC00h. See Section 4.8 for more in­formation on determin g the BootPROM Address
and Mask register values.)

3.8

Low-Power Modes

For power-sensitive applications, the CS8920A
supports three low-power modes: Hardware
Standby, Hardware Suspend, and Software Sus­pend. All three low-power modes are controlled
through the SelfCT L register (Register 15).

An internal reset occurs when the CS8920A
comes out of any s uspend or standby mode. Af­ter a reset (internal or external), the CS8920A
goes though a self configuration. This includes
calibrating on-chip analog circuitry, and reading
EEPROM for validity and configuration. When
the calibration is done, bit InitD in Register 16
(Self Stat us regist er) is s et indicat ing th at init iali­zation is complete, and the SIBusy bit in the

same register is cleared (indicating that the
EEPROM is no longer being read or pro­grammed. Time required fo r the reset calibration
is typically 10 ms. Software drivers should not
access registers internal to CS8920A during this
time.

Hardware Standby

Hardware (HW) Standby is designed for use in

systems, such as portable PC’s, that may be tem­porarily disconn ected from the 10BASE-T cable.
It allows the sys tem to conserve power while the
LAN is not in use, and then automatically re­store Ethernet operation once the cable is
reconnected.

In HW Standby mod e, all analog and digita l cir­cuitry in the CS8920A is turned off, except for
the 10BASE-T receiver which remains active to
listen for l ink activity. If link activity is detected,
the

LANLED pin is driven low, providing an in­dication to the host that the network connection
is active. The host can then activate the
CS8920A by de-asserting the

SLEEP pin. Dur-

ing this mode , all ISA bus a ccesses are ignored.

CS8920A Configuration CS8920A Operation

SLEEP
(Pin 116)

Low Set Set Clear Not Present HW Standby mode:

Low Set Set Clear Receiver

Low Clear Set Clear N/A HW Suspend mode
Low to High N/A Set Clear N/A CS8920A resets and goes

High N/A N/A Clear N/A Not in any sleep mode
Low N/A Clear Set N/A SW Suspend mode
Low N/A Clear Clear N/A Not in any sleep mode

NOTE: Both HW Standby and HW Suspend take precedence over SW Suspend.

Table 3 .8. Low-Power Mode Operation

DS238PP2 25

HWstandbyE
(SelfCTL, Bit
A)

HWSleepE
(SelfC TL, B it 9)

SWSuspend
(SelfCTL, Bit 8)

Link Pulses

Activity

10BASE-T receiver listens for
link activity

HW Standby mode:
LANLED low

through Initialization

CS8920A

To enter HW Standby mode, the SLEEP pin
must be low and the HWSleepE bit (R egister 15,
SelfCTL, Bit 9) and the HWstandbyE bit (Regis­ter 15, SelfCTL, Bit A) must be set. When the
CS8920A enters HW Standby, all registers and
circuits are reset except for the SelfCTL register.
Upon exit from HW Standby, the CS8920A per­forms a complete reset, and then goes through
normal initiali zation.

Hardware Suspend

During Hardware Suspend mode, the CS8920A
uses the least amou nt of current of the three low­power modes. All internal circuits are turned off

and the CS892 0A’s core is electronically isol ated
from the rest of the system. Accesses from the
ISA bus and Ethernet activity are bo th ignored .

HW Suspend mode is entered by driving the
SLEEP pin low and setting the HWSleepE bit
(Register 15, SelfCTL, bit 9) while the
HWstandbyE bit (Registe r 15, SelfCTL, bit A) is
clear. To exit from this mode, the

SLEEP pin
must be driven high. Upon exit, the CS8920A
performs a comp lete reset, an d then goes through
a normal init ializatio n procedure.

Software Suspend

Software (SW) Suspend mode can be used to
conserve power in certain applications, such as
adapter cards that do not have power manage­ment circuitry available. During software
suspend mode there is a partial reset. All regis­ters and c ircuits are re set except for the Plug an d
Play state, CSN, read data port, ISA I/O Base
Address Regist er, and the SelfCTL r egister.

To enter SW Suspend mode, the host must set
the SWSuspend bit (Register 15, SelfCTL, bi t 8).
To exit SW Suspend, the host must write to the
CS8920A’s assigned I/O space (the write is only
used to wake the CS8920A, the write itself is
ignored). Upon exit, the CS8920A performs a

complete reset, then goes through a normal in­itialization p rocedure.

Any hardware reset takes the chip out of any
sleep mode.

Table 3.8 summarizes the operation of the three
low-power modes.

HC0E
(Bit C)

0 N/A Pin configured as LINKLED: Output

1 0 Pin co nfigur ed as HC0:

1 1 Pin co nfigur ed as HC0:

Table 3.9. LINKLED/HC0 Pin Operation

3.9

HCB0
(Bit E)

Pin Function

is low when valid 10BASE-T link
pulses are detected. Output is high if
valid link pulses are not detected.

Output is high

Output is low

LED Outputs

The CS8920A provid es four output pins th at can
be used to cont rol LEDs or external lo gic.

LANLED:

LANLED goes low whenever the
CS8920A tran smits or receives a frame, or when
it detects a collision.

LANLED remains low until
there has been no activity for 6 ms (i.e. each
transmission, reception, or collision produces a
pulse lasting a minimum of 6 ms).

HC1E
(Bit D)

0 N/A Pin configured as BSTATUS: Output

1 0 Pin co nfigur ed as HC1:

1 1 Pin co nfigur ed as HC1:

Table 3.10. BSTATUS/HC1 Pin O peration

HCB1
(Bit F)

Pin Function

is low when a receive frame begins
transfer acro ss th e ISA bus. Output is
high otherwise.

Output is high

Output is low

26 DS238PP2

CS8920A

LINKLED or HC0: LINKLED or HC0 can be
controlled by either the CS8920A or the host.
When controlle d by the CS8920A,

LINKLED is
low whenever the CS8920A receives valid
10BASE-T link pulses. To configure this p in for
CS8920A control, the HC0E bit (Register 15,
SelfCTL, Bit C) must be clear. When controlled
by the host,

LINKLED is low whenever the
HCB0 bit (Register 15, SelfCTL, Bit E) is set.
To configure it for host control, the HC0E bit
must be set. Table 3.9 summari zes this ope ration.

BSTATUS or HC1:

BSTATUS or HC1 can be
controlled by either the CS8920A or the host.
When controlled by the CS8920A,

BSTATUS is
low whenever the host reads the RxEvent regis­ter (PacketPage base + 0124h), signaling the
transfer of a receive frame across the ISA bus.
To configure this pin for CS8920A control, the
HC1E bit (Register 15, SelfCTL, Bit D) must be
clear. When controlle d by the host,

BSTATUS is
low whenever the HCB1 bit (Register 15,
SelfCTL, Bit F) is set. To configure it for host
control, HC1E must be set. Table 3.10 summa­rizes this operatio n.

+5V

LOCALLED:

LOCALLED goes low whenever
local LAN activity is occurring. Local LAN ac­tivity is defined as either the the receipt of
Ethernet frames that pass the address filter of
the CS8920A, or the transmission of fra mes onto
the Ethernet. This LED is intended to be used
on the front panel of a PC in a manner analo­gous to a Hard Drive Activity LED. See Section

5.3 for discussi on of the receive address filter.

LED Connection

Each LED output is capab le of sinking 10 mA to
drive an LED directly through a series resistor.
The outp ut voltage of e ach pin is les s than 0.4 V
when the pin is low. Figure 3.4 shows a typical
LED circuit.

3.10

Media Access Control

Overview

The CS8920A’s Ethernet Media Access Control
(MAC) engine is fully compliant with the IEEE

802.3 Ethernet stand ard (ISO/IEC 8802-3, 1993).
It handles all asp ects of Et hernet frame transmis­sion and recept ion, includi ng: collisio n detection,
preamble generation and detection, and CRC
generation and test. Programmable MAC fea­tures include automatic retransmission on
collision, a nd padding of tra nsmitted frames.

Figure 3.5 shows how the MAC engine inter­faces to other CS8920A functions. On the host
side, it interfaces to the CS8920A’s internal

LOCALLED

LANLED

LINKLED

Figure 3.4. LED Connection Diagram

DS238PP2 27

CS8920A

Internal Bus

Figure 3.5. MAC Interface

LED

Logic

802.3
MAC

Engine

Enco der/
Decoder

&

PLL

10BASE-T

& AUI

CS8920A

data/address/control bus. On the network side, it
interfaces t o the internal Manchester encod er/de­coder (ENDEC). The primary functions of the
MAC are: frame encapsulation and decapsula­tion; error detection and handling; and, media
access manag ement.

Frame Encapsulation and Decapsulation

The CS8920A’s MAC engine automatically as­sembles transmit packets and disassembles
receive packets. It also determines if transmit
and receive frames are of legal minimum size.

Transmission: Once the proper number of bytes
have been transferred to t he CS8920A’s memory
(either 5, 381, 1021 bytes, or full frame), and
providing that access to the network is permitt ed,
the MAC automatically transmi ts the 7-byte pre­amble (1010101b...), followed by the
Start-of-Frame Delimiter (SFD, 10101011b), and
then the serialized frame data. It then transmits
the Frame Check Seq uence (FCS). The data after
the SFD and before the FCS (Destination Ad­dress, So urce Address, Len gth, and data field) is
supplied by the host. FCS generation by the
CS8920A may be disabled by setting the In­hibitCRC bit (Regis ter 9, TxCMD, bit C).

Figure 3.6 shows the Ethernet frame format.

Reception: The MAC receives the incoming
packet as a serial stream of NRZ data from the
Manchester enc oder/decoder. It begins by che ck­ing for the SFD. Once the SFD is detected, the
MAC assumes all subseque nt bits ar e frame data.
It reads the DA and compares it to the criteria
programmed into the address filter (see Section

5.3 for a description of Address Filtering ). If the
DA passes the address filter, the frame is lo aded
into the CS8920A’s memory. If the BufferCRC
bit (Register 3, RxCFG, bit B) is set, the re­ceived FCS is also loaded into memory. Once
the entire packet has been received, the MAC
validates the FCS. If an error is detected, the
CRCerror bit (Registe r 4, RxEvent, Bit C) i s set.

Enforcing Minimum Frame Size: The MAC
provides minimum frame size enforcement of
both transmit and receive packets. When the
TxPadDis bit (Register 9, TxCMD, Bit D) is
clear, transmit frames will be padded with addi­tional bits to ensure that the receiving station
receives a legal frame (64 bytes, including
CRC). When TxPadDis is set, the CS892 0A will
not add pad bits and will transmit frames less
that 64 bytes. If a frame is received that is less
than 64 bytes (including CRC), the Runt bit
(Register 4, RxEvent, Bit D) will be set indicat­ing the arrival of an ill egal frame.

1 byteup to 7 bytes 6 bytes 6 bytes

alternating 1s / 0s

preamble

Direction of Transmission

SFD = Start of Frame Delimiter
DA = Destination Address
SA = Source Address
LLC = Logical Link Control
FCS = Frame Check Sequence (also
called Cyclic Redundancy Check, or CRC)

SFD DA SA

Packet

The optional field, which is two bytes long, is
either a TYPE field for Etherne t applica tions or
a LENGTH field for IEEE 802.3 applications.

The Pad field will be used only to get the frame
to the minimum size. When the CS8920 adds pad
bytes, the pad is the last byte of the LLC data
field rep eat e d M ti mes .

Frame

2 bytes N bytes M bytes

Optional Field

frame length
min 64 bytes
max 1518 bytes

LLC data Pad

4 bytes

FCS

Figure 3.6. Ethernet Frame Format

28 DS238PP2

CS8920A

Transmit Error Detectio n and Handling

The MAC engine monitors Ethernet activity and
reports and recovers from a number of error con­ditions. For transmission, the MAC reports the
following errors in the TxEvent register (Register

8) and BufEvent register (Register C):

Loss of Carrier: Whenever the CS8920A is
transmitting on the AUI port, it expects to see its
own transmission "loope d back" to its rece iver. If
it is unable to monitor its transmission after the
end of the pr eamble, the MAC reports a loss-of­carrier error by setting the Loss-of-CRS bit
(Register 8, TxEvent, Bit 6). If the Loss-of­CRSiE bit (Register 7, T xCFG, Bit 6) is set, the
host will be inte rrupted.

SQE Error: After the end of transmission on the
AUI port, the MAC expects to see a collision
within 64 bit times. If no collision is detected,
the SQEerror bit (Register 8, TxEvent, Bit 7) is
set. If the SQEerroriE bit is set (Register 7,
TxCFG, Bit 7), the host is interrupted. An SQE
error may indicate a fault o n the AUI cable or a
faulty transc eiver (it is assumed th at the attached
transceiver supports this function).

Out-of-Window (Late) Collision: If a coll ision is
detected after the first 512 bits have been trans­mitted, the MAC reports a late collision by
setting the Out-of-window bit (Register 8,
TxEvent, Bit 9). The MAC then forces a bad
CRC and termin ates the transmiss ion. If the Out­of-windowiE bit (Register 7, TxCFG, Bit 9) is
set, the host is interrupted. A late collision may
indicate an illegal n etwork configuration .

Jabber Error: If a transmission continue s longer
than about 26 ms, the MAC disables the trans­mitter and sets the Jabber bit (Register 8,
TxEvent, Bit A). The output of the transmitter
returns to idle and remains there until the host
issues a new Transmit Command. If the JabberiE
bit (Register 7, Tx CFG, Bit A) is set, the host is
interrupted. A Jabber condition indicates that

there may be something wrong with the
CS8920A transmit function. To prevent possible
network faults, t he host should clea r the transmit
buffer. Possible op tions includ e:

Reset the chip with either software or hardware
reset (see Se ction 3.3 ).

Issue a Force Transmit Command by setting the
Force bit (Register 9, Tx CMD, bit 8).

Issue a Transmit Command with the TxLength
field set to zero.

Transmit Collision: The MAC counts the num­ber of times an individual packet must be
re-transmitted due to network collisi ons. The col­lision count is stored in bits B through E of the
TxEvent register (Register 8). If the packet col­lides 16 times, transmission of that packet is
terminated and the 16coll bit (Register 8,
TxEvent, Bit F) is set. If the 16co lliE bit (Regis­ter 7, TxCFG, Bit F) is set, the host will be
interrupted on the 16th collision. A running
count of transmit collisions is recorded in the
TxCOL register.

Transmit Underrun: If the CS8920A starts
transmission o f a packet but runs out of data be­fore reaching the end of frame, the TxUnderrun
bit (Register C, BufEvent, Bit 9) is set. The
MAC then forces a bad CRC and term inates the
transmission. If the TxUnderruniE bit (Register
B, BufCFG, Bit 9) i s set, the hos t is interrupte d.

Receive Error Detec tion and Handling

The following receive errors are reported in the
RxEvent register (Register 4):

CRC Error: If a frame is received with a bad
CRC, the CRC error bit (Register 4, Rx Event, Bit
C) is set. If the CRCerrorA bit (Register 5,
RxCTL, Bit C) is set, the frame will be buffered
by the CS8920A. If the CRCerroriE bit (Register
3, RxCFG. Bit C) i s set, the hos t is interrupte d.

DS238PP2 29

CS8920A

Runt Frame: If a frame is received that is
shorter than 64 bytes, the Runt bit (Register 4,
RxEvent, Bit D) is set. If the Runt A bit (Register
5, RxCTL, Bit D) is set, the frame will still be
buffered by CS8920A. If the RuntiE bit (Regis­ter 3, RxCFG. Bit D) is set, the host is
interrupted.

Extra Data: If a fr ame is received that is longer
than 1518 bytes, the Extradata bit (Register 4,
RxEvent, Bit E) is set. If the ExtradataA bit
(Register 5, RxCTL, Bit E) is set, the first 1518
bytes of the frame will still be buffered by
CS8920A. If the ExtradataiE bit (Register 3,
RxCFG. Bit E) is set, the host is interrupted.

Dribble Bits and Alignment Error: Under nor­mal operating conditions, the MAC may detect
up to 7 add itional bits a fter the last ful l byte of a
receive packet. These bits, known as dribble bits,
are ignored. If dribb le bits are de tected, t he Drib­blebit bit (Register 4, RxEvent, Bit 7) is set. If
both the Dribb lebit bit and CRCerror bit (Regis­ter 4, RxEvent, Bit C) are set at the same time,
an alignment er ror has occur red.

Media Access Managem ent

Collision Avoidance: The MAC continually

monitors network traffic by checking for the
presence of carrier activity (carrier activity is in­dicated by the assertion of the internal Carrier
Sense signal generated by the ENDEC). If car­rier activity is detected, the network is assumed
busy and the MAC must wait until the current
packet is finished before attempting transmis­sion. The CS8920A supports two schemes for
determining when to initiate transmission: Two­Part Deferral, and Simple Deferral. Selection of
the deferral scheme is determined by the 2-part-

Start Monitoring
Network Activity

Yes

Network

Active?

No

Start IPG

Timer

Yes

IPG

Timer =

s?

6.4

µ

The Ethernet networ k topology is a single s hared
medium with several attached stations. The Eth­ernet protocol is designed to allow each station
equal access to the network at any given time.

Wait

3.2

µ

s

No

Network

Active?

No

Any node can attempt to gain access to the net­work by first completing a deferral process

Yes

(described below) after the last network activity,
and then transmitting a packet that will be re­ceived by all other stations. If two nodes
transmit simultaneously, a collision occurs and
the colliding packets are corrupted. Two primary

Tx

Frame

and

Ready

in Backoff?

Not

No

No

Network

Active?

Yes

tasks of the MAC are to avoid network colli­sions, and then recover from them when they
occur. In addition, when the CS8920A is using
the AUI, the MAC must support the SQE Test
function described in section 7.2.4.6 of the Eth-

Figure 3 .7. Two-Part Deferral

Yes

Transmit

Frame

ernet standard.

30 DS238PP2