Cirrus Logic CS8904-CM5, CS8904-CM3 Datasheet
FEATURES
■ Single-Chip Quad IEEE 802.3-compliant Ethernet
Interface
■ 3 V and 5 V Operation
■ Full and Half Duplex Operation
■ Auto-Negotiation with Manual Override Capability
■ Four 10BASE-T Ports with Integrated Active Ana-
log Filters
■ Automatic Polarity Detection and Correction
■ Integrated Manchester Encoder/Decoders
(ENDEC)
■ Link Status LED Driver for Each Port
■ Per Port Control - Manual Duplex select (Half or
Full), Auto-Negotiation select, Loopback select
■ Per Port Status - Collision dete ct, Ca rr ie r det ec t,
Jabber indication, Link status, Duplex status,
Auto-Negotiation status
ORDERING INFORMATION
CS8904-CM5 0 to 70 °C 100-pin MQFP, 5.0 V
CS8904-CM3 0 to 70 °C 100-pin MQFP, 3.3 V
CDK8904-5 Developer’s Kit, 5.0 V
CS8904
Advanced Product Databook
Crystal LAN™ Quad
Ethernet Transceiver
DESCRIPTION
The CS8904 combines four 10BASE-T Ethernet ENDECs and transceivers into a single low-cost device.
Complete on-chip 10BASE-T Transceivers and filters
eliminate external com ponents, saving valuable boa rd
space and reducing cost. The CS8904 offers maximum
design flexibility by providing individual control and status lines for each of the four interface ports.
The CS8904 supports full-duplex operation, allowing simultaneous transmission and reception on all ports.
Auto-negotiation allows the automatic selection of either half or full duplex operation on a per-port basis.
The CS8904 is ideally suited for cost-sensitive Ethernet
switch designs. With the CS8904, engineers can design
a four-port Ethernet Transceiver circuit that occupies
less than 1.0 squa re inch (6.5 sq. cm) of spac e, excl usive of transformers and RJ-45 connectors.
STATUS (5)
TxDATA
RxDATA
RxCLK
CONTROL(4)
STATUS (5)
TxDATA
RxDATA
RxCLK
CONTROL(4)
STATUS (5)
TxDATA
RxDATA
RxCLK
CONTROL(4)
STATUS (5)
TxDATA
RxDATA
RxCLK
CONTROL(4)
TxCLK
CS8904 Quad Ethernet Transceiver
Encoder/Decoder & PLL
Encoder/Decoder & PLL
Encoder/Decoder & PLL
Encoder/Decoder & PLL
VDD(11) GND(13)
MODE(3)
10BASE-T RX Filters & Receiver
10BASE-T TX Filters &Transmitter
10BASE-T RX Filters & Receiver
10BASE-T TX Filters &Transmitter
10BASE-T RX Filters & Receiver
10BASE-T TX Filters &Transmitter
10BASE-T RX Filters & Receiver
10BASE-T TX Filters &Transmitter
RESET
RES
Clock
20 MHz XTAL
LINK LED
RJ-45 10BASE-T
LINK LED
RJ-45 10BASE-T
LINK LED
RJ-45 10BASE-T
LINK LED
RJ-45 10BASE-T
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
FEB ‘98 DS191PP2
Copyright Cirrus Logic, Inc. 1998
(All Rights Reserved)
Crystal LAN™ Quad Ethernet Transceiver
TABLE OF CONTENTS
1.0 INTRODUCTION.....................................................................................................3
1.1 General Description .........................................................................................................3
1.2 System Applications ........................................................................................................ 4
1.3 Key Features and Benefits ............................................................................................... 4
1.3.1 Low Cost, Low Noise, More Features.................................................................... 4
2.0 PIN DESCRIPTION.................................................................................................7
2.1 Controller Interface.......................................................................................................... 8
2.2 10BASE-T Interface ........................................................................................................ 9
2.3 LED Pins.......................................................................................................................... 9
2.4 General Pins..................................................................................................................... 9
3.0 THEORY OF OPERATION .................................................................................12
3.1 Overview........................................................................................................................ 12
3.2 Encoder/Decoder (ENDEC)........................................................................................... 12
3.2.1 Encoder ................................................................................................................ 13
3.2.2 Carrier Detection................................................................................................... 13
3.2.3 Clock and Data Recovery ..................................................................................... 13
3.3 10BASE-T Transceiver.................................................................................................. 13
3.3.1 10BASE-T Filters ................................................................................................. 14
3.3.2 Transmitter............................................................................................................ 14
3.3.3 Receiver ................................................................................................................ 14
3.3.4 Collision Detection ............................................................................................... 15
4.0 FUNCTIONAL DESCRIPTION...........................................................................16
4.1 Reset and Calibration..................................................................................................... 16
4.1.1 Reset Operation..................................................................................................... 16
4.1.2 Allowing Time for Reset....................................................................................... 16
4.2 Mode Control................................................................................................................. 16
4.3 Controller Interface........................................................................................................16
4.3.1 Transmit and Receive Interface ............................................................................ 16
4.3.2 Control and Status Information............................................................................. 17
4.4 External Clock Oscillator............................................................................................... 19
5.0 SPECIFICATIONS.................................................................................................20
ABSOLUTE MAXIMUM RATINGS................................................................................. 20
RECOMMENDED OPERATING CONDITIONS .............................................................20
DC CHARACTERISTICS................................................................................................... 20
DIGITAL INPUT/OUTPUT CHARACTERISTICS .......................................................... 21
SWITCHING CHARACTERISTICS - MODE 1................................................................ 22
SWITCHING CHARACTERISTICS - MODE 2................................................................ 24
SWITCHING CHARACTERISTICS - MODE 3................................................................ 26
SWITCHING CHARACTERISTICS - MODE 4................................................................ 28
SWITCHING CHARACTERISTICS - MODE 5................................................................ 30
10BASE-T CHARACTERISTICS...................................................................................... 32
CRYSTAL OSCILLATOR REQUIREMENTS.................................................................. 32
6.0 PACKAGE DIMENSIONS....................................................................................33
CS8904
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
2 DS191PP2
CS8904
T
T
T
T
Crystal LAN™ Quad Ethernet Transceiver
1.0 INTRODUCTION
1.1 General Description
The CS8904 is a true single-chip quad Ethernet
interface solution, incorporating all analog and
digital circuitry needed for a complete Ethernet
front end circuit. It includes high-performance onchip filtering, eliminating the need for external
filters. In addition, the CS8904 supports the latest
IEEE Ethernet features including full duplex and
Auto-Negotiation.
CS8904
The CS8904 incorporates four independent
Manchester encoder/decoders (ENDEC), clock
recovery circuits, 10BASE-T transceivers, and link
status LED circuits. The 10BASE-T transceivers
include drivers, receivers, and high-performance
on-chip analog filters, allowing direct connections
to low-cost isolation transformers. The CS8904’s
superior EMI characteristics are a result of the
high-quality receive and transmit filters which
eliminate the need for external fi lter packs and help
to make FCC Part 15, Class B compliance easier to
achieve. Each of the four transceivers support half
and full duplex operation and include IEEEcompliant Auto-Negotiation capability.
20 MHz
XTAL
RJ-45
10BASE-
W
LINKLED
S
I
T
C
H
I
N
G
B
U
S
SYSTEM
ASIC
Figure 1. Ethernet Switching Hub Application of CS8904
RJ-45
RJ-45
RJ-45
10BASE-
LINKLED
10BASE-
LINKLED
10BASE-
LINKLED
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS191PP2 3
CS8904
Crystal LAN™ Quad Ethernet Transceiver
Each of the CS8904 interface ports support 100,
120, and 150 Ω shielded and unshielded cables, and
automatic receive reverse-polarity detection and
correction.
1.2 System Applications
The CS8904 is designed for use in Ethernet switch,
hub, and router systems and in ATM switches with
Ethernet support. Offering the latest features of the
IEEE 802.3 specification (ISO/IEC 8802-3:1996),
the CS8904 can be easily interfaced to custom
digital system ASICs. Inputs to the CS8904 from
the digital system ASIC are: transmit data, transmit
enable, duplex selection, auto-negotiation
selection, and loopback selection (loopback from
digital system ASIC through CS8904 to digital
system ASIC), and mode selection. Mode selection
allows the CS8904 to operate with a variety of
compatible Ethernet controllers.
Outputs of the CS8904 to the digital system ASIC
are: transmit clock, receive clock, receive data, and
five status lines: collision detect, carrier detect,
jabber indication, duplex (half / full), and autonegotiation (active / inactive).
The Link Status LED indicates that there is an
operational link with the remote network device.
1.3 Key Features and Benefits
1.3.1 Low Cost, Low Noise, More Features
• High-performance on-chip 10BASE-T filters
allow designers to use simple isolation transformers instead of more costly filt er/transformer packages.
• The CS8904 is designed to be used on a 4-layer
circuit board instead of a more expensive multilayer board, saving board manufacturing costs.
• The CS8904 has been designed for very low
noise emission. As a result FCC testing and
qualification time is reduced considerably.
• Half and full duplex operation make the
CS8904 ideal for use in 10BASE-T Ethernet
switch designs and in ATM switch systems that
require 10BASE-T Ethernet ports.
• Auto-Negotiation capability that is fully compliant with the latest IEEE Ethernet specification (ISO/IEC 8802-3:1995(u)) provides the
newest Ethernet features to system designers.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
4 DS191PP2
CS8904
Crystal LAN™ Quad Ethernet Transceiver
Port A
Port B
Figure 2. Typical Connection Diagram
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS191PP2 5
CS8904
Crystal LAN™ Quad Ethernet Transceiver
Port C
Port D
Figure 2. Typical Connection Diagram (continued)
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
6 DS191PP2
CS8904
Crystal LAN™ Quad Ethernet Transceiver
2.0 PIN DESCRIPTION
CD1
COLL1
JABBER1
LINKLED1
RxDATA1
RCLK1
DUPLEX1
MODE1
MODE0
DSUB
DVDD0
DVSS0
DUPLEX0
RCLK0
RxDATA0
LINKLED0
JABBER0
COLL0
CD0
AUTONEG0
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
AUTONEG1
TxDATA1
807978
123
TXENBL1
AUTOSEL1
DUPSEL1
76
5
LOOP1
RVDD1
Rx1-
Rx1+
RVSS1
75
747372
717770696867666564
678910411
Tx1-
Tx1+
TVSS1
CS8904
100-Pin
MQFP
121314
TVDD1
(Q)
151617
RESET
MODE2
AVSS1
TVDD2
TVSS2
636261
181920
Tx2-
Tx2+
RVSS2
RVDD2
6059585756
2122232425
Rx2-
Rx2+
LOOP2
555453
2627282930
AUTOSEL2
DUPSEL2
TxENBL2
51
52
TxDATA2
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
AUTONEG2
CD2
COLL2
JABBER2
LINKLED2
RxDATA2
RCLK2
DUPLEX2
TCLK
DVSS1
DVDD1
XTAL2
XTAL1
DUPLEX3
RxCLK3
RxDATA3
LINKLED3
JABBER3
COLL3
CD3
RVDD0
Tx0-
Tx0+
RVSS0
TVSS0
RX0-
Rx0+
LOOP0
TxENBL0
TxDATA0
DUPSEL0
AUTOSEL0
RES
TVDD0
AVSS0
AVDD0
TVDD3
Tx3-
Tx3+
TVSS3
Rx3-
Rx3+
RVSS3
LOOP3
RVDD3
AUTOSEL3
TxENBL3
DUPSEL3
TxDATA3
AUTONEG3
Figure 3. CS8904 Pin Diagram
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS191PP2 7
Crystal LAN™ Quad Ethernet Transceiver
2.1 Controller Interface
DUPSEL[0:3] - Duplex Select. Input, Pins 3, 77, 53, and 27.
When AUTOSEL is low, setting this pin high will force the port into full duplex operation and
setting this pin low will force the port into half duplex operation. When AUTOSEL is high,
setting this pin high indicates that full and half duplex capability should be advertised, and
setting this pin low indicates that only half duplex capability should be advertised.
AUTOSEL[0:3] - Auto-Negotiation Select. Input, Pins 4, 76, 54, and 26.
Setting this pin high will cause the port to Auto-Negotiate, automatically selecting half or full
duplex operation. When low, Auto-Negotiation is disabled and the duplex of the port is
controlled by the DUPSEL pin.
LOOP[0:3] - Port Loopback Enable. Input, Pins 5, 75, 55, and 25.
Port Loopback Enable: Setting this pin high will cause the input data on the TxDATA pin for
this port to appear on the RxDATA pin for this port. Tx+ and Tx- will remain idle and any data
received on Rx+ and Rx- will be ignored. Setting this pin low will result in normal operation of
the port.
CS8904
TxENBL[0:3] - Transmit Enable. Input, Pins 2, 78, 52, and 28.
Transmit Enable: When this pin is asserted, the input data for this port, present on the TxDATA
pin, is input to the CS8904 using the transmit clock, TxCLK. When this pin is deasserted, Tx+
and Tx- output pins are idle.
TxDATA[0:3] - Transmit Data. Input, Pins 1, 79, 51, and 29.
The data to be transmitted is presented on this pin using NRZ encoding and synchronized by
the transmit clock, TxCLK. Data is accepted when TxENBL is high.
TxCLK - Transmit Clock. Output with 4 mA drive, Pin 42.
Common transmit clock for all four ports. TxENBL is used to control the sampling of TxDATA
using TxCLK.
COLL[0:3] - Collision Detect Status. Output with 4 mA drive, Pins 98, 82, 48, and 32.
This output pin will assert to indicate that a collision has been detected on this port and
deasserts when the collision is no longer present. When operating in full duplex mode,
collisions will not occur and COLL will not transition.
CD[0:3] - Carrier Detect Status. Output with 4 mA drive, Pins 99, 81, 49, and 31.
This output pin is asserted while receive data is available on the RxDATA pin for this port.
DUPLEX[0:3] - Duplex Status. Output with 4 mA drive, Pins 93, 87, 43, and 37.
This output remains high when the port is operating full duplex, and remains low when the port
is operating half duplex.
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8 DS191PP2
CS8904
Crystal LAN™ Quad Ethernet Transceiver
AUTONEG[0:3] - Auto-Negotiation Status. Output with 4 mA drive, Pins 100, 80, 50, and 30.
This output remains high when Auto-Negotiation has taken place successfully, and remains low
when Auto-Negotiation has failed or is disabled for this port. See Section 4.3.2 (Control and
Status Information) for more information.
RxDATA[0:3] - Re ceived Data. Output with 4 mA drive, Pins 95, 85, 45, and 35.
The data received for this port is output on this pin. This data is NRZ encoded and is
synchronized using the receive clock, RxCLK. The CD pin is asserted when receive data is
present on the RxDATA pin.
JABBER[0:3] - Jabber. Output with 4 mA drive, Pins 97, 83, 47, and 33.
This output pin will assert to indicate that a jabber condition has been detected for this port.
RxCLK[0:3] - Recovered Receive Clock. Output with 4 mA drive, Pins 94, 86, 44, and 36.
The recovered receive clock for the port is output on this pin.
2.2 10BASE-T Interface
TX+[0:3], TX-[0:3] - 10BASE-T Transmit Pair. Output, Pins 10, 69, 60, 19, 11, 70, 61, and 20.
Differential output pair that drives 10 Mb/s Manchester-encoded data to the 10BASE-T twistedpair segment.
RX+[0:3], RX-[0:3] - 10BASE-T Receive Pair. Input, Pins 6, 73, 56, 23, 7, 74, 57, and 24.
Differential input pair that receives 10 Mb/s Manchester-encoded data from the 10BASE-T
twisted-pair segment.
2.3 LED Pins
LINKLED[0:3] - Link Status LED. Open Drain Output with 10 mA drive, Pins 96, 84, 46, and 34.
This active-low output goes low and remains continuously low for a functioning 10BASE-T
link. Refer to Section 4.3.2 (Control and Status Information) for more information on using the
LINKLED pin.
2.4 General Pins
XTAL1, XTAL2 - Crystal. Input, Output, Pins 38 and 39.
A 20 MHz crystal should be connected across these pins. Alternatively, a 20 MHz signal may
be connected to XTAL1; XTAL2 is left open.
RESET - Reset. Input with Internal Weak Pullup, Pin 66.
Setting this pin low for at least 500 ns will reset the CS8904.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
DS191PP2 9
MODE[0:2] - Mode Select. Input, Pins 89, 88, and 64.
Selects the controller compatibility mode. See Table 1.
RES - Reference Resistor. Input, Pin 16.
A 4.99 kΩ ±1% resister should be connected between this input and ground.
AVDD - Analog Power. Power, Pin 14.
Provides power to the analog circuits of the CS8904.
AVSS0, AVSS1 - Analog Ground. Ground, Pins 15 and 65.
Provides a ground reference (0 V) to the analog circuits of the CS8904.
DVDD0, DVDD1 - Digital Power. Power, Pins 91 and 40.
Provides power to the digital circuits of the CS8904.
DVSS0, DVSS1 - Digital Ground. Ground, Pins 92 and 41.
CS8904
Crystal LAN™ Quad Ethernet Transceiver
Provides a ground reference (0 V) to the digital circuits of the CS8904.
TVDD[0:3] - Transmitter Analog Power. Power, Pins 13, 67, 63, and 17.
Provides power to the transmitter analog circuits of the CS8904.
TVSS[0:3] - Digital Ground. Ground, Pins 12, 68, 62, and 18.
Provides a ground reference (0 V) to the transmitter analog circuits of the CS8904.
RVDD[0:3] - Receiver Analog Power. Power, Pins 8, 72, 58, and 22.
Provides power to the receiver analog circuits of the CS8904.
RVSS[0:3] - Receiver Analog Ground. Ground, Pins 9, 71, 59, and 21.
Provides a ground reference (0 V) to the receiver analog circuits of the CS8904.
DSUB - Ground. Ground, Pin 90.
Provides ground to the substrate layer of the CS8904.
CIRRUS LOGIC ADVANCED PRODUCT DATABOOK
10 DS191PP2
CS8904
Crystal LAN™ Quad Ethernet Transceiver
Mode
Controller Compatibility
Advanced Micro Devices AM7990, Motorola 68EN360, or
compatible controllers
Intel 82586, Intel 82596, or compatible controllers Mode 2 1 0 1
Fujitsu MB86950, Fujitsu MB86960, or compatible controllers Mode 3 1 1 0
National Semiconductor 8390, Texas Instruments TMS380C26, or
compatible controllers
Seeq 8005 or compatible controller Mode 5 0 1 1
Reserved; Operation Undefined 0 1 0
Reserved; Operation Undefined 0 0 1
Reserved; Operation Undefined 0 0 0
Table 1. Mode Selection Summary
Parameter Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Mode Bits (MODE2, MODE1, MODE0) 1 0 0 1 0 1 1 1 0 1 1 1 0 1 1
Controller Compatibility AMD
Motorola
Edge of TxCLK where TxDATA is sampled Rising Falling Falling Rising Rising
Polarity of Active TxENBL High Low High High High
Polarity of Active LOOP High Low High High High
Polarity of Active COLL High Low Low High High
Edge of RxCLK where RxDATA is clocked. Rising Falling Falling Rising Rising
Polarity of Active CD High Low High High High
Level of RxDATA when CD is deasserted High High Low Low Low
RxCLK after CD is deasserted 5 cycles 5 cycles Continuous 5 cycles Continuous
Ta ble 2. Mode Operation Comparison
Intel Fujitsu National
Selected
Mode 1 1 0 0
Mode 4 1 1 1
MODE2
Pin
MODE1
TI
Pin
MODE0
Pin
SEEQ
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DS191PP2 11
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