Cirrus Logic CS8422 User Manual

Serial Audio

Input

4:1

MUX

RX0/RXP0

RX1/RXN0

RX2/RXP1

RX3/RXN1

Receiver

Clock &

Data

Recovery

(PLL)

ILRCK

ISCLK

SDIN

Sample

Rate

Converter

C or U Data Buffer

(First 5 Bytes)

Control Port & Registers

2:1

MUX

Serial Audio

Output

3:1

MUX

XTI

Clock

Generator

SDA/

CDOUT

SCL/

CCLK

AD1/ CDIN

AD0/

RMCK

General Purpose Outputs

GPO0

Format

Detect

GPO1 GPO2 GPO3

OLRCK1

OSCLK1

SDOUT1

TDM_IN

Serial Audio

Output

3:1

MUX

OLRCK2

OSCLK2

SDOUT2

AGND

XTO

Level Translators

DGND

V_REG

CS8422

24-bit, 192-kHz, Asynchronous Sample Rate Converter with

Integrated Digital Audio Interface Receiver

Sample Rate Converter Features

 140 dB Dynamic Range

 -120 dB THD+N

 No External Master Clock Required

 Supports Sample Rates up to 211 kHz

 Input/Output Sample Rate Ratios from 6:1 to

1:6

 Master Mode Master Clock/Sample Rate Ratio

Support: 64, 96, 128, 192, 256, 384, 512, 768, 1024

 16, 18, 20, or 24-bit Data I/O

 Dither Automatically Applied and Scaled to

Output Resolution

 Multiple Device Outputs are Phase Matched

Digital Audio Interface Receiver Features

 Complete EIAJ CP1201, IEC-60958, AES3,

S/PDIF Compatible Receiver

 28 kHz to 216 kHz Sample Rate Range  2:1 Differential AES3 or 4:1 S/PDIF Input Mux  De-emphasis Filtering for 32 kHz, 44.1 kHz,

and 48 kHz

 Recovered Master Clock Output: 64 x Fs,

96 x Fs, 128 x Fs, 192 x Fs, 256 x Fs, 384 x Fs, 512 x Fs, 768 x Fs, 1024 x Fs

 49.152 MHz Maximum Recovered Master

Clock Frequency

 Ultralow-jitter Clock Recovery  High Input Jitter Tolerance  No External PLL Filter Components Required  Selectable and Automatic Clock Switching  AES3 Direct Output and AES3 TX Pass-

through

 On-chip Channel Status Data Buffering  Automatic Detection of Compressed Audio

Streams

 Decodes CD Q Sub-Code

http://www.cirrus.com

NOV '12

DS692F2

CS8422

System Features

 SPI™ or I²C™ Software Mode and Stand-Alone

Hardware Mode

 Flexible 3-wire Digital Serial Audio Input Port

 Dual Serial Audio Output Ports with

Independently Selectable Data Paths

 Master or Slave Mode Operation for all Serial

Audio Ports

 Time Division Multiplexing (TDM) Mode

 Integrated Oscillator for use with External

Crystal

 Four General-purpose Output Pins (GPO)

 +3.3 V Analog Supply (VA)

 +1.8 V to 5.0 V Digital Interface (VL)

 Space-saving 32-pin QFN Package

General Description

The CS8422 is a 24-bit, high-performance, monolithic CMOS stereo asynchronous sample rate converter with an integrated digital audio interface receiver that decodes audio data according to the EIAJ CP1201, IEC60958, AES3, and S/PDIF interface standards.

Audio data is input through the digital interface receiver or a 3-wire serial audio input port. Audio is output through one of two 3-wire seria l audio output ports. Serial audio data outputs can be set to 24, 20, 18, or 16-bit word-lengths. Data into the digital interface receiver and serial audio input port can be up to 24-bits long. Input and output data can be completely asynchronous, synchronous to an external clock through XTI, or synchronous to the recovered master clock.

The CS8422 can be controlled through the control port in Software Mode or in a Stand-Alone Hardware Mode. In Software Mode, the user can control the device through an SPI or I²C control port.

Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high-quality D/A, effects processors, and computer audio systems.

The CS8422 is available in a space-saving QFN package in Commercial (-40° C to +85° C) grade. The CDB4822 is also available for device evaluation and implementation suggestions. Please refer to “Ordering

Information” on page 81 for complete details.

2 DS692F2

1. PIN DESCRIPTION ................................................................................................................................. 9

1.1 Software Mode .................................. ... ... .... ... ... ... .......................................... .... ... ... ... ..................... 9

1.2 Hardware Mode ............................. ... ... ... .... ... ... ... .... ... .......................................... ... ... ................... 11

2. CHARACTERISTICS AND SPECIFICATIONS .................................................................................... 13

RECOMMENDED OPERATING CONDITIONS .................................................................................. 13

ABSOLUTE MAXIMUM RATINGS ...................................................................................................... 13

PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTER .............................................. 14

DIGITAL FILTER CHARACTERISTICS .............................................................................................. 14

DC ELECTRICAL CHARACTERISTICS . ... ... .... ... ... ... .... ... ... .......................................... ... ... .... ... ... ... ... 15

DIGITAL INTERFACE SPECIFICATIONS ........................................................................................... 16

SWITCHING SPECIFICATIONS ......................................................................................................... 17

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE ................................................. 20

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE ...................................... ............ 21

3. TYPICAL CONNECTION DIAGRAMS .................................................................................................22

3.1 Software Mode .............................................................................................................................. 22

3.2 Hardware Mode ............................... ... ... .... ... ... ... .... ... ... .......................................... ... ................... 23

4. OVERVIEW ........................................................................................................................................... 24

5. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT ...................................................................... 24

5.1 Serial Port Clock Operation .................... .... ... ... ... .... ... ... ... .... ......................................... ................ 25

5.1.1 Master Mode ......................................................................................................................... 25

5.1.2 Slave Mode ........................................................................................................................... 25

5.1.3 Hardware Mode Control ........................................................................................................25

5.1.4 Software Mode Control ................................ .... ... ... ... .... ... ... ... ... .... ... ... ................................... 25

5.1.5 Time Division Multiplexing (TDM) Mode ................................... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 27

5.1.5.1 TDM Master Mode ..................................................................................................... 27

5.1.5.2 TDM Slave Mode ................................................................................. ...................... 27

5.1.5.3 Hardware Mode Control ................... .... ... .......................................... ... ... ................... 27

5.1.5.4 Software Mode Control .............................................................................................. 27

6. DIGITAL INTERFACE RECEIVER ....................................................................................................... 29

6.1 AES3 and S/PDIF Standards ......................................................................................................... 29

6.2 Receiver Input Multiplexer ............................................................................................................. 29

6.2.1 Hardware Mode Control ........................................................................................................29

6.2.2 Software Mode Control ................................ .... ... ... ... .... ... ... ... ... .... ... ... ................................... 29

6.2.2.1 Single-Ended Input Mode ....................................................... ... .... ... ... ... ................... 30

6.2.2.2 Differential Input Mode ............................................................................................... 30

6.3 Recovered Master Clock - RMCK .................................................................................................. 31

6.3.1 Hardware Mode Control ........................................................................................................31

6.3.2 Software Mode Control ................................ .... ... ... ... .... ... ... ... ... .... ... ... ................................... 31

6.4 XTI System Clock Mode ...................... ... .... ... ... ... .... ... .......................................... ... ... ... .... ............ 31

6.4.1 Hardware Mode Control ........................................................................................................32

6.4.2 Software Mode Control ................................ .... ... ... ... .... ... ... ... ... .... ... ... ................................... 32

6.5 AES11 Behavior ............................................................................................................................. 32

6.6 Error and Status Reporting ............................................................................................................ 32

6.6.1 Software Mode ...................................................................................................................... 32

6.6.2 Hardware Mode Control ........................................................................................................33

6.7 Non-Audio Detection ................................... ... ... ... .... ... ... ... .... ... ... ................................................... 33

6.7.1 Hardware Mode Control ........................................................................................................34

6.7.2 Software Mode Control ................................ .... ... ... ... .... ... ... ... ... .... ... ... ................................... 34

6.8 Format Detection (Software Mode Only) ....................................................................................... 34

6.9 Interrupts (Software Mode Only) .................................................................................................... 34

6.10 Channel Status and User Data Handling .....................................................................................34

6.10.1 Hardware Mode Control ...................................................................................................... 34

CS8422

DS692F2 3

CS8422

6.10.2 Software Mode Control ........................................................................................................ 35

7. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 37

7.1 SRC Data Resolution and Dither ................................................................................................... 37

7.1.1 Hardware Mode Control ........................................................................................................ 37

7.1.2 Software Mode Control .......................................................................................................... 37

7.2 SRC Locking .................................................................................................................................. 37

7.3 SRC Muting .................................................................................................................................... 38

7.4 SRC Master Clock ......................................................................................................................... 38

7.4.1 Hardware Mode Control ........................................................................................................ 39

7.4.2 Software Mode Control .......................................................................................................... 39

8. HARDWARE MODE CONTROL .......................................................................................................... 39

8.1 Hardware Mode Serial Audio Port Control ..................................................................................... 41

9. SOFTWARE MODE CONTROL ........................................................................................................... 43

9.1 Control Port Description ................................................................................................................ 43

9.1.1 SPI Mode .................................. ... ... .......................................... .... ... ...................................... 43

9.1.2 I²C Mode ................................ .......................................... ... ... ................................................ 44

9.1.3 Memory Address Pointer (MAP) ............................... .... ...... ...... ....... ...... ....... ...... ....... ...... ...... 44

10. REGISTER QUICK REFERENCE ...................................................................................................... 45

11. SOFTWARE REGISTER BIT DEFINITIONS ...................................................................................... 48

11.1 CS8422 I.D. and Version Register (01h) ..................................... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 48

11.2 Clock Control (02h) .. .... ... ... ... .......................................... .... ... ... ... ... ............................................. 48

11.3 Receiver Input Control (03h) ........................................................................................................ 49

11.4 Receiver Data Control (04h) ........................................................................................................ 49

11.5 GPO Control 1 (05h) .... ... ... ... .... ... .......................................... ... ... ... .... ... ...................................... 51

11.6 GPO Control 2 (06h) .... ... ... ... .... ... .......................................... ... ... ... .... ... ...................................... 51

11.7 Serial Audio Input Clock Control (07h) ........................................................................................ 51

11.8 SRC Output Serial Port Clock Control (08h) ...............................................................................52

11.9 Recovered Master Clock Ratio Control & Misc. (09h) ................................................................ 53

11.10 Data Routing Control(0Ah) ......................................................................................................... 54

11.11 Serial Audio Input Data Format (0Bh) ....................................................................................... 54

11.12 Serial Audio Output Data Format - SDOUT1 (0Ch) ................................................................... 55

11.13 Serial Audio Output Data Format - SDOUT2 (0Dh) .................................................................. 56

11.14 Receiver Error Unmasking (0Eh) .............................................................................................. 57

11.15 Interrupt Unmasking (0Fh) ......................................................................................................... 58

11.16 Interrupt Mode (10h) .................................................................................................................. 58

11.17 Receiver Channel Status (11h) ................................................................................................. 58

11.18 Format Detect Status (12h) ........................... .......... ............. ............. ............. ............ ................ 59

11.19 Receiver Error (13h) ................................................................................................................. 59

11.20 Interrupt Status (14h) ................................................................................................................ 60

11.21 PLL Status (15h) ....................................................................................................................... 61

11.22 Receiver Status (16h) ............................................................................................................... 62

11.23 Fs/XTI Ratio (17h - 18h) ........................................................................................................... 63

11.24 Q-Channel Subcode (19h - 22h) ................................................................................................ 63

11.25 Channel Status Registers (23h - 2Ch) ....................................................................................... 63

11.26 IEC61937 PC/PD Burst preamble (2Dh - 30h) .......................................................................... 64

12. APPLICATIONS ................................................................................................................................. 65

12.1 Reset, Power Down, and Start-Up ............................ .......................................... ......................... 65

12.2 Power Supply, Grounding, and PCB layout ................................................................................. 65

12.3 External Receiver Components ................... ... ... .... ... ... ... ............................................. .... ... ... ... ... 65

12.3.1 Attenuating Input signals ..................................................................................................... 66

12.3.2 Isolating Transformer Requirements ...................................... ............................................. 67

12.4 Channel Status Buffer Management ............................................................................................ 67

12.4.1 AES3 Channel Status (C) Bit Management ........................................................................ 67

12.4.2 Accessing the E buffer ........................................................................................................ 68

4 DS692F2

12.4.3 Serial Copy Management System (SCMS) ......................................................................... 69

12.5 Jitter Attenuation .......................................................................................................................... 69

12.6 Jitter Tolerance ............................................................................................................................ 70

12.7 Group Delay ................................................................................................................................. 70

13. PERFORMANCE PLOTS ......................................... .... ... ... ... .... ... ... ... ... .... ... ... ................................... 71

14. PACKAGE DIMENSIONS ............................................................ ... ... ... .... ... ...................................... 80

15. THERMAL CHARACTERISTICS AND SPECIFICATIONS .............................................................. 80

16. ORDERING INFORMATION ................. ... ... .......................................... .... ... ... ... .... ... ... ... ... ................ 81

17. REFERENCES ....................... ... ... .... ... ... ... ... .... ... ... .......................................... ... .... ... ... ...................... 81

18. REVISION HISTORY ....................................... ... ... ... .... ... .......................................... ... ... ................... 82

LIST OF FIGURES

Figure 1.Non-TDM Slave Mode Timing ..................................................................................................... 19

Figure 2.TDM Slave Mode Timing ............................................................................................................ 19

Figure 3.Non-TDM Master Mode Timing ................................................................................................... 19

Figure 4.TDM Master Mode Timing .......................................................................................................... 19

Figure 5.SPI Mode Timing ........................................................................................................................ 20

Figure 6.I²C Mode Timing ......................................................................................................................... 21

Figure 7.Typical Connection Diagram, Software Mode .............................................................................22

Figure 8.Typical Connection Diagram, Hardware Mode ........................................................................... 23

Figure 9.Serial Audio Interface Format – I²S ............................................................................................. 26

Figure 10.Serial Audio Interface Format – Left-Justified ........................................................................... 26

Figure 11.Serial Audio Interface Format – Right-Justified (Master Mode only) ........................................ 26

Figure 12.Serial Audio Interface Format – AES3 Direct Output ................................................................ 26

Figure 13.TDM Master Mode Timing Diagram .......................................................................................... 28

Figure 14.TDM Slave Mode Timing Diagram ................................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 28

Figure 15.TDM Mode Configuration (All CS8422 outputs are slave) ........................................................ 28

Figure 16.TDM Mode Configuration (First CS8422 output is master, all others are slave) ....................... 28

Figure 17.Single-Ended Receiver Input Structure, Receiver Mode 1 ....................................................... 30

Figure 18.Differential Receiver Input Structure ......................................................................................... 31

Figure 19.C/U Data Outputs ...................................................................................................................... 36

Figure 20.Typical Connection Diagram for Crystal Circuit ........................................................................ 38

Figure 21.Hardware Mode Clock Routing ................................................................................................. 40

Figure 22.Control Port Timing in SPI Mode ..................................... ... ... ... ... .... ... ... ... .... ... ......................... 43

Figure 23.Control Port Timing, I²C Slave Mode Write ............................................................................... 44

Figure 24.Control Port Timing, I²C Slave Mode Read ............................................................................... 44

Figure 25.De-Emphasis Filter Response .................................................................................................. 50

Figure 26.Professional Input Circuit – Differential Mode ........................................................................... 66

Figure 27.Transformerless Professional Input Circuit – Differential Mode ............. ................................... 66

Figure 28.S/PDIF MUX Input Circuit – Single-Ended ................................................................................ 66

Figure 29.Receiver Mode 1 Single-Ended Input Circuit – Differential Mode ................. ............................ 66

Figure 30.S/PDIF MUX Input Circuit – Digital Mode ................................................................................. 66

Figure 31.TTL/CMOS Input Circuit – Differential Mode ............................................................................ 66

Figure 32.Receiver Input Attenuation – Single-ended Input ..................................................................... 67

Figure 33.Receiver Input Attenuation – Differential Input ......................................................................... 67

Figure 34.Channel Status Data Buffer Structure ....................................................................................... 68

Figure 35.Flowchart for Reading the E Buffer ........................................................................................... 68

Figure 36.CS8422 PLL Jitter Attenuation Characteristics ......................................................................... 69

Figure 37.Jitter Tolerance Template ......................................................................................................... 70

Figure 38.Wideband FFT –

0 dBFS 1 kHz Tone, 48 kHz:48 kHz ......................................... .......................................... ... ... .... ... ......... 71

Figure 39.Wideband FFT –

0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz .................................... ... .... ... ... ... ... .... ... ... ... ................................ 71

CS8422

DS692F2 5

CS8422

Figure 40.Wideband FFT –

0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ...................................................................................................... 71

Figure 41.Wideband FFT –

0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ...................................................................................................... 71

Figure 42.Wideband FFT –

0 dBFS 1 kHz Tone, 48 kHz:96 kHz ......................................................................................................... 71

Figure 43.Wideband FFT –

0 dBFS 1 kHz Tone, 96 kHz:48 kHz ......................................................................................................... 71

Figure 44.Wideband FFT –

0 dBFS 1 kHz Tone, 192 kHz:48 kHz ....................................................................................................... 72

Figure 45.Wideband FFT –

-60 dBFS 1 kHz Tone, 48 kHz:96 kHz ...................................................................................................... 72

Figure 46.Wideband FFT –

-60 dBFS 1 kHz Tone, 48 kHz:48 kHz ...................................................................................................... 72

Figure 47.Wideband FFT –

-60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz ................................................................................................. 72

Figure 48.Wideband FFT –

-60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz ................................................................................................... 72

Figure 49.Wideband FFT –

-60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz ................................................................................................... 72

Figure 50.Wideband FFT –

-60 dBFS 1 kHz Tone, 96 kHz:48 kHz ...................................................................................................... 73

Figure 51.IMD –

10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz ............................................................................................73

Figure 52.Wideband FFT –

-60 dBFS 1 kHz Tone, 192 kHz:48 kHz ....................................................................................................73

Figure 53.IMD –

10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz ......................................................................................... 73

Figure 54.IMD –

10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz .........................................................................................73

Figure 55.Wideband FFT –

0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz .................................................................................................... 73

Figure 56.Wideband FFT –

0 dBFS 80 kHz Tone, 192 kHz:192 kHz ................................................................................................... 74

Figure 57.Wideband FFT –

0 dBFS 20 kHz Tone, 48 kHz:96 kHz ....................................................................................................... 74

Figure 58.Wideband FFT –

0 dBFS 20 kHz Tone, 48 kHz:48 kHz ....................................................................................................... 74

Figure 59.Wideband FFT –

0 dBFS 20 kHz Tone, 96 kHz:48 kHz ....................................................................................................... 74

Figure 60.Wideband FFT –

0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz .................................................................................................... 74

Figure 61.THD+N vs. Output Sample Rate –

0 dBFS 1 kHz Tone, Fsi = 192 kHz ........................................................................................................... 74

Figure 62.THD+N vs. Output Sample Rate –

0 dBFS 1 kHz Tone, Fsi = 48 kHz ............................................................................................................. 75

Figure 63.THD+N vs. Output Sample Rate –

0 dBFS 1 kHz Tone, Fsi = 96 kHz ............................................................................................................. 75

Figure 64.THD+N vs. Output Sample Rate –

0 dBFS 1 kHz Tone, Fsi = 44.1 kHz .......................................................................................................... 75

Figure 65.Dynamic Range vs. Output Sample Rate –

-60 dBFS 1 kHz Tone, Fsi = 192 kHz ....................................................................................................... 75

Figure 66.THD+N vs. Output Sample Rate –

0 dBFS 1 kHz Tone, Fsi = 32 kHz ............................................................................................................. 75

6 DS692F2

CS8422

Figure 67.Dynamic Range vs. Output Sample Rate –

-60 dBFS 1 kHz Tone, Fsi = 32 kHz ...... ... ... ... ... .... ... ... ... .... .......................................... ... ... ... ... .... ... ......... 75

Figure 68.Dynamic Range vs. Output Sample Rate –

-60 dBFS 1 kHz Tone, Fsi = 96 kHz ...... ... ... ... ... .... ... ... ... .... .......................................... ... ... ... ... .... ... ......... 76

Figure 69.Dynamic Range vs. Output Sample Rate –

-60 dBFS 1 kHz Tone, Fsi = 44.1 kHz ... .......................................... ... ... ... ... .... ... ... ... .... ... ......................... 76

Figure 70.Frequency Response – 0 dBFS Input ....................................................................................... 76

Figure 71.Passband Ripple – 192 kHz:48 kHz ......................................................................................... 76

Figure 72.Dynamic Range vs. Output Sample Rate –

-60 dBFS 1 kHz Tone, Fsi = 48 kHz ...... ... ... ... ... .... ... ... ... .... .......................................... ... ... ... ... .... ... ......... 76

Figure 73.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ................................................................................. 76

Figure 74.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz .............................................................................. 77

Figure 75.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ................................................................................. 77

Figure 76.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz ................................................................................. 77

Figure 77.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz ............................................................................ 77

Figure 78.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz .............................................................................. 77

Figure 79.Linearity Error –

0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz ............................................................................ 77

Figure 80.THD+N vs. Input Amplitude –

1 kHz Tone, 48 kHz:44.1 kHz ................................................................................................................... 78

Figure 81.THD+N vs. Input Amplitude –

1 kHz Tone, 48 kHz:96 kHz ...................................................................................................................... 78

Figure 82.THD+N vs. Input Amplitude –

1 kHz Tone, 96 kHz:48 kHz ...................................................................................................................... 78

Figure 83.THD+N vs. Input Amplitude –

1 kHz Tone, 44.1 kHz:192 kHz ................................................................................................................. 78

Figure 84.THD+N vs. Input Amplitude –

1 kHz Tone, 44.1 kHz:48 kHz ................................................................................................................... 78

Figure 85.THD+N vs. Input Amplitude –

1 kHz Tone, 192 kHz:48 kHz .................................................................................................................... 78

Figure 86.THD+N vs. Input Frequency –

0 dBFS, 48 kHz:44.1 kHz .......................................................................................................................... 79

Figure 87.THD+N vs. Input Frequency –

0 dBFS, 48 kHz:96 kHz ............................................................................................................................. 79

Figure 88.THD+N vs. Input Frequency –

0 dBFS, 44.1 kHz:48 kHz .......................................................................................................................... 79

Figure 89.THD+N vs. Input Frequency –

0 dBFS, 96 kHz:48 kHz ............................................................................................................................. 79

Figure 90.Total Power Supply Current vs. Differential Mode Receiver Input Sample Frequency ............. 79

DS692F2 7

LIST OF TABLES

Table 1. VLRCK Behavior ......................................................................................................................... 35

Table 2. PLL Clock Ratios ......................................................................................................................... 38

Table 3. Hardware Mode Control Settings ...... ... .... ... ... ... .... ... ... ... .... ... ... ... ................................................ 41

Table 4. Hardware Mode Serial Audio Format Control .............................................................................42

Table 5. Hardware Mode Serial Audio Port Clock Control ........... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 42

Table 6. Summary of Software Register Bits ............................................................................................ 45

Table 7. GPO Pin Configurations .............................................................................................................. 51

Table 8. ISCLK/ILRCK Ratios and SISF Settings ..................................................................................... 54

Table 9. OSCLK1/OLRCK1 Ratios and SOSF1 Settings .......................................................................... 55

Table 10. OSCLK2/OLRCK2 Ratios and SOSF2 Settings ........... ............. ............. ............. ............. ......... 57

CS8422

8 DS692F2

1. PIN DESCRIPTION

109

13 14 15 16

262728

303132

Top-Down View

32-Pin QFN Package

Thermal Pad

XTO

ILRCK

GPO3

OLRCK1

OSCLK1

SDOUT1

OSCLK2

AGND

AD0/CS

RX0/RXP0

SDOUT2 VL

TDM_IN

OLRCK2

RX1/RXN0

RX2/RXP1 RX3/RXN1

RMCK

GPO2

VD_FILT V_REG

XTI

AD1/CDIN

SDA/CDOUT

SCL/CCLK

ISCLK

GPO1

GPO0

SDIN

DGND

RST

1.1 Software Mode

CS8422

Pin Name Pin # Pin Description

AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF RX[3:0], RXP/RXN[1:0]

encoded digital data. RX[3:0] comprise the single-ended input multiplexer. RXP[1:0] comprise the

non-inverting inputs of the differential input multiplexer and RXN[1:0] comprise the inverting inputs

of the differential input multiplexer. Unused inputs should be tied to AGND/DGND.

Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure VA 3

that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter perfor-

mance of the recovered clock. AGND 4

AD0/CS

AD1/CDIN 8

SCL/CCLK 9

SDA/CDOUT 10

DS692F2 9

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be

connected to a common ground area under the chip.

Address Bit 0 (I²C) / Software Chip Select (SPI) (Input) - A falling edge on this pin puts the

CS8422 into SPI Control Port Mode. With no falling edge, the CS8422 defaults to I²C Mode. In I²C

Mode, AD0 is a chip address pin. In SPI Mode, CS

the CS8422. See “Control Port Description” on page 43.

Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin.

In SPI Mode, CDIN is the input data line to the control port interface. See “Control Port Description”

on page 43.

Software Clock (Input) - Serial control interface clock used to clock control data bits into and out of

the CS8422.

Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O

data line. In SPI Mode, CDOUT is the output data from the control port interface on the CS8422.

is used to enable the control port interface on

CS8422

Pin Name Pin # Pin Description

XTI 11

XTO 12

ILRCK 13 ISCLK 14 Serial Audio Input Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin.

SDIN 15 Serial Audio Input Data Port (Input) - Audio data serial input pin.

GPO[3:0]

V_REG 19 Voltage Regulator In (Input) - Regulator power supply input, nominally +3.3 V.

VD_FILT 20

DGND 21 VL 22 Logic Power (Input) - Input/Output power supply, typically +1.8 V, +2.5 V, +3.3 V, or +5.0 V.

SDOUT2 23 Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin. OSCLK2 24

OLRCK2 25

TDM_IN 26 SDOUT1 27 OSCLK1 28

OLRCK1 29

RMCK 31

RST

THERMAL PAD -

Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master

Clock” on page 38 for more details.

Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38 for

more details.

Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the

SDIN pin.

General Purpose Outputs (Output) - See page 51 for details. In I²C Mode, a 20 k pull-up resistor

to VL on GPO2 will set AD2 chip address bit to 1, otherwise AD2 will be 0.

18 30

Digital Voltage Regulator (Output) - Digital core voltage regulator output. Should be connected to

digital ground through a 10 µF capacitor. Typically +2.5 V. Cannot be used as an external voltage

source.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con-

nected to a common ground area under the chip.

Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2

pin.

Serial Audio Output 2 Left/ Righ t Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT2 pin.

Serial Audio Output TDM Input (Input) - Time Division Multiplexing serial audio data input. Should

remain grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 27.

Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin.

Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT 1

pin.

Serial Audio Output 1 Left/ Righ t Clock (Input/Output) - Word rate clock for the audio data on the

SDOUT 1 pin.

Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128x,

192x, 256x, 384x, 512x, 768x, or 1024x Fs, where Fs is the sample rate of the incoming AES3-

compatible data, or ISCLK/64.

Reset (Input) - When RST is low the CS8422 enters a low power mode and all internal states are

reset. On initial power up RST must be held low until the power supply is stable and all input clocks

are stable in frequency and phase.

Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dis-

sipation.

10 DS692F2

1.2 Hardware Mode

109

13 14 15 16

262728

303132

Top-Down View

32-Pin QFN Package

Thermal Pad

XTO

MCLK_OUT

SRC_UNLOCK

SDOUT1

OSCLK2

AGND

SAOF

RXP0

SDOUT2 VL

TDM_IN

OLRCK2

RXN0

RXP1 RXN1

RMCK

TX/U

VD_FILT V_REG

XTI

MS_SEL

V/AUDIO

NV/RERR

TX_SEL

RCBL

RX_SEL

DGND

RST

OSCLK1

OLRCK1

CS8422

Pin Name Pin # Pin Description

AES3/SPDIF Input (Input) - Differential receiver inputs carrying AES3 or S/PDIF encoded digital

RXP/RXN[1:0]

VA 3

AGND 4

SAOF 7

MS_SEL 8

NV/RERR 9

V/AUDIO

XTI 11 XTO 12 Crystal Out (Output) - Crystal output for Master clock. See “SRC Master Clock” on page 38.

DS692F2 11

2 5 6

data. RXP[1:0] comprise the non-inverting inputs of the differential input multiplexer; and RXN[1:0] comprise the inverting inputs of the input multiplexer. Unused inputs should be tied to AGND.

Analog Power (Input) - Analog power supply, nominally +3.3 V. Care should be taken to ensure that this supply is as noise-free as possible, as noise on this pin will directly affect the jitter performance of the recovered clock.

Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip.

Serial Audio Output Format Select (Input) - Used to select the serial audio output format after RST is released. See Table 4 on page 42 for format settings.

Master/Slave Select (Input) - Used to select Master or Slave settings for the output serial audio ports after RST is released. See Table 5 on page 42 for format settings.

Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is output by default, RERR is selected by a 20 k resistor to VL.

Validity Data/AUDIO

data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode. If a 20 k pull-up is present, the pin will be low when valid linear PCM data is present at the AES3 input.

Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “SRC Master Clock”

(Output) - If a 20 k pull-down is present on this pin, it will output serial Validity

on page 38.

CS8422

Pin Name Pin # Pin Description

MCLK_OUT 13

TX_SEL 14 RX_SEL 15 Receiver MUX Selection (Input) - Used to select the active AES3-compatible receiver input.

RCBL 16

C17

TX/U 18

V_REG 19 Voltage Reg ul ato r In (Input) - Regulator power supply input, nominally +3.3 V. VD_FILT 20

DGND 21 VL 22 Logic Power (Input) - Input/Output power supply, typically +1.8V, +2.5V, +3.3 V, or +5.0 V.

SDOUT2 23 Serial Audio Output 2 Data Port (Output) - Audio data serial output 2 pin. OSCLK2 24 Serial Audio Output 2 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT2 pin.

OLRCK2 25

TDM_IN 26

SDOUT1 27 OSCLK1 28 Serial Audio Output 1 Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT1 pin. OLRCK1 29

SRC_UNLOCK 30

RMCK 31

RST

THERMAL PAD -

Buffered MCLK (Output) - Buffered out put of XTI cl ock. If a 20k pull-up resistor to VL is present on this pin, the SRC MCLK source will be the PLL clock, otherwise it will be the ring oscillator.

TX Pin MUX Selection (Input) - Used to select the AES3-compatible receiver input for pass-through to the TX pin.

Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. Will go high for one subframe during each Z preamble following the first detected Z preamble. If no Z preamble is detected, output is indeterminate. See Figure 19 on page 36 for more detail.

Channel Status Data (Output) - Serial channel status data output from the AES3-compatible receiver, clocked by the rising and falling edges of OLRCK2 in master mode. A 20 k pull-up resistor to VL must be present on this pin to put the part in Hardware Mode.

Receiver MUX Pass-through/User Data (Output) - If no 20 k pull-up resistor is present on this pin it will output a copy of the receiver mux input selected by the TX_SEL pin. If a 20 k pull-up resistor to VL is present on this pin, it will output serial User data from the AES3 receiver, clocked by the rising and falling edges of OLRCK2 in master mode.

Digital Voltag e Regu lator Out (Output) - Digital core voltage regulator output. Should be connected to digital ground through a 10 µF capacitor. Cannot be used as an external voltage source.

Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip.

Serial Audio Output 2 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT2 pin.

Serial Audio Output 1 TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 27

Serial Audio Output 1 Data Port (Output) - Audio data serial output 1 pin. A 20 k pull-up to VL present on this pin will disable de-emphasis auto detect.

Serial Audio Output 1 Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT1 pin.

SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking” on

page 37 for more details.

Recovered Master Clock (Output) - Recovered master clock from the PLL. Frequency is 128 x, 256 x, or 512 x Fs, where Fs is the sample rate of the incoming AES3-compatible data or ISCLK/64. If a 20 k pull-up to VL is present on this pin, the SDOUT1 MCLK source will be RMCK, otherwise it will be the clock input through XTI-XTO.

Reset (Input) - When RST

reset. On initial power up RST are stable in frequency and phase.

Thermal Pad - Thermal relief pad. Should be connected to the ground plane for optimized heat dissipation.

is low the CS8422 enters a low power mode and all internal states are

must be held low until the power supply is stable and all input clocks

for details.

12 DS692F2

CS8422

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guar anteed over the S pecified Op erating Conditions. T ypical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and T

= 25° C.)

RECOMMENDED OPERATING CONDITIONS

GND = 0 V, all voltages with respect to 0 V.

Parameter Symbol Min Nominal Max Units

Power Supply Voltage

V_REG

Ambient Operating Temperature: Commercial Grade T

VL VA

1.71

3.135

-40 - +85 °C

3.3

3.30

5.25

3.465

V V V

ABSOLUTE MAXIMUM RATINGS

DGND = AGND = 0 V; all voltages with respect to 0 V. Operation beyond thes e limit s may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

Parameter Symbol Min Max Units

Power Supply Voltage

V_REG Input Current, Any Pin Except Supplies (Note 1) I Input Voltage, Any Pin Except RXP[1:0], RXN[1:0], or

RX[3:0] Input Voltage, RXP[1:0], RXN[1:0], or RX[3:0] V Ambient Operating Temperature (power applied) T Storage Temperature T

VL VA

stg

in A

-0.3

-±10mA

-0.3 VL+0.4 V

-0.3 VA+0.4 V

-55 +125 °C

-65 +150 °C

6.0

4.3

V V V

Notes:

1. Transient currents of up to 100 mA will not cause SCR latch-up.

DS692F2 13

CS8422

PERFORMANCE SPECIFICATIONS - SAMPLE RATE CONVERTER

XTI-XTO = 24.576 MHz; Input signal = 1.000 kHz, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 24-Bits. (Note 2)

Parameter Min Typ Max Units

Resolution 16 - 24 bits Sample Rate Slave

Master Sample Rate Ratio - Upsampling - - 1:6 Fsi:Fso Sample Rate Ratio - Downsampling - - 6:1 Fsi:Fso Interchannel Gain Mismatch - 0.0 - dB Interchannel Phase Deviation - 0.0 - Degrees Gain Error -0.2 - 0 dB Peak Idle Channel Noise Component - - -144 dBFS

Dynamic Range - Unweighted (20 Hz to Fso/2, -60 dBFS Input)

32 kHz:48 kHz - 140 - dB

44.1 kHz:48 kHz - 141 - dB

44.1 kHz:192 kHz - 138 - dB 48 kHz:44.1 kHz - 140 - dB 48 kHz:96 kHz - 141 - dB 96 kHz:48 kHz - 140 - dB 192kHz:32kHz - 141 - dB

Total Harmonic Distortion + Noise (20 Hz to Fso/2, 0 dBFS Input)

32 kHz:48 kHz - -134 - dB

44.1 kHz:48 kHz - -134 - dB

44.1 kHz:192 kHz - -133 - dB 48 kHz:44.1 kHz - -131 - dB 48 kHz:96 kHz - -135 - dB 96 kHz:48 kHz - -136 - dB 192kHz:32kHz - -137 - dB

XTI/2048

XTI/512

XTI/128 XTI/128

kHz kHz

Notes:

2. Fsi indicates the input sample rate. Fso indicates the output sample rate. Numbers separated by a colon indicate the ratio of Fsi to Fso.

DIGITAL FILTER CHARACTERISTICS

Parameter Min Typ Max Units

Passband (Upsampling or Downsampling) Passband Ripple - - ± 0.05 dB

Stopband (Downsampling) Stopba nd Attenuation 125 - - dB Group Delay See “Group Delay” on page 70

14 DS692F2

0.5465*Fso

--Fs

0.4535*

min(Fsi,Fso)

DC ELECTRICAL CHARACTERISTICS

AGND = DGND = 0 V; all voltages with respect to 0 V.

Parameter Min Typ Max Units

Power-Down Mode

Supply Current in power down VA

Normal Operation

Supply Current at 48 kHz Fsi and Fso VA

Supply Current at 192 kHz Fsi and Fso VA

(Note 3)

V_REG VL = 1.8 V VL = 2.5 V VL = 3.3 V VL = 5.0 V

(Note 4)

V_REG VL = 1.8 V VL = 2.5 V

VL = 3.3 V VL = 5.0 V

V_REG VL = 1.8 V VL = 2.5 V

VL = 3.3 V VL = 5.0 V

CS8422

4.7 1

0.3

7.1

16.9

102.6

18.8

15.2

2.7

3.8

5.2

5.3

18.9

32.4

6.2

8.8

12 18

µA µA µA µA µA µA

mA mA mA mA mA mA

Notes:

3. Power-Down Mode is defined as RST attached across XTI - XTO.

4. Normal operation is defined as RST interface receiver in differential mode, serial audio output port 1 in master mode sourced by the SRC, and serial audio output port 2 in master mode sourced by the AES3 receiver output.

= LOW with all clocks and data lines held static and no crystal

= HIGH. The typical values shown were measured with the digital

DS692F2 15

CS8422

DIGITAL INTERFACE SPECIFICATIONS

AGND = DGND = 0 V; all voltages with respect to 0 V.

Parameter Symbol Min Typ Max Units

Input Leakage Current (Note 5) I Input Capacitance I

in in

Digital Interface Receiver - RXP[1:0], RXN[1:0], RX[3:0 ]

Differential Input Sensitivity, RXP to RXN (Note 6) --200mVpp Differential Input Impedance, RXP and RXN to GND - 11 - k Single-Ended Input Sensitivity, RX pins, Receiver Input Mode 1

(Note 6)

Single-Ended Input Impedance, RX pins, Receiver Input Mode 1 - 11 - k High-Level Input Voltage, RX pins in Digital mode V

Low-Level Input Voltage, RX pins in Digital mode V

IH IL

Digital I/O

High-Level Output Voltage (I Low-Level Output Voltage (I High-Level Input Voltage V Low-Level Input Voltage V

= -4 mA)

= 4 mA)

IH IL

Input Hysteresis - 0.2 - V

--+32A

-8-pF

--200mVpp

0.55xVA

-0.3

.77xVL

0.65xVL

VA+0.3 V

0.3xVL V

0.8 V

-V

0.6 V

-V

Notes:

5. When a digital signal is sent to the AES RX pins, the pins will draw approximately 730 µA from the digital signal’s supply from the time RST

is released until the RX_MODE, RX_SEL, and INPUT_TYPE bits in register 03h are properly configured to allow a digital input signal on the driven pins, see Section 11.3

on page 49.

6. Maximum sensitivity in accordance with AES3-2003 section 8.3.3. Measured with eye diagram height at the specified voltage and width of at least 50% of one-half the biphase symbol period.

16 DS692F2

SWITCHING SPECIFICATIONS

Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.

Parameter Symbol Min Typ Max Units

RST

pin Low Pulse Width (Note 7)

CS8422

1--ms PLL Clock Recovery Sample Rate Range (Note 8) RMCK Output Jitter (Note 9) Differential RX Mode

Single-Ended RX Mode

XTI Frequency Crystal

28 - 216 kHz

200 475

ps RMS

12 - 27.000 MHz

Digital Clock Source 1.024 - 49.152 MHz

XTI Pulse Width High/Low

9--ns

VL = 3.3V, 5V

RMCK/MCLK_OUT Output Frequency RMCK/MCLK_OUT Output Duty Cycle

- - 49.152 MHz

45 50 55 %

Slave Mode

ISCLK Frequency ISCLK High Time ISCLK Low Time OSCLK Frequency OSCLK High Time OSCLK Low Time I/OLRCK Edge to I/OSCLK Rising Edge I/OSCLK Rising Edge to I/OLRCK Edge OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge TDM Mode OLRCK High Time (Note 10) TDM Mode OLRCK Rising Edge to OSCLK Rising Edge TDM Mode OSCLK Rising Edge to OLRCK Falling Edge

sckh

sckl

sckh

sckl

lcks

lckd

dpd

t t

lrckh

fss

fsh

ds dh

- - 49.152 MHz

9.2 - - ns

- - 26.9 MHz

16.7 - - ns

5.7 - - ns

4.2 - - ns

--15ns

3.6 - - ns

5.5 - - ns 20 - - ns

5.3 - - ns

4.2 - - ns

Master Mode (Note 11)

I/OSCLK Frequency (non-TDM Mode) 48*Fsi/o - 128*Fsi/o MHz I/OLRCK Duty Cycle 49.5 - 50.5 % I/OSCLK Duty Cycle 45 - 55 % I/OSCLK Falling Edge to I/OLRCK Edge t OSCLK Falling Edge to SDOUT Output Valid t

SDIN Setup Time Before I/OSCLK Rising Edge SDIN Hold Time After I/OSCLK Rising Edge

lcks dpd

--4.2ns

--4.6ns

2.7 - - ns

5.5 - - ns

TDM Mode OSCLK Frequency (Note 12) - - 49.152 MHz

DS692F2 17

CS8422

Parameter Symbol Min Typ Max Units

TDM Mode OSCLK Falling Edge to OLRCK Edge t

fsm

VL = 1.8V, 2.5V

RMCK/MCLK_OUT Output Frequency (VL = 1.8 V) RMCK/MCLK_OUT Output Frequency (VL = 2.5 V) RMCK/MCLK_OUT Output Duty Cycle (VL = 1.8 V) RMCK/MCLK_OUT Output Duty Cycle (VL = 2.5 V)

Slave Mode

ISCLK Frequency ISCLK High Time ISCLK Low Time

sckh

sckl

OSCLK Frequency OSCLK High Time OSCLK Low Time I/OLRCK Edge to I/OSCLK Rising Edge I/OSCLK Rising Edge to I/OLRCK Edge OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge TDM Mode OLRCK High Time (Note 10) TDM Mode OLRCK Rising Edge to OSCLK Rising Edge TDM Mode OSCLK Rising Edge to OLRCK Falling Edge

sckh

sckl

lcks

lckd

dpd

t t

lrckh

fss

fsh

ds dh

Master Mode (Note 11)

I/OSCLK Frequency (non-TDM Mode) 48*Fsi/o - 128*Fsi/o MHz I/OLRCK Duty Cycle 45 - 55 % I/OSCLK Duty Cycle 45 - 55 % I/OSCLK Falling Edge to I/OLRCK Edge t OSCLK Falling Edge to SDOUT Output Valid (VL = 1.8 V) t OSCLK Falling Edge to SDOUT Output Valid (VL = 2.5 V) t SDIN Setup Time Before I/OSCLK Rising Edge

SDIN Hold Time After I/OSCLK Rising Edge

lcks dpd dpd

TDM Mode OSCLK Frequency (Note 12) --31MHz TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 1.8V) t TDM Mode OSCLK Falling Edge to OLRCK Edge (VL = 2.5V) t

fsm fsm

Notes:

7. After powering up the CS8422, RST

should be held low until the power supplies and clocks are se ttled.

8. If ISCLK is selected as the clock source for the PLL, then the Sample Rate = ISCLK/64.

--4.2ns

--13.5MHz

--31MHz 37 50 63 % 45 50 55 %

- - 49.152 MHz

9.2 - - ns

--15.7MHz

28.7 - - ns

7.4 - - ns

6.2 - - ns

--29.5ns

4.7 - - ns

7.3 - - ns 20 - - ns

7.0 - - ns

6.2 - - ns

--5.7ns

--11.2ns

--6.4ns

4.7 - - ns

7.3 - - ns

--9.6ns

--5.7ns

18 DS692F2

CS8422

OLRCK

(input)

sckh

sckl

fsh

fss

OSCLK

(input)

TDM_IN

(input)

SDOUT

(output)

MSB

dpd

MSB-1

MSB

MSB-1

lrckh

MSB

dpd

MSB-1

I/OLRCK

(input)

I/OSCLK

(input)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

sckh

sckl

lcks

lckd

Figure 1. Non-TDM Slave Mode Timing Figure 2. TDM Slave Mode Timing

OLRCK

(output)

dpd

fsm

OSCLK

(output)

SDOUT

(output)

MSB

MSB-1

MSB

dpd

MSB-1

lcks

I/OLRCK

(output)

I/OSCLK

(output)

SDIN

(input)

SDOUT

(output)

MSB

MSB-1

Figure 3. Non-TDM Master Mode Timing Figure 4. TDM Master Mode Timing

9. Typical base band jitter in accordance with AES-12id-2006 section 3.4.2. Measurements are Time Interval Error (TIE) taken with 3rd order 100 Hz to 40 kHz band-pass filter. Measured with Sample Rate = 48 kHz.

10. OLRCK must remain high for at least 1 OSCLK period and at most 255 OSCLK periods in TDM Mode.

11. In TDM formatted master mode, the TDM_IN pin is not supported.

12. In TDM formatted master mode, the OSCLK frequency is fixed at 256*OLRCK.

DS692F2 19

SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE

dsu

sch

scl

CCLK

CDIN

css

csh

spi

srs

RST

CDOUT

scdov

cscdo

Hi-Impedance

Figure 5. SPI Mode Timing

Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.

Parameter Symbol Min M ax Unit

CCLK Clock Frequency RST

Rising Edge to CS Falling CCLK Edge to CS CS

High Time Between Transmissions

Falling to CCLK Edge

Falling (Note 13)

CCLK Low Time CCLK High Time CDIN to CCLK Rising Setup Time CCLK Rising to DATA Hold Time (Note 14) CCLK Falling to CDOUT Valid (Note 15) Time from CS

Rising to CDOUT High-Z CDOUT Rise Time CDOUT Fall Time CCLK and CDIN Rise Time (Note 16) CCLK and CDIN Fall Time (Note 16)

sck

srs

spi

csh

css

scl

sch

dsu

scdov

cscdo

06.0MHz 500 - µs 500 - ns

1.0 - µs 20 - ns 66 - ns 66 - ns 40 - ns 15 - ns

-100ns

-25ns

-100ns

CS8422

Notes:

13. t

only needed before first falling edge of CS after RST rising edge. t

spi

14. Data must be held for sufficient time to bridge the transition time of CCLK.

15. CDOUT should not be sampled during this time.

16. For f

< 1 MHz.

sck

= 0 at all other times.

spi

20 DS692F2

SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE

buf

hdst

low

hdd

high

sud

Stop Start

SDA

SCL

irs

RST

hdst

sust

susp

Start

Stop

Repeated

ack

Figure 6. I²C Mode Timing

Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF.

Parameter Symbol Min Max Unit

SCL Clock Frequency RST

Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low time Clock High Time Setup Time for Repeated Start Condition SDA Hold Time from SCL Falling (Note 17) SDA Setup time to SCL Rising Rise Time of SCL and SDA Fall Time SCL and SDA Setup Time for Stop Condition Acknowledge Delay from SCL Falling

t t

susp

scl

irs

buf

hdst

low

high

sust hdd sud

, t , t

ack

rd fd

- 100 kHz

500 - µs

4.7 - µs

4.0 - µs

4.7 - µs

4.0 - µs

4.7 - µs 10 - ns

250 - ns

- 1000 ns

-300ns

4.7 - µs

300 1000 ns

CS8422

Notes:

17. Data must be held for sufficient time to bridge the transition time, t

, of SCL.

DS692F2 21

3. TYPICAL CONNECTION DIAGRAMS

CS8422

VD_FILT

Serial Audio Input

Device

Crystal/Clock Source

Microcontroller

Serial Audio Input

Device

Serial Audio Output

Device

AES3/SPDIF/IEC60958

Receiver Circuitry

Clock Routing,

Interrupt Control,

Channel-Status, and

User Data Output

TDM Output Device

RX0/RXP0

RX1/RXN0

RX2/RXP1

RX3/RXN1

ILRCK

ISCLK

SDIN

XTI

XTO

AD0/CS

AD1/CDIN

SCL/CCLK

SDA/CDOUT

RST

32 GPO0

GPO1

GPO2

GPO3

GND

10 µF0.1 µF

RMCK

SDOUT2

OSCLK2

OLRCK2

TDM_IN

SDOUT1

OLRCK1

OSCLK1

10 µF

0.1 µF

+3.3V

+1.8V to +5V

0.1 µF

10 µF

0.1 µF

V_R

+3.3V

20 k

+VL

Figure 7. Typical Connection Diagram, Software Mode

See section 12.3 for details.

3.1 Software Mode

CS8422

22 DS692F2

3.2 Hardware Mode

CS8422

VD_FILT

Serial Audio Input

Device

AES3/SPDIF/IEC60958

Receiver Circuitry

TDM Output Device

RXP0

RXN0

RXP1

RXN1

SDOUT2

OSCLK2

OLRCK2

MCLK_OUT

TDM_IN

SDOUT1

OSCLK1

OLRCK1

Serial Audio Input

Device

Crystal/Clock

Source

XTI

XTO

10 µF

0.1 µF

Hardware Control Circuitry

RX_SEL

TX_SEL

SRC_UNLOCK

NV/RERR

RCBL

TX/U

V/AUDIO

+VL

20 k

RST

SAOF

MS_SEL

Channel Status, User, and Validity Data Handling and

TX Passthrough

10 µF

0.1 µF

+3.3V

10 µF

0.1 µF

V_R

+3.3V

0.1 µF

+1.8V to +5V

31RMCK

20 k

+VL

20 k

+VL

20 k

+VL

20 k

Figure 8. Typical Connection Diagram, Hardware Mode

See section 12.3 for details.

CS8422

DS692F2 23

CS8422

4. OVERVIEW

The CS8422 is a 24-bit, high performance, monolithic CMOS stereo asynchronous sample r ate converter with integrated digital audio interface receiver that decodes audio data according to EIAJ CP1201, IEC-60958, AES3, and S/PDIF interface standards.

Audio data is input through either a 3-wire serial audio port or the AES3-compatible digital interface receiver. Audio data is output through one of two 3-wire serial audio output ports. The serial audio ports are capable of 24, 20, 18, or 16-bit word lengths. Data in to the digital inter face receiver can be up to 24- bit. Input and output data can be completely asynchronous, synchronous to an external data clock through XTI, or synchronous to the master clock recovered from the incoming S/PDIF or AES3 data.

CS8422 can be controlled either in Software Mode or in a stand-alone Hardware Mod e. In Software Mode, the user can control the device through either a SPI or I²C control port.

Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high quality D/A, effects processors, and computer audio systems.

Figure 7 and Figure 8 show typical connections to the CS8422.

5. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT

The CS8422 provides two independent 3-wire serial audio output ports, and a 3-wire serial audio input (only available in Software Mode). The interface format should be chosen to suit the attached device either through the control port in Software Mode, or through the MS_SEL and SAOF pins in Hardware Mode. The following parameters are adjustable:

Hardware Mode

• Master or slave mode operation

• Master-mode MCLK-to-OLRCK (OLRCK1 and OLRCK2) ratios: 128, 256, and 512

• Audio data resolution of 16, 20, or 24-bits

• Left-Justified, I²S, or Right-Justified serial data formats

• Multi-channel TDM serial audio format (Serial Audio Output 1 only)

Software Mode

• Master or slave mode operation

• Master-mode MCLK-to-ILRCK and MCLK-to-OLRCK (OLRCK1 and OLRCK2) ratios: 64, 128, 192, 256, 384, 512, 768, and 1024

• Audio data resolution of 16, 18, 20, or 24-bits

• Left-Justified, I²S, or Right-Justified serial data formats

• Multi-channel TDM serial audio format

• AES3 Direct Output format

Figures 9, 10, 11, and 12 show the standard input/output formats available. The TDM serial audio format is de-

scribed in Section 5.1.5 on page 27. For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel Serial Audio Interface: A Tutorial”, available at www.cirrus.com.

24 DS692F2

5.1 Serial Port Clock Operation

5.1.1 Master Mode

When a serial port is set to master mode, its left/righ t clock (I LRCK, OLRCK1, or OLRCK2), and its serial bit-clock (ISCLK, OSCLK1, or OSCLK2) are outputs. If a serial output is source d directly by the AES3 receiver, then that serial port’s left/right clock and serial bit-clock will be synchronous with RMCK. If a serial port is routed to or from the sample rate converter (SRC), then that serial port’s left/right clock and serial bit-clock can be synchronous with either the XTI-XTO or RMCK when it is in master mode.

If a serial output is source directly by the serial input port without the use of the SRC, then all associated clocks must be synchrono us, so both serial ports must use the same master clock source. It is for this reason that, when in this mode, the serial output clock control is done throu gh the Serial Audio Input Clock

Control (07h) register.

5.1.2 Slave Mode

When a serial port is in slave mode, its left/right clock (ILRCK, OLRCK1, or OLRCK2), and its serial bitclock (ISCLK, OSCLK1, or OSCLK2) are inputs. If the serial input or a serial output has the SRC in its data path, then the serial port’s LRCK and SCLK may be asynchronous to all other serial ports. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are present in each associated LRCK phase to clock all of the data bits.

CS8422

If there are fewer SCLK periods than required to clock all the bits present in on e half LRCK period in LeftJustified and I²S Modes, data will be truncated beginning with the LSB. In Right-Justified Modes, the data will be invalid.

If a serial audio output is operated in slave mode and sourced directly by the AES3 receiver or the serial input port without the use of the sample rate converter, then the OLRCK supplied to the seri al audio output should be synchronous to Fsi or ILRCK to avoid skipped or repeated samples. The OSLIP bit (“Interrupt

Status (14h)” on page 60) is provided to indicate when skipped or repeated samples occur.

If the input sample rate, Fsi or ILRCK, is greater than the slave-mode OLRCK frequency, then dropped samples will occur. If Fsi or ILRCK is less than the slave-mode OLRCK frequency, then samples will be repeated. In either case the OSLIP bit will be set to 1 and will not be cleared until read through the control port.

5.1.3 Hardware Mode Control

In Hardware Mode, the serial audio input port is not available. SDOUT1 is th e ser ial da ta outp ut fr om the sample rate converter, and SDOUT2 is the serial audio output directly from the AES3-compatible receiver. Because there is no serial audio input available in Hardware Mode, all audio data input is done through the AES3-compatible receiver. In Hardware Mode, the serial output ports are controlled through the SAOF and MS_SEL pins. See “Hardware Mode Serial Audio Port Control” on page 41 for more details.

In Hardware Mode, there are always 64 SCLK pe riods per LRCK period when a ser ial port is set to master mode.

5.1.4 Software Mode Control

In Software Mode, the CS8422 provides a serial audio input port and two serial audio output ports. Each serial port’s clocking and data routin g options ar e fully configu rable as show n in Serial Audio Input Data

Format (0Bh), Serial A udio Ou tput Data Forma t - SDOUT 1 (0Ch) , and Serial Au dio Ou tput Dat a Forma t

- SDOUT2 (0Dh) registers, found on pages 54, 55, and 56.

DS692F2 25

+ 57 hidden pages

Cirrus Logic CS8422 User Manual

TABLE OF CONTENTS

LIST OF FIGURES

LIST OF TABLES

1. PIN DESCRIPTION

1.1 Software Mode

1.2 Hardware Mode

2. CHARACTERISTICS AND SPECIFICATIONS

3. TYPICAL CONNECTION DIAGRAMS

3.1 Software Mode

3.2 Hardware Mode

4. OVERVIEW

5. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT

5.1 Serial Port Clock Operation

5.1.1 Master Mode

5.1.2 Slave Mode

5.1.3 Hardware Mode Control

5.1.4 Software Mode Control