CIRRUS LOGIC CS8421 Service Manual

CS8421

32-bit, 192 kHz Asynchronous Sample Rate Converter

Features

! 175 dB Dynamic Range ! –140 dB THD+N ! No Programming Required ! No External Master Clock Required ! Supports Sample Rates up to 211 kHz ! Input/Output Sample Rate Ratios from 7.5:1 to

1:8

! Master Clock Support for 128 x Fs, 256 x Fs,

384 x Fs, and 512 x Fs (Master Mode)

! 16, 20, 24, or 32-bit Data I/O ! 32-bit Internal Signal Processing ! Dither Automatically Applied and Scaled to

Output Resolution

! Flexible 3-Wire Serial Digital Audio Input and

Output Ports

RST

! Master and Slave Modes for Both Input and

Output

! Bypass Mode ! Time Division Multiplexing (TDM) Mode ! Attenuates Clock Jitter ! Multiple Part Outputs are Phase Matched ! Linear Phase FIR Filter ! Automatic Soft Mute/Unmute ! +2.5 V Digital Supply (VD) ! +3.3 V or 5.0 V Digital Interface (VL) ! Space-Saving 20-Pin TSSOP and QFN

Packages

See page 2 for Ordering Information.

BYPASS

SDIN

Serial

ISCLK

ILRCK

Level Translators

MS_SEL

SAIF

SAOF

3.3 V or 5.0 V (VL)

Audio

Input

Sync Info

Serial

Port

Mode

Decoder

Preliminary Product Information

http://www.cirrus.com

Level Translators

Time

Data

Varying

Digital Filters

Digital

PLL

2.5 V (VD) GND

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Data

Sync Info

XTI XTO

Serial Audio

Data

Output

Clock

Generator

Level Translators

TDM_IN

SDOUT

OSCLK

OLRCK

SRC_UNLOCK

MCLK_OUT

JULY '05

DS641PP2

CS8421

General Description

The CS8421 is a 32-bit, high performance, monolithic CMOS stereo asynchronous sample ra te converter. Digital audio inputs and outputs can be 32, 24, 20, or 16-bits. Input and output data can be completely asynchro-

nous, synchronous to an external data clock, or the part can operate without any external clock by using an integrated oscillator.

Audio data is input and output through configur able 3-wire input/output ports. The CS8421 does no t require any software control via a control port.

Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mixing consoles, high quality D/A, effects processors, computer audio systems, and automotive audio systems.

The CS8421 is also suitable for use as an asynchronous decimation or interpolation filter. See Cirrus Logic applications note AN270, “Audio A/D Conversion with an Asynchronous Decimation Filter”, available at www.cirrus.com for more details.

The part is available in space saving 20-pin TSSOP and QF N pa ckag es and suppor ts sample rate s up to 211 kHz.

ORDERING INFORMATION

Product Description Package

TSSOP

CS8421

CDB8421

2 DS641PP2

32-bit Asynchronous Sample Rate

Converter

Evaluation Board for CS8421 - - - CDB8421

QFN

TSSOP -40° to +85°C

Pb-Free

YES

Temp Range Container

Rail CS8421-CZZ

Tape and Reel CS8421-CZZR

-10° to +70°C Rail CS8421-CNZ

Tape and Reel CS8421-CNZR

Rail CS8421-DZZ

Tape and Reel CS8421-DZZR

Order#

TABLE OF CONTENTS

1. PIN DESCRIPTIONS ............................................................................................................................ 6

1.1 TSSOP Pin Descriptions ................................................. .... ... ... ... .................................................. 6

1.2 QFN Pin Descriptions ............................................................. ... ... ... .... ... ... ..................................... 8

2. CHARACTERISTICS AND SPECIFICATIONS ................................................................................... 10

SPECIFIED OPERATING CONDITIONS............................................................................................ 10

ABSOLUTE MAXIMUM RATINGS...................................................................................................... 10

PERFORMANCE SPECIFICATIONS......................................... ......................................................... 11

DIGITAL FILTER CHARACTERISTICS .............................................................................................. 12

DC ELECTRICAL CHARACTERISTICS .......... ... ... ... .... .......................................... ... ... ... ... .... ... ... ... ... 12

DIGITAL INPUT CHARACTERISTICS................................................................................................ 13

DIGITAL INTERFACE SPECIFICATIONS .......................................................................................... 13

SWITCHING SPECIFICATIONS ......................................................................................................... 13

3. TYPICAL CONNECTION DIAGRAMS ................................................................................................15

4. GENERAL DESCRIPTION .................................................................................................................. 17

5. THREE-WIRE SERIAL INPUT/OUTPUT AUDIO PORT ..................................................................... 17

6. MODE SELECTION ............................................................................................................................. 19

7. SAMPLE RATE CONVERTER (SRC) ................................................................................................. 20

7.1 Data Resolution and Dither ... .... ... ... ... ... .......................................... .... ... ... ... .... ... ... ... ................... 20

7.2 SRC Locking and Varispeed ........ ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ................................................ 20

7.3 Bypass Mode ................ ... ... ... .... ... ... ... ... .......................................... ............................................. 20

7.4 Muting .................... .......................................... ... .......................................... ................................ 21

7.5 Group Delay and Phase Matching Between Multiple CS8421 Parts ............................................ 21

7.6 Master Clock ....... .......................................... ... .......................................... ................................... 21

7.6.1 Clocking .... ... .... ... ............................................................................. .... ... ... ... ... .... ............ 22

8. TIME DIVISION MULTIPLEXING (TDM) MODE ................................................................................. 23

9. PERFORMANCE PLOTS ............................................................................................................ 25

10. APPLICATIONS ...................... .......................................... ... .... ... ...................................................... 34

10.1 Reset, Power Down, and Start-Up ............................................................................................. 34

10.2 Power Supply, Grounding, and PCB Layout .............................................................................. 34

11. PACKAGE DIMENSIONS ................................................................................................................ 35

THERMAL CHARACTERISTICS.........................................................................................................35

THERMAL CHARACTERISTICS.........................................................................................................36

12. REVISION HISTORY ........................................................................................................................ 37

CS8421

DS641PP2 3

LIST OF FIGURES

Figure 1. Non-TDM Slave Mode Timing..................................................................................................... 14

Figure 2. TDM Slave Mode Timing ............................................................................................................ 14

Figure 3. Non-TDM Master Mode Timing................................................................................................... 14

Figure 4. TDM Master Mode Timing .......................................................................................................... 14

Figure 5. Typical Connection Diagram, No External Master Clock............................................................ 15

Figure 6. Typical Connection Diagram, Master and Slave Modes............................................................. 16

Figure 7. Serial Audio Interface Format - I²S ............................................................................................. 18

Figure 8. Serial Audio Interface Format - Left-Justified.............................................................................. 18

Figure 9. Serial Audio Interface Format - Right-Justified ........................................................................... 18

Figure 10. Typical Connection Diagram for Crystal Circuit ........................................................................22

Figure 11. TDM Slave Mode Timing Diagram............................... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ...... 23

Figure 12. TDM Master Mode Timing Diagram.......................................................................................... 23

Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave)....................................................... 24

Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave).................... 24

Figure 15. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:48 kHz..................................... 25

Figure 16. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:192 kHz................................ 25

Figure 17. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 44.1 kHz:48 kHz.................................. 25

Figure 18. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:44.1 kHz.. .... ... ... ... ... .... ... ... ... ... 25

Figure 19. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 48 kHz:96 kHz..................................... 25

Figure 20. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 96 kHz:48 kHz..................................... 25

Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Tone, 192 kHz:48 kHz................................... 26

Figure 22. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:96 kHz............................... ... 26

Figure 23. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:48 kHz............................... ... 26

Figure 24. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:192 kHz.......................... ... 26

Figure 25. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 44.1 kHz:48 kHz......................... ... ... 26

Figure 26. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 48 kHz:44.1 kHz............................... 26

Figure 27. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 96 kHz:48 kHz............................... ... 27

Figure 28. IMD, 10 kHz and 11 kHz -7 dBFS, 96 kHz:48 kHz ................................................................... 27

Figure 29. Wideband FFT Plot (16k Points) -60 dBFS 1 kHz Tone, 192 kHz:48 kHz................................ 27

Figure 30. IMD, 10 kHz and 11 kHz -7 dBFS, 48 kHz:44.1 kHz ................................................................ 27

Figure 31. IMD, 10 kHz and 11 kHz -7 dBFS, 44.1 kHz:48 kHz ................................................................ 27

Figure 32. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 44.1 kHz:48 kHz................................ 27

Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Tone, 192 kHz:192 kHz............................... 28

Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:96 kHz................................... 28

Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:48 kHz................................... 28

Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 96 kHz:48 kHz................................... 28

Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Tone, 48 kHz:44.1 kHz................................ 28

Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 192 kHz..................................... 28

Figure 39. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 48 kHz....................................... 29

Figure 40. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 96 kHz....................................... 29

Figure 41. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 44.1 kHz.................................... 29

Figure 42. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 192 kHz .................... 29

Figure 43. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz Tone, Fsi = 32 kHz....................................... 29

Figure 44. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 32 kHz ...................... 29

Figure 45. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 96 kHz ...................... 30

Figure 46. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 44.1 kHz ................... 30

Figure 47. Frequency Response with 0 dBFS Input ..................................................................................30

Figure 48. Passband Ripple, 192 kH z: 48 kHz ..................................................... ... ... ................................ 30

Figure 49. Dynamic Range vs. Output Sample Rate, -60 dBFS 1 kHz Tone, Fsi = 48 kHz ...................... 30

Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:48 kHz ....................................... 30

Figure 51. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:44.1 kHz.................................... 31

Figure 52. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 48 kHz:96 kHz ....................................... 31

CS8421

4 DS641PP2

Figure 53. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 96 kHz:48 kHz.................... ... .... ... ... ... ... 31

Figure 54. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:192 kHz.................. .... ... ... ... ... 31

Figure 55. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 44.1 kHz:48 kHz................. ... .... ... ... ... ... 31

Figure 56. Linearity Error, 0 to -140 dBFS Input, 200 Hz Tone, 192 kHz:44.1 kHz...................... ... ... ... ... 31

Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:44.1 kHz ..................................................... 32

Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone, 48 kHz:96 kHz ........................................................ 32

Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone, 96 kHz:48 kHz ........................................................ 32

Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:192 kHz ................................... .... ... ... ... ... 32

Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone, 44.1 kHz:48 kHz ..................................................... 32

Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone, 192 kHz:48 kHz ...................................................... 32

Figure 63. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:44.1 kHz........................................................... 33

Figure 64. THD+N vs. Frequency Input, 0 dBFS, 48 kHz:96 kHz.............................................................. 33

Figure 65. THD+N vs. Frequency Input, 0 dBFS, 44.1 kHz:48 kHz..................... ... ... .... ... ... ... ... .... ... ... ...... 33

Figure 66. THD+N vs. Frequency Input, 0 dBFS, 96 kHz:48 kHz.............................................................. 33

LIST OF TABLES

Table 1. TSSOP Pin Descriptions................................................................................................................ 7

Table 2. QFN Pin Descriptions..................................................................................................................... 9

Table 3. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL) ................. 19

Table 4. Serial Audio Input Port Start-Up Options (SAIF)................................................. ......................... 19

Table 5. Serial Audio Output Port Start-Up Options (SAOF) ..................................................................... 19

CS8421

DS641PP2 5

1. PIN DESCRIPTIONS

1.1 TSSOP PIN DESCRIPTIONS

CS8421

XTO SRC_UNLOCK

XTI SAIF

VD SAOF

GND VL

RST GND

BYPASS MS_SEL

ILRCK OLRCK ISCLK OSCLK

SDIN SDOUT

MCLK_OUT TDM_IN

1 2 3 4 5 6 7

20 19 18 17 16 15 14

813

Top-Down View

20-pin TSSOP Package

10 11

6 DS641PP2

Pin Name # Pin Description

CS8421

XTO 1

XTI 2

VD 3

GND 4

RST 5

BYPASS 6

ILRCK 7 ISCLK 8

SDIN 9

MCLK_OUT 10

TDM_IN 11

Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 21. Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock”

on page 21.

Digital Power (Input) - Digital core power supply. Typically +2.5 V. Ground (Input) - Ground for I/O and core logic. Reset (Input) - When RST is low the CS8421 enters a low power mode and all internal states are

reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase.

Sample Rate Converter Bypass (Input) - When BYP ASS is high, the sample rate converter will be bypassed and any data input through the serial audio input port will be directly output on the serial audio output port. When Bypass is low the sample rate converter will operate normally.

Serial Audio Input Left/Right Cl oc k (Input/Output) - Word rate clock for the audio dat a on th e SDIN pin.

Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. Serial Audio Input Data Port (Input) - Audio data serial input pin. Master Clock Output (Output) - Buffered and level shifted output for Master clock. If MCLK_OUT

is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See

“Master Clock” on page 21.

Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See

“Time Division Multiplexing (TDM) Mode” on page 23

SDOUT 12 OSCLK 13 OLRCK 14

MS_SEL 15

GND 16

VL 17

SAOF 18

SAIF 19

SRC_UNLOCK 20

Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be pulled low through a 47 kΩ resistor, but should not be pulled high.

Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin. Serial Audio Input Left/Right Cl oc k (Input/Output) - Word rate clock for the audio dat a on th e

SDOUT pin. Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio

ports at startup and reset. See

Ground (Input) - Ground for I/O and core logic. Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. Serial Audio Output Format Select (Input) - Used to select the serial audio output format at star-

tup and reset. See Table 5 on page 19 for format settings. Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup

and reset. See Table 4 on page 19 for format settings. SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and

Table 3 on page 19 for settings.

Varispeed” on page 20.

Table 1. TSSOP Pin Descriptions

DS641PP2 7

1.2 QFN PIN DESCRIPTIONS

CS8421

GND

RST

BYPASS

ILRCK

XTI

XTO

181920

Thermal Pad

Top-Down View

20-pin QFN Package

SRC_UNLOCK

SAIF

SAOF

GND

MS_SEL OLRCK

OSCLK

SDIN

ISCLK

MCLK_OUT

SDOUT

TDM_IN

8 DS641PP2

Pin Name # Pin Description

CS8421

VD 1

GND 2

RST 3

BYPASS 4

ILRCK 5 ISCLK 6

SDIN 7

MCLK_OUT 8

TDM_IN 9

SDOUT 10

OSCLK 11

reset. On initial power up RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase.

Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will be bypassed and any data input through the serial audio input port will be directly output on the serial audio output port. When Bypass is low the sample rate converter will operate normally.

Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin.

is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See

“Master Clock” on page 21.

Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See

Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be pulled low through a 47 kΩ resistor, but should not be pulled high.

Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin.

“Time Division Multiplexing (TDM) Mode” on page 23

OLRCK 12

MS_SEL 13

GND 14

VL 15

SAOF 16

SAIF 17

SRC_UNLOCK 18

XTO 19

XTI 20

THERMAL PAD -

Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin.

Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio ports at startup and reset. See

tup and reset. See Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup

and reset. See Table 4 on page 19 for format settings. SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and

Table 5 on page 19 for format settings.

Table 3 on page 19 for settings.

Varispeed” on page 20.

Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 21. Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock”

on page 21.

Thermal Pad - Thermal relief pad for optimized heat dissipation.

Table 2. QFN Pin Descriptions

DS641PP2 9

CS8421

2. CHARACTERISTICS AND SPECIFICATIONS

(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and spe cif icat ion s ar e de riv e d from measurements taken at nominal supply voltages and T

= 25°C.)

SPECIFIED OPERATING CONDITIONS

(GND = 0 V, all voltages with respect to 0 V)

Parameter Symbol Min Nominal Max Units

Power Supply Voltage

Ambient Operating Temperature: ‘-CZ’

‘-CNZ’

‘-DZ’

VL T

2.38

3.14

-10

-40

2.5

3.3 or 5.0

2.62

5.25 +70

+70 +85

V V

°C °C °C

ABSOLUTE MAXIMUM RATINGS

(GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaran te e d at th es e extremes.)

Parameter Symbol Min Max Units

Power Supply Voltage

Input Current, Any Pin Except Supplies (Note 1) Input Voltage Ambient Operating Temperature (power applied) Storage Temperature

stg

-0.3

3.5

6.0

V V

-±10mA

in A

-0.3 VL+0.4 V

-55 +125 °C

-65 +150 °C

Notes:

1. Transient currents of up to 100 mA will not cause SCR latch-up.

2. Numbers separated by a colon indicate input and ou tput sample rates. For example, 48 kHz:96 kHz indicates that Fsi = 48 khz and Fso = 96 kHz.

10 DS641PP2

CS8421

PERFORMANCE SPECIFICATIONS

(XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits, unless otherwise stated.)

Parameter Min Typ Max Units

Resolution Sample Rate with XTI = 27.000 MHz Slave

Master

Sample Rate with other XTI clocks Slave

Master

Sample Rate with ring oscillator (XTI to GND or VL, XTO floating) Sample Rate Ratio - Upsampling Sample Rate Ratio - Downsampling Interchannel Gain Mismatch Interchannel Phase Deviation Peak Idle Channel Noise Component (32-bit operation)

Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input)

44.1 kHz:48 kHz A-Weighted Unweighted

44.1 kHz:192 kHz A-Weighted Unweighted

48 kHz:44.1 kHz A-Weighted

Unweighted

48 kHz:96 kHz A-Weighted

Unweighted

96 kHz:48 kHz A-Weighted

Unweighted

192kHz:32kHz A-Weighted

Unweighted

Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS Input) 32 kHz:48 kHz

44.1 kHz:48 kHz

44.1 kHz:192 kHz

48 kHz:44.1 kHz 48 kHz:96 kHz 96 kHz:48 kHz 192kHz:32kHz

16 - 32 bits

7.2 53

XTI/3750

XTI/512

207 211

XTI/130 XTI/128

kHz kHz

12 - 96 kHz

--1:8

- - 7.5:1

-0.0-dB

- 0.0 - Degrees

- - -192 dBFS

180 177

175 172

180 177

179 176

176 173

175 172

- -161 - dB

- -171 - dB

- -130 - dB

- -160 - dB

- -148 - dB

- -168 - dB

- -173 - dB

dB dB

DS641PP2 11

DIGITAL FILTER CHARACTERISTICS

Parameter Min Typ Max Units

Passband (Upsampling or Downsampling) Passband Ripple Stopband Stopband Attenuation Group Delay

3. The equation for the group delay through the sample rate converter is (56.581 / Fsi) + (55.658 / Fso). For example, if the input sample rate is 192 kHz and the outp ut samp le rate is 96 kHz, the g roup dela y through the sample rate converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds.

DC ELECTRICAL CHARACTERISTICS

(GND = 0 V; all voltages with respect to 0 V.)

Parameters Symbol Min Typ Max Units

Power-down Mode (Note 4)

Supply Current in power down VD (Oscillator attached to XTI-XTO) VL = 3.3 V

VL = 5.0 V

Supply Current in power down VD (Crystal attached to XTI-XTO) VL = 3.3 V

VL = 5.0 V

Normal Operation (Note 5)

Supply Current at 48 kHz Fsi and Fso VD (Oscillator attached to XTI-XTO) VL = 3.3 V

VL = 5.0 V

Supply Current at 192 kHz Fsi and Fso VD (Oscillator attached to XTI-XTO) VL = 3.3 V

VL = 5.0 V

Supply Current at 48 kHz Fsi and Fso VD (Crystal attached to XTI-XTO) VL = 3.3 V

VL = 5.0 V

Supply Current at 192 kHz Fsi and Fso VD (Crystal attached to XTI-XTO) VL = 3.3 V

VL = 5.0 V

CS8421

- - 0.4535*Fso Hz

- - ±0.007 dB

0.5465*Fso - - Hz 125 - - dB

(Note 3) ms

50 100 200

100

1.5 4

2.5 4

13 24

3 7

6.5

µA µA µA

µA

mA mA

mA mA mA

4. Power Down Mode is defined as RST

= LOW with all clocks and data lines held static, except when a

crystal is attached across XTI-XTO, in which case the crystal will begin oscillating.

5. Normal operation is defined as RST

= HI.

12 DS641PP2

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