Cirrus Logic CS8420-CS, CS8420 Datasheet
CS8420
Digital Audio Sample Rate Converter
Features
l Complete IEC60958, AES3, S/PDIF, EIAJ
CP1201 compati ble transceiver with
asynchronous sample rate converter
l Flexible 3-wire serial digital i/o ports
l 8 kHz to 108 kHz sample rate range
l 1:3 and 3:1 maximum in put to outpu t sample
rate ratio
l 128 dB dynamic range
l -117 dB THD+N at 1 kHz
l Excellent performance at almost a 1:1 ratio
l Excellent clock jitter rejection
l 24 bit i/o words
l Pin and micro-controller read/write access to
Channel Status and User Data
l Micro-controller and stand-alone modes
I
General Description
The CS8420 is a stereo digi tal audio sample rate converter (SRC) with AES3 type and serial digital audio
inputs, AES3 type and serial digital audio outputs, along
with comprehensive control ability via a 4-wire microcontroller port. Channel status and user data can be
assembled in block sized buffers, making read/modify/write cycles easy.
Digital audio inputs and outputs may be 24, 20 or 16 bits.
The input data can be c ompletely asynchronous to the
output data, with the output data being synchronous to
an external system clock.
Target applications in clude CD-R, DAT, MD, DVD and
VTR equipment, mixing consoles, digital audio transmission equipment, high quality D/A and A/D converters,
effects processors and computer audio systems.
ORDERING INFO
CS8420-CS 28-pin SOIC, -10 to +70°C temp. range
CDB8420 Evaluation Board
AGND
ILRCK
ISCLK
SDIN
RXP
RXN
VA+
Serial
Audio
Input
Receiver
Misc.
Control
H/S
FILT RERR VD+
Clock &
Data
Recovery
RST OMCKEMPH U TCBL SDA/
Preliminary Product Information
RMCK
Sample
Rate
Converter
AES3
S/PDIF
Decoder
CDOUT
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
C&Ubit
Data
Buffer
Control
Port &
Registers
SCL/
CCLK
AD1/
CDIN
AD0/CSINT
AES3
S/PDIF
Encoder
Output
Clock
Generator
DGND
Serial
Audio
Output
Driver
OLRCK
OSCLK
SDOUT
TXP
TXN
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
AUG ‘99
DS245PP2
1
TABLE OF CONTENTS
1. CHARACTERISTICS/SPECIFICATIONS .................................................................................5
PERFORMANCE SPECIFICATIONS....................................................................................... 5
DIGITAL FILTER CHARACTERISTICS....................................................................................5
POWER AND THERMAL CHARACTERISTICS . ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ..... 5
DIGITAL CHARACTERISTICS................................................................................................. 6
SWITCHING CHARACTERISTICS .................... ....... ...... ...... .............................................. ..... 6
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS.................................................7
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE..................................... 8
SWITCHING CHARACTERISTICS - CONTROL PORT - I
2. TYPICAL CONNECTION DIAGRAM ......................................................................................10
3. GENERAL DESCRIPTION .....................................................................................................11
4. DATA I/O FLOW AND CLOCKING OPTIONS .......................................................................12
5. SAMPLE RATE CONVERTER (SRC) .................................................................................... 15
5.1 Dither ...............................................................................................................................15
5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register ....................................... 15
6. THREE-WIRE SERIAL AUDIO PORTS .................................................................................16
7. AES3 TRANSMITTER AND RECEIVER ................................................................................19
7.1 AES3 Receiver ................................................................................................................. 19
7.1.1 PLL, Jitter Attenuation, and Varispeed ................................................................ 19
8. OMCK OUT ON RMCK ...........................................................................................................21
9. PLL EXTERNAL COMPONENTS ..........................................................................................21
9.1 Error Reporting and Hold Function ..................................................................................21
9.2 Channel Status Data Handling .........................................................................................21
9.3 User Data Handling ..........................................................................................................22
9.4 Non-Audio Auto Detection ...............................................................................................22
9.5 AES3 Transmitter ............................................................................................................. 23
9.5.1 Transmitted Frame and Channel Status Boundary Timing ................................. 23
9.5.2 TXN and TXP Drivers ..........................................................................................23
9.6 Mono Mode Operation .....................................................................................................24
10. CONTROL PORT DESCRIPTION AND TIMING ..................................................................26
10.1 SPI Mode ....................................................................................................................... 26
2
10.2 I
C Mode ....... ...... ....... ...... ....... ...... ....... ...... ....... ............................................. ...... ..........27
10.3 Interrupts ........................................................................................................................27
11. CONTROL PORT REGISTER BIT DEFINITIONS ................................................................28
12. SYSTEM AND APPLICATIONS ISSUES .............................................................................44
12.1 Reset, Power Down and Start-up Options .....................................................................44
12.2 ID Code and Revision Code ..........................................................................................44
2C®
MODE ................................... 9
CS8420
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product info rmation describes products which are i n production, but for whic h ful l characterization data is not yet available. Advance produ ct i nformation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logi c websit e or di sk may be pri nted for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS245PP2
CS8420
12.3 Power Supply, Grounding, and PCB layout ................................................................... 44
12.4 Synchronization of Multiple CS8420s ............................................................................ 45
12.5 Extended Range Sample Rate Conversion ................................................................... 45
13. SOFTWARE MODE - PIN DESCRIPTION ....................................... ....... ...... ....................... 46
14. HARDWARE MODES ........................................................................................................... 49
14.1 Overall Description ........................................................................................................ 49
14.1.1 Hardware Mode Definitions ............................................................................... 49
14.1.2 Serial Audio Port Formats ................................................................................. 49
14.2 Hardware Mode 1 Description ....................................................................................... 50
14.2.1 Pin Description - Hardware Mode 1 .................................................................. 51
14.3 Hardware Mode 2 Description ...................................................................................... 53
14.3.1 Pin Description - Hardware Mode 2 .................................................................. 54
14.4 Hardware Mode 3 Description ....................................................................................... 56
14.4.1 Pin Description - Hardware Mode 3 .................................................................. 58
14.5 Hardware Mode 4 Description ....................................................................................... 60
14.5.1 Pin Description - Hardware Mode 4 .................................................................. 62
14.6 Hardware Mode 5 Description ....................................................................................... 64
14.6.1 Pin Description - Hardware Mode 5 .................................................................. 65
14.7 Hardware Mode 6 Description ....................................................................................... 67
14.7.1 Pin Description - Hardware Mode 6 .................................................................. 68
15. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958
TRANSMITTER AND RECEIVER COMPONENTS .............................................................. 70
15.1 AES3 Transmitter External Components ....................................................................... 70
15.2 AES3 Receiver External Components ........................................................................... 70
15.3 Isolating Transformer Requirements ............................................................................. 71
16. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT .......... 72
16.1 AES3 Channel Status(C) Bit Management .................................................................... 72
16.1.1 Manually accessing the E buffer ....................................................................... 72
16.1.2 Reserving the first 5 bytes in the E buffer ......................................................... 74
16.1.3 Serial Copy Management System (SCMS) ....................................................... 74
16.1.4 Channel Status Data E Buffer Access .............................................................. 74
16.1.5 One Byte mode ................................................................................................. 74
16.1.6 Two Byte mode ................................................................................................. 74
16.2 AES3 User (U) Bit Management .................................................................................... 75
16.2.1 Mode 1: Transmit All Zeros ............................................................................... 75
16.2.2 Mode 2: Block Mode ......................................................................................... 75
16.2.3 IEC60958 Recommended U Data Format For Consumer Applications ............ 75
16.2.4 Mode (3): Reserved .......................................................................................... 76
16.2.5 Mode (4): IEC Consumer B ............................................................................... 76
17. PARAMETER DEFINITIONS ................................................................................................ 77
18. PACKAGE DIMENSIONS .................................................................................................... 78
LIST OF FIGURES
Figure 1. Audio Ports Master Mode Timing..................................................................................... 7
Figure 2. Audio Ports Slave Mode and Data I/O Timing................................................................. 7
Figure 3. SPI Mode Timing ............................................................................................................. 8
Figure 4. I
Figure 5. Recommended Connection Diagram for Software Mode .............................................. 10
Figure 6. Software Mode Audio Data Flow Switching Options...................................................... 12
Figure 7. Serial Audio Input, using PLL, SRC enabled................................................................. 13
Figure 8. Serial Audio Input, No PLL, SRC enabled..................................................................... 13
Figure 9. AES3 Input, SRC enabled ............................................................................................. 13
Figure 10. Serial Audio Input, AES3 Input Clock Source, SRC Enabled ...................................... 13
DS245PP2 3
2
C Mode Timing.............................................................................................................. 9
CS8420
Figure 11. Serial Audio Input, SRC Output clocked by AES3 Recovered Clock........................... 14
Figure 12. AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out..................14
Figure 13. AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, no SRC.............14
Figure 14. AES3 Input to Serial Audio Output Only ......................................................................14
Figure 15. Input Serial Port to AES3 Transmitter..........................................................................14
Figure 16. Serial Audio Input Example Formats............................................................................17
Figure 17. Serial Audio Output Example Formats......................................................................... 18
Figure 18. Jitter Attenuation Characteristics of PLL with “slow” Filter Components......................20
Figure 19. Jitter Attenuation Characteristics of PLL with “medium” Filter Components................20
Figure 20. Jitter Attenuation Characteristics of PLL with “fast” Filter Components.......................20
Figure 21. AES3 Receiver Timing for C & U pin output data ........................................................22
Figure 22. AES3 Transmitter Timing for C, U and V pin input data............................................... 24
Figure 23. Mono Mode Operation Compared to Normal Stereo Operation...................................25
Figure 24. Control Port Timing in SPI Mode..................................................................................26
Figure 25. Control Port Timing in I
Figure 26. Hardware Mode 1 - Default Data Flow, AES3 Input..................................................... 50
Figure 27. Hardware Mode 2 - Default Data Flow, Serial Audio Input ..........................................53
Figure 28. Hardware Mode 3 - Transceive Data Flow, with SRC.................................................. 56
Figure 29. Hardware Mode 4 - Transceive Data Flow, without SRC............................................. 60
Figure 30. Hardware Mode 5 - AES3 Receiver Only.....................................................................64
Figure 31. Hardware Mode 6 - AES3 Transmitter Only................................................................. 67
Figure 32. Professional Output Circuit ..........................................................................................70
Figure 33. Consumer Output Circuit..............................................................................................70
Figure 34. TTL/CMOS Output Circuit............................................................................................70
Figure 35. Professional Input Circuit .............................................................................................71
Figure 36. Transformerless Professional Input Circuit .................................................................. 71
Figure 37. Consumer Input Circuit ................................................................................................71
Figure 38. TTL/CMOS Input Circuit...............................................................................................71
Figure 39. Channel Status Data Buffer Structure.......................................................................... 72
Figure 40. Channel Status Block Handling When Fso is Not Equal to Fsi....................................73
Figure 41. Flowchart for Reading the E Buffer..............................................................................73
Figure 42. Flowchart for Writing the E Buffer ................................................................................ 73
2
C Mode .................................................................................. 27
LIST OF TABLES
Table 1. PLL External Component Values .................................................................................... 21
Table 2. Summary of all Bits in the Control Register Map.............................................................29
Table 3. Hardware Mode Definitions.............................................................................................49
Table 4. Serial Audio Output Formats Available in Hardware Mode.............................................49
Table 5. Serial Audio Input Formats Available in Hardware Mode................................................ 49
Table 6. Hardware Mode 1 Start-up Options................................................................................. 50
Table 7. HW Mode 2A COPY/C and ORIG/U Pin Function ..........................................................53
Table 8. HW Mode 2 Serial Audio Port Format Selection .............................................................53
Table 9. Hardware Mode 2 Start-up Options................................................................................. 53
Table 10. Hardware Mode 3 Start-up Options............................................................................... 57
Table 11. Hardware Mode 4 Start-up Options............................................................................... 61
Table 12. Hardware Mode 5 Start-up Options............................................................................... 64
Table 13. HW 6C COPY/C and ORIG pin function .......................................................................67
Table 14. HW 6 Serial Audio Port Format Selection .....................................................................67
4 DS245PP2
1. CHARACTERISTICS/SPECIFICATIONS
CS8420
PERFORMANCE SPECIFICATIONS (T
Parameter* Symbol Min Typ Max Units
Dynamic Range 120 128 - dB
Input Sample Rate (serial input port) Fsi 8 - 108 kHz
Output Sample Rate Fso 8 - 108 kHz
Output to Input Sample Rate Ratio 0.33 - 3
Total Harmonic Distortion + Noise
1 kHz, -1dBFS, 0.33 < Fso/Fsi < 1.7
1 kHz, -1dBFS, 0.33 < Fso/Fsi < 3
10 kHz, -1dBFS, 0.33 < Fso/Fsi < 1.7
10 kHz, -1dBFS, 0.33 < Fso/Fsi < 3
Peak idle channel noise component - - -140 dBFS
Input Jitter Tolerance of SRC - - TBD ns
Resolution 16 - 24 bits
Gain Error -0.12 - 0 dB
DIGITAL FILTER CHARACTERISTICS (T
Parameter* Symbol Min Typ Max Units
Passband Upsampling
Downsampling
Passband Ripple - - ±0.007 dB
Stopband (Downsampling) 0.5465*Fso - Fsi/2 Hz
Stopband Attenuation 110 - - dB
Group Delay (Note 1) t
Group Delay Variation vs. Frequency
Interchannel Phase Deviation - - 0.0 °
= 25 °C; VA+ = VD+ = 5V ±5%)
A
THD+N
-
-
-
-
= 25 °C; VA+ = VD+ = 5V ±5%)
A
0
0
gd
∆
t
gd
- - 1.75 ms
--0.0µs
-
-
-
-
-
-
-117
-112
-110
-107
0.4535*Fsi
0.4535*Fso
dB
dB
dB
dB
Hz
Hz
Notes: 1. The value shown is for Fsi = Fso = 48 kHz. The group delay scales with input and output sample rate
according to the following formula: t
= 41/Fsi + 43/Fso
gd
POWER AND THERMAL CHARACTERISTICS (AGND, DGND = 0V, all voltages with respect
to ground)
Parameter Symbol Min Typ Max Units
Power Supply Voltage VD+,VA+ 4.75 5.0 5.25 V
Power Consumption at 96 kHz Fso and Fsi
Power Consumption at 48 kHz Fso and Fsi
Supply Current at 96 kHz Fso and Fsi VA+
VD+
Supply Current in power down (RST
Ambient Operating Temperature (Note 2) T
Junction Temperature T
Junction to Ambient thermal impedance (28 pin SOIC)
Notes: 2. ‘-CS’ parts are specified to operate over -10°C to 70 °C but are tested at 25 °C only.
* Parameter Definitions are given at the end of this data sheet
DS245PP2 5
high, VD+ & VA+)
A
J
θ
JA
-
-
-
-
-0.5- mA
-10 25 70 °C
- - 135 °C
-65-°C/W
660
350
7.0
125
TBD
TBD
TBD
TBD
mW
mW
mA
mA
CS8420
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with respect to ground)
Parameter Symbol Min Max Units
Power Supply Voltage VD+,VA+ - 6.0 V
Input Current, Any Pin Except Supply, RXP, RXN (Note 3) I
Input Current, RXP, RXN I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
in
in
in
A
stg
Notes: 3. Transient currents of up to 100mA will not cause SCR latch-up.
-±10mA
±0.25 ±TBD mA
-0.3 (VD+) + 0.3 V
-55 125 °C
-65 150 °C
DIGITAL CHARACTERISTICS (T
= 25 °C; VA+ = VD+ = 5V ±5%)
A
Parameter Symbol Min Typ Max Units
High-Level Input Voltage, except RXP, RXN V
Low-Level Input Voltage, except RXP, RXN V
Low-Level Output Voltage, (Io=-20uA), except TXP, TXN V
High-Level Output Voltage, (Io=20uA), except TXP, TXN V
Input Leakage Current I
Differential Input Voltage, RXP to RXN V
Output High Voltage, TXP, TXN (I
Output Low Voltage, TXP, TXN (I
SWITCHING CHARACTERISTICS (T
= VD+; C
= 20 pF)
L
= -21mA) (VD+) -
OH
= 21mA) - 0.4 0.7 V
OL
= 25 °C; VA+ = VD+ = 5V ±5%, Inputs: Logic 0 = 0V, Logic 1
A
IH
IL
OL
OH
in
TH
2.0 - (VD+) + 0.3 V
-0.3 - 0.8 V
--0.4V
(VD+) - 1 - - V
-±10±15µA
200 - - mV
0.7
(VD+) -
0.4
-V
Parameter Symbol Min Typ Max Units
RST
pin Low Pulse Width 200 - -
µ
s
OMCK Frequency for OMCK = 512*Fso 4.096 - 55.3 MHz
OMCK Low and High Width for OMCK = 512*Fso 8.2 - - ns
OMCK Frequency for OMCK = 384*Fso 3.072 - 41.5 MHz
OMCK Low and High Width for OMCK = 384*Fso 12.3 - - ns
OMCK Frequency for OMCK = 256*Fso 2.048 - 27.7 MHz
OMCK Low and High Width for OMCK = 256*Fso 16.4 - - ns
PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz
RMCK output jitter - 200 - ps RMS
RMCK output duty cycle 40 50 60 %
RMCK Input Frequency (Note 4) 2.048 - 27.7 MHz
RMCK Input Low and High Width (Note 4) 16.4 - - ns
AES3 Transmitter Output Jitter - - 1 ns
Notes: 4. PLL is bypassed, clock is input to the RMCK pin. The value given is guaranteed to work, with an external
RMCK applied the part will actually work at much lower frequencies.
6 DS245PP2
CS8420
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (T
5V ±5%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C
= 20 pF)
L
= 25 °C; VA+ = VD+ =
A
Parameter Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid (Note 5) t
SDIN Setup TIme Before ISCLK Active Edge (Note 5) t
SDIN Hold Time After ISCLK Active Edge (Note 5) t
dpd
ds
dh
--20ns
20 - - ns
20 - - ns
Master Mode
O/RMCK to I/OSCLK active edge delay (Note 5) t
O/RMCK to I/OLRCK delay (Note 6) t
smd
lmd
0-10ns
0-10ns
I/OSCLK and I/OLRCK Duty Cycle - 50 - %
Slave Mode
I/OSCLK Period t
I/OSCLK Input Low Width t
I/OSCLK Input High Width t
I/OSCLK Active Edge to I/OLRCK Edge (Note 5,6,7) t
I/OLRCK Edge Setup Before I/OSCLK Active Edge
(Note 5,6,8) t
sckw
sckl
sckh
lrckd
lrcks
36 - - ns
14 - - ns
14 - - ns
20 - - ns
20 - - ns
Notes: 5. The active edges of ISCLK and OSCLK are programmable.
6. The polarity of ILRCK and OLRCK is programmable.
7. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
8. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has
changed.
ILRCK
OLRCK
ISCLK
OSCLK
(output)
ILRCK
OLRCK
(output)
RMCK
OMCK
(input)
t
smd
t
lmd
(input)
ISCLK
OSCLK
(input)
SDIN
SDOUT
t
lrckd
t
lrcks
t
sckh
t
sckw
t
ds
t
dh
Figure 1. Audio Ports Master Mode Timing Figure 2. Audio Ports Slave Mode and Data I/O
Timing
t
sckl
t
dpd
DS245PP2 7
CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE (T
VA+ = VD+ = 5V ±5%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C
= 20 pF)
L
= 25 °C;
A
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 9) f
CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 10) t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 11) t
Fall Time of CCLK and CDIN (Note 11) t
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
0-6.0MHz
1.0 - -
µ
s
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
--45ns
--25ns
--25ns
- - 100 ns
- - 100 ns
Notes: 9. If Fso or Fsi is lower than 46.875 kHz, then maximum CCLK frequency should be less than 128Fso and
less than 128Fsi. This is dictated by the timing requirements necessary to access the Channel Status
and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate.
The minimum allowable input sample rate is 8 kHz, so choosing CCLK of less than or equal to
1.024 MHz should be safe for all possible conditions
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
<1 MHz.
sck
CS
t
t
sch
CCLK
CDIN
CDOUT
t
css
scl
t
r2
t
dsu
t
f2
t
dh
t
pd
t
csh
Figure 3. SPI Mode Timing
8 DS245PP2
CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - I2C® MODE (Note 12, T
25 °C; VA+ = VD+ = 5V ±5%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C
Parameter Symbol Min Typ Max Units
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 13) t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
2
Notes: 12. I
C is a registered trademark of Philips Semiconductors.
13. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
= 20 pF)
L
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
- - 100 k Hz
4.7 - -
4.0 - -
4.7 - -
4.0 - -
4.7 - -
µ
µ
µ
µ
µ
0--µs
250 - - ns
--1µs
- - 300 ns
4.7 - -
µ
=
A
s
s
s
s
s
s
SDA
SCL
Stop Start
t
buf
Repeated
Start
t
sust
t
hdst
t
r
t
t
hdst
low
t
hdd
t
high
t
sud
Figure 4. I2C Mode Timing
Specifications are subject to change without notice
Stop
t
f
t
susp
DS245PP2 9
2. TYPICAL CONNECTION DIAGRAM
Ferrite *
Bead
0.1 F
VA+ VD+
RXP
RXN
µ
0.1 F
CS8420
AES3/
SPDIF
Source
+5V
Analog
Supply *
Cable
Termination
CS8420
+5V
Digital
µ
TXP
TXN
Supply
Cable
Interface
AES3/
SPDIF
Equipment
3-wire Serial
Audio Source
Clock Source
and Control
47k
Hardware
Control
To other
CS8420’s
ILRCK
ISCLK
SDIN
RMCK
OMCK
Ω
EMPH
RERR
RST
TCBL
AGND
FILT
OLRCK
OSCLK
SDOUT
SDA/CDOUT
AD0/CS
SCL/CCLK
AD1/CDIN
INT
U
H/S
DGND
RFILT
CFILT CRIP
3-wire Serial
Audio Input
Device
Microcontroller
* A separate analog supply is only necessary in applications where
RMCK is used for a jitter sensitive task. For applications where
RMCK is not used for a jitter sensitive task, connect VA+ to VD+
via a ferrite bead. Keep the decoupling capacitor between VA+
and AGND.
Figure 5. Recommended Connection Diagram for Software Mode
10 DS245PP2
CS8420
3. GENERAL DESCRIPTION
The CS8420 is a fully asynchronous sample rate
converter plus AES3 transceiver intended to be
used in digital audio systems. Such systems include
digital mixing consoles, effects processors, tape recorders and computer multimedia systems. The
CS8420 is intended for 16, 20, and 24-bit applications where the input sample rate is unknown, or is
known to be asynchronous to the system sample
rate.
On the input side of the CS8420, AES3 or a 3-wire
serial format can be chosen. The output side produces both AES3 and a 3-wire serial format. An
I2C/SPI compatible microcontroller interface allows full block processing of channel status and
user data via block reads from the incoming AES3
data stream and block writes to the outgoing AES3
data stream. The user can also access informati on
decoded from the input AES3 data stream, such as
the presence of non-audio data and pre-emphasis,
as well as control the various modes of the device.
For users who prefer not to use a micro-controller,
six hardware modes have been provided, documented towards the end of this data sheet. In these
modes, flexibility is limited, with pins providing
some programmability.
When used for AES3 in, AES3 out applications, the
CS8420 can automatically transceive user data that
conforms to the IEC60958 recommended format.
The CS8420 also allows access to the relevant bits
in the AES3 data stream to comply with the serial
copy management system (SCMS).
The diagram on the cover of this data sheet shows
the main functional blocks of the CS8420. Figure 5
shows the supply and external connections to the
device.
Familiarity with the AES3 and IEC60958 specifications are assumed throughout this document. The
Application Note: “Overview of Digital Audio Interface Data Structures”, contains a tutorial on digital audio specifications. The paper “An
Understanding and Implementation of the SCMS
Serial Copy Management System for Digital Audio
Transmission”, by Clif Sanchez, is an excellent tutorial on SCMS. It may be obtained from Crystal
Semiconductor, or from the AES.
To guarantee system compliance, the proper standards documents should be obtained. The latest
AES3 standard should be obtained from the Audio
Engineering Society or ANSI, the latest IEC60958
standard from the International Electrotechnical
Commission and the latest EIAJ CP-1201 standard
from the Japanese Electronics Bureau.
DS245PP2 11
CS8420
T
4. DATA I/O FLOW AND CLOCKING OPTIONS
The CS8420 can be configured for nine connectivity alternatives, called data flows. Each data flow
has an associated clocking set-up. Figure 6 shows
the data flow switching, along with the control register bits which control the switches; this drawing
only shows the audio data paths for simplicity.
The AESBP switch allows a TTL level, already biphase mark encoded, data stream connected to
RXP to be routed to the TXP and TXN pin drivers.
The TXOFF switch causes the TXP and TXN outputs to be driven to ground.
In modes including the SRC function, there are two
audio data related clock domains. One domain includes the input side of SRC, plus the attached data
source. The second domain includes the output side
of the SRC, plus any attached output ports.
There are two possible clock sources. The first is
known as the recovered clock, is the output of a
PLL, and is connected to the RCMK pin. The input
to the PLL can be either the incoming AES3 data
stream, or the ILRCK word rate clock from the serial audio input port. The second clock is input via
the OMCK pin, and would normally be a crystal
derived stable clock. The Clock Source Control
Register bits determine which clock is connected to
which domain.
By studying the following drawings, and appropriately setting the Data Flow Control and Clock
Source Control register bits, the CS8420 can be
configured to fit a variety of customer requirements.
The following drawings illustrate the possible valid
data flows. The audio data flow is indicated by the
thin lines; the clock routing is indicated by the bold
lines. The register settings for the Data Flow Control register and the Clock Source Register are also
shown for each data flow. Some of the register settings may appear to be not relevant to the particular
data flow in question, but have been assigned a particular state. This is done to minimize power consumption. The AESBP data path from the RXP pin
to the AES3 output drivers, and the TXOFF control, have been omitted for clarity, but are present
and functional in all modes where the AES3 transmitter is in use.
Figures 7 and 8 show audio data entering via the serial audio input port, then passing through the sample rate converter, and then output both to the serial
audio output port and to the AES3 transmitter. Figure 7 shows the PLL recovering the input clock
from ILRCK word clock. Figure 8 shows using a
SPD1-0
ILRCK
ISCLK
SDIN
RXN
RXP
12 DS245PP2
Serial
Audio
Input
AES3
Receiver
Figure 6. Software Mode Audio Data Flow Switching Options
SRCD
Sample
Rate
Converter
AES3
Encoder
TXD1-0
Serial
Audio
Output
TXOFFAESBP
OLRCK
OSCLK
SDOU
TXP
TXN
CS8420
direct 256*Fsi clock input via the RMCK pin, instead of the PLL.
Figure 9 shows audio data entering via the AES3
Receiver. The PLL locks onto the pre-ambles in the
incoming audio stream, and generates a 256*Fsi
clock. The rate converted data is then output via the
serial audio output port and via the AES3 transmitter.
Figure 10 shows the same data flow as Figure 7.
The input clock is derived from an incoming AES3
data stream. The incoming data must be synchronous to the AES3 data stream.
Figure 11 shows the same data flow as Figure 7.
The input data must be synchronous to OMCK.
The output data is clocked by the recovered PLL
SDIN
ISCLK
ILRCK
Serial
Audio
Input
PLL
Sample
Rate
Converter
Serial
Audio
Output
AES3
Encoder
&Driver
OLRCK
OSCLK
SDOUT
TXP
TXN
clock from an AES3 input stream. This may be
used to implement a “house sync” architecture.
Figure 8 shows audio data entering via the AES3
receiver, passing through the sample rate converter,
and then exiting via the serial audio output port.
Synchronous audio data may then be input via the
serial audio input port and output via the AES3
transmitter.
Figure 13 is the same as Figure 12, but without the
sample rate converter. The whole data path is
clocked via the PLL generated recovered clock.
Figure 14 illustrates a standard AES3 receiver
function, with no rate conversion.
Figure 15 shows a standard AES3 transmitte r function, with no rate conversion.
SDIN
ISCLK
ILRCK
Serial
Audio
Input
Sample
Rate
Converter
Serial
Audio
Output
AES3
Encoder
&Driver
OLRCK
OSCLK
SDOUT
TXP
TXN
TXD1-0:
SPD1-0:
SRCD:
RMCK OMCK
Clock Source Control BitsData Flow Control Bits
00
00
0
OUTC:
INC:
RXD1-0:
0
0
00
TXD1-0:
SPD1-0:
SRCD:
RMCK OMCK
Clock Source Control BitsData Flow Control Bits
00
00
0
OUTC:
INC:
RXD1-0:
0
0
10
Figure 7. Serial Audio Input, using PLL, SRC enabled Figure 8. Serial Audio Input, No PLL, SRC enabled
RXN
RXP
AES3
Rx &
Decode
PLL
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
RMCK OMCK
Clock Source Control BitsData Flow Control Bits
00
00
1
Serial
Audio
Output
AES3
Encoder
&Driver
OUTC:
INC:
RXD1-0:
OLRCK
OSCLK
SDOUT
TXP
TXN
0
0
01
SDIN
ISCLK
ILRCK
RXN
RXP
Serial
Audio
Input
AES3
Rx
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
PLL
RMCK OMCK
00
00
0
Clock Source Control BitsData Flow ControlBits
OUTC:
INC:
RXD1-0:
Serial
Audio
Output
AES3
Encoder
&Driver
0
0
01
OLRCK
OSCLK
SDOUT
TXP
TXN
Figure 9. AES3 Input, SRC enabled Figure 10. Serial Audio Input, AES3 Input Clock
DS245PP2 13
CS8420
N
N
T
N
Figure 15. Input Serial Port to AES3 Transmitter
SDIN
ISCLK
ILRCK
Serial
Audio
Input
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
00
00
0
PLL
AES3
Rx
RXP RXN
Clock Source Control BitsDataFlow Control Bits
Serial
Audio
Output
AES3
Encoder
&Driver
RMCKOMCK
OUTC:
INC:
RXD1-0:
OLRCK
OSCLK
SDOUT
TXP
TXN
1
1
01
Figure 11. Serial Audio Input, SRC Output clocked by
AES3 Recovered Clock
ISCLKSDIN
AES3
Encoder
&Driver
ILRCK
TXP
TX
RXN
RXP
AES3
Rx &
Decode
OLRCKOSCLKSDOUT
Serial
Audio
Output
Serial
Audio
Input
ISCLKSDIN
AES3
Encoder
&Driver
0
0
01
ILRCK
TXP
TX
RXN
RXP
AES3
Sample
Rx &
Rate
Decode
Converter
PLL
RMCK OMCK
TXD1-0:
SPD1-0:
SRCD:
01
00
1
OLRCKOSCLKSDOUT
Serial
Audio
Output
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Serial
Audio
Input
Figure 12. AES3 Input, SRC to Serial Audio Output,
Serial Audio Input to AES3 Out
RXN
RXP
AES3
Rx &
Decode
PLL
Serial
Audio
Output
OLRCK
OSCLK
SDOU
PLL
RMCK
Clock Source Control BitsData Flow Control Bits
TXD1-0:
SPD1-0:
SRCD:
01
10
0
OUTC:
INC:
RXD1-0:
1
0
01
Figure 13. AES3 Input to Serial Audio Output, Serial
Audio Input to AES3 Out, no SRC
SDIN
ISCLK
ILRCK
Serial
Audio
Input
TXD1-0:
SPD1-0:
SRCD:
01
01
0
OMCK
Clock Source Control BitsData Flow ControlBits
AES3
Encoder
&Driver
OUTC:
INC:
RXD1-0:
TXP
TX
0
1
00
RMCK
Clock Source Control BitsData Flow Control Bits
TXD1-0:
SPD1-0:
SRCD:
TXOFF:
10
10
0
1
OUTC:
INC:
RXD1-0:
1
0
01
Figure 14. AES3 Input to Serial Audio Output Only
14 DS245PP2
CS8420
5. SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are
used to conceptually upsample the incoming data
to very high rate and then downsample to the outgoing rate, resulting in a 24 bit output, regardless of
the width of the input. The filtering is designed so
that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates
are greater than 44.1 kHz. When the output sample
rate becomes less than the input sa mple rate, the input is automatically bandlimited to avoid aliasing
products in the output. Careful design ensures minimum ripple and distortion products are added to
the incoming signal. The SRC also determines the
ratio between the incoming and outgoing sample
rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little
impact on the dynamic performance of the rate converter, and has no influence on the output clock.
5.1 Dither
When using the AES3 input, and when using the
serial audio input port in left justified and I2S
modes, all input data is treated as 24-bits wide. Any
truncation that has been done prior to the CS8420
to less than 24-bits should have been done using an
appropriate dither process. If the serial audio input
port is used to feed the S RC, and the port is in right
justified mode, then the input data will be truncated
to the SIRES bit setting value. If SIRES bits are set
to 16 or 20-bits, and the input data is 24-bits wide,
then truncation distortion will occur. Similarly, in
any serial audio input port mode, if an inadequate
number of bit clocks are entered (say 16 instead of
20), then the input words will be truncated, causing
truncation distortion at low levels. In summary,
there is no dithering mechanism on the input side of
the CS8420, and care must be taken to ensure that
no truncation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16, 20 or
24 bits. Optional dithering can be applied, and is
automatically scaled to the selected output word
length. This dither is not correlated between left
and right channels. It is recommended that the dither control bit be left in its default on state.
5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register
The SRC calculates the ratio between the input
sample rate and the output sample rate, and uses
this information to set up various parameters inside
the SRC block. The SRC takes some time to make
this calculation. For a worst case 3:1 to 1:3 input
sample rate transition, the SRC will take 9400/Fso
to settle (195 ms at Fso of 48 kHz). For a power-up
situation, the SRC will start from 1:1, the worst
case time becomes 8300/Fso (172 ms at Fso of
48 kHz).
If the PLL is in use (either AES3 or serial input
port), then the worst case locking time for the PLL
and the SRC is the sum of each locking time.
If Fsi is changing, for example in a varispeed application, the REUNLOCK interrupt will occur, and
the SRC will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data, but at increased distortion
levels. Once the incoming sample rate is stable,
then the REUNL OCK in terrupt will b ecome false,
and the SRC will return to normal levels of audio
quality.
The VFIFO interrupt occurs if the data buffer in the
SRC overflows, which can occur if the input sample rate changes at >10%/second.
Varispeed at Fsi slew rates approaching 10%/sec is
only supported when the input is via the serial audio input port. When using the AES3 input, high
frame rate slew rates will cause the PLL to lose
lock.
The sample rate ratio is also made available as a
register, accessible via the control port. The upper
DS245PP2 15
CS8420
2 bits of this register form the integer part of the ratio, while the lower 6 bits form the fractional part.
Since, in many instances, Fso is known, this allows
the calculation of the incoming sample rate by the
host microcontroller.
6. THREE-WIRE SERIAL AUDIO PORTS
A 3-wire serial audio input port and a 3-wire serial
audio output port is provided. Each port can be adjusted to suit the attached device via control registers. The following parameters are adjustable:
master or slave, serial clock frequency, audio data
resolution, left or right justification of the data relative to left/right clock, optional 1 bit cell delay of
the 1st data bit, the polarity of the bit clock and the
polarity of the left/right clock. By setting the appropriate control bits, many formats are possible.
Figure 16 shows a selection of common input formats, along with the control bit settings. The clocking of the input section of the CS8420 may be
derived from the incoming ILRCK word rate clock,
using the on-chip PLL. The PLL operation is described in the AES receiver description on page 19.
In the case of use with the serial audio input port,
the PLL locks onto the leading edges of the ILRCK
clock.
Figure 17 shows a selection of common output formats, along with the control bit settings. A special
AES3 direct output format is included, which allows serial output port access to the V, U, and C
bits embedded in the serial audio data stream. The
P bit is replaced by a bit indicating the location of
the start of a block. This format is only available
when the serial audio output port is being clocked
by the AES3 receiver recovered clock. Also, the received channel status block start signal is only
available in hardware mode 5, as the RCBL pin.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the appropriate
clock domain master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be synchronous to the appropriate master clock, but the
serial bit clock can be asynchronous and discontinuous if required. By appropriate phasing of the
left/right clock and control of the serial clocks,
multiple CS8420’s can share one serial port. The
left/right clock should be continuous, but the duty
cycle does not have to be 50%, provided that
enough serial clocks are present in each phase to
clock all the data bits. When in slave mode, the serial audio output port must be set to left j ustified or
I2S data.
When using the serial audio output port in slave
mode with an OLRCK input which is asynchronous to the port’s data source, then an interrupt bit
is provided to indicate when repeated or dropped
samples occur.
The CS8420 allows immediate mute of the serial
audio output port audio data via a control register
bit.
16 DS245PP2
CS8420
Left
Right
ILRCK
Left
Justified
(In)
2
I S
(In)
Right
Justified
(In)
ISCLK
SDIN
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
MSB LSB MSB LSB MSB
Left Right
LSB
MSB
Left
MSB LSB
LSB
MSB
Right
MSB LSB
LSB
SIMS SIS F SIRES1/0 SIJUST SIDEL SISPOL SILRPOL
Left Justified X X 00 0 0 0 0
2
I
S
XX00+0 1 0 1
Right Justified X X XX* 1 0 0 0
MSB
X = don’t care to match format, but does need to be set to the desired setting
2
S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
+ I
* not 11 - See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 16. Serial Audio Input Example Formats
DS245PP2 17
CS8420
AES3
Direct
(Out)
Left
Justified
(Out)
2
I S
(Out)
Right
Justified
(Out)
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
LSB
Right
MSB
LSB
Right
MSB LSB
Right
MSB
UC
VP
Left
MSB LSB MSB LSB MSB
Left Right
LSB
LSB
MSB
MSB
Left
MSB LSB
Left
UCLSB
VP
MSB
LSB
SOMS SOSF SORES1/0 SOJUST SODEL SOSPOL SOLRPOL
Left Justified X X XX* 0 0 0 0
2
I
S
XXXX*0 1 0 1
Right Justified 1 X XX* 1 0 0 0
AES3 Direct X X 11 0 0 0 0
X = don’t care to match format, but does need to be set to the desired setting
* not 11 - See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 17. Serial Audio Output Example Formats
18 DS245PP2
CS8420
7. AES3 TRANSMITTER AND RECEIVER
The CS8420 includes an AES3 type digital audio
receiver and an AES3 type digital audio transmitter. A comprehensive buffering scheme provides
read/write access to the channel status and user data. This buffering scheme is described in the Appendix: Channel Status and User Data Buffer
Management on page 72.
7.1 AES3 Receiver
The AES3 receiver accepts and decodes audio and
digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
The receiver consists of a differential input stage,
accessed via pins RXP and RXN, a PLL based
clock recovery circuit, and a decoder which separates the audio data from the channel status and
user data.
External components are used to terminate and isolate the incoming data cables from the CS8420.
These components are detailed in the Appendix
“External AES/SPDIF/IEC60958 Transmitter and
Receiver Components” on page 70.
7.1.1 PLL, Jitter Attenuation, and Varispeed
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Although the on-chip sample rate converter is
immune to large amounts of jitter, there are some
applications where low jitter in the recovered
clock, presented on the RMCK pin, is important.
For this reason, the PLL has been designed to have
good jitter attenuation characteristics, shown in
Figures 18, 19 & 20. In addition, the PLL has been
designed to only use the preambles of the AES3
stream to provide lock update information to the
PLL. This results in the PLL being immune to data
dependent jitter affects, since the AES3 preambles
do not vary with the data. The PLL has the ability
to lock onto a wide range of input sample rates,
with no external component changes. If the sample
rate of the input subsequently changes, for example
in a varispeed application, then the PLL will only
track up to ±12.5% from the nominal center sample
rate. The nominal center sample rate is the sample
rate that the PLL first locks onto upon application
of an AES3 data stream, or after enabling the
CS8420 clocks by setting the RUN control bit. If
the 12.5% sample rate limit is exceeded, the PLL
will return to its wide lock range mode, and re-acquire a new nominal center sample rate.
DS245PP2 19
-60
-50
-40
-30
-20
-10
0
10
1 10 100 1000 10000 100000
Jitter Frequen c y (H z)
Jitter Attenuation (dB)
-60
-50
-40
-30
-20
-10
0
10
1 10 100 1000 10000 100000
Jitter Frequency (Hz)
Jitter Attenuation (dB)
Figure 20. Jitter Attenuation Characteristics of PLL
with “fast” Filter Components
CS8420
10
0
-10
-20
-30
-40
Jitter Attenuation (dB)
-50
-60
1 10 100 1000 10000 100000
Jitter Frequency (Hz)
Figure 18. Jitter Attenuation Characteristics of PLL
with “slow” Filter Components
Figure 19. Jitter Attenuation Characteristics of PLL
with “medium” Filter Components
20 DS245PP2
CS8420
8. OMCK OUT ON RMCK
A special mode is available that allows the clock
that is being input through the OMCK pin to be output through the RMCK pin. This feature is controlled by the SWCLK bit in register 4 of the
control registers. When the PLL loses lock the frequency of the VCO drops to 300 kHz. The SWCLK
function allows the clock from RMCK to be used
as a clock in the system without any disruption
when input is removed from the Receiver.
9. PLL EXTERNAL COMPONENTS
The PLL behavior is affected by the external filte r
component values. Figure 5 shows the configuration of the required 2 capacitors and 1 resistor. Two
alternate sets of component values are recommended, depending on the requirements of the applica -
tion (see Table 1). The default set, called “fast”,
accommodates input sample rates of 16 kHz to
108 Hz with no component changes. It has the
highest corner frequency jitter attenuation curve,
and takes the shortest time to lock. The alternate
component set, called “medium” allows the lowest
input sample rate to be 8 kHz, and increases the
lock time of the PLL. Lock times are worst case for
an Fsi transition of 96 kHz.
9.1 Error Reporting and Hold Function
While decoding the incoming AES3 data stream,
the CS8420 can identify several kinds of error, indicated in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked t o
the incoming AES3 data. The V bit reflects the current validity bit status. The CONF (confidence) bit
indicates the amplitude of the eye pattern opening,
indicating a link that is close to generating errors.
The BIP (bi-phase) error bit indicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity error.
The error bits are “sticky”: they are set on the first
occurrence of the associated error, and will remain
set until the user reads the register via the control
port. This enables the register to log all unmasked
errors that occurred since the last time the register
was read.
The Receiver Error Mask register allows masking
of individual errors. The bits in this register serve
as masks for the corresponding bits of the Receiver
Error Register. If a mask bit is set to 1, the error is
considered unmasked, meaning that its occurrence
will be reported in the receiver error register, will
affect the RERR pin, will invoke the occurrence of
a RERR interrupt, and will affect the current audio
sample according to the status of the HOLD bits.
The HOLD bits allow a choice of holding the previous sample, replacing the current sample with
zero (mute), or do not change the current audio
sample. If a mask bit is set to 0, the error is c onsidered masked, meaning that its occurrence wil l not
be reported in the receiver error register, will not
induce a pulse on RERR or generate a RERR interrupt, and will not affect the current audio sample.
The QCRC and CCRC errors do not affect the current audio sample, even if unmasked.
9.2 Channel Status Data Handling
The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register.
The setting of the CHS bit in the Channel Status
Data Buffer Control register determines whether
Ty p e
Medium 0.909 1.8 33 8 to 96 56
Fast 1.78 0.47 8.2 16 to 108 15
DS245PP2 21
RFILT (kΩ)CFILT (µF) CRIP (nF) Fsi Range (kHz)
Table 1. PLL External Component Values
PLL Lock Time (ms)
CS8420
g
the channel status decodes are from the A channel
(CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly.
Also, for consumer data, the COPY (copyright) bit
is extracted, and the category code and L bits are
decoded to determine SCMS status, indicated by
the ORIG (original) bit. Finally, the AUDIO bit is
extracted, and used to set an AUDIO indicator, as
described in the Non-Audio Auto Detection section
below.
If 50/15 µs pre-emphasis is detected, then this is reflected in the state of the EMPH pin.
The encoded sample word length channel status
bits are decoded according to AES3-1992 or IEC
60958. If the AES3 receiver is the data source for
the SRC, then the SRC audio input data is truncated
according to the channel status word length settings. Audio data routed to the serial audio output
port is unaffected by the word length settings; all
24 bits are passed on as received.
The Appendix: Channel Status and User Data Buffer Management (page 72) describes the overall
handling of CS and U data.
9.3 User Data Handling
The incoming user data is buffered in a user accessible buffer. Various automatic modes of re-transmitting received U data are provided. The
Appendix: Channel Status and User Data Buffer
Management (page 72) describes the overall handling of CS and U data.
Received U data may also be output to the U pin,
under the control of a control register bit. Depending on the data flow and clocking options selected,
there may not be a clock available to qualify the U
data output. Figure 21 illustrates the timing.
If the incoming user data bits have been encoded as
Q-channel subcode, then the data is decoded and
presented in 10 consecutive register locations. An
interrupt may be enabled to indicate the decoding
of a new Q-channel block, which may be read via
the control port.
9.4 Non-Audio Auto Detection
Since it is possible to convey non-audio data in an
AES3 data stream, it is important to know whether
the incoming AES3 data stream is digital audio or
not. This information is typically conveyed in
channel status bit 1 (AUDIO), which is extracted
RCBL
out
VLRCK
C, U
Output
RCBL and C output ar e only availab le in hardwar e mode 5.
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If no S RC is used, and the se rial audio ou tput port i s in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
C, U transitions are ali
22 DS245PP2
ned within 1%of VLRCK period to VLRCK edges
Figure 21. AES3 Receiver Timing for C & U pin output data
±
CS8420
automatically by the CS8420. However, certain
non-audio sources, such as AC3 or MPEG encoders, may not adhere to this convention, and the bit
may not be properly set. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code,
consisting of 0x0000, 0x0000, 0x0000, 0x0000,
0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be
asserted. If no additional sync codes are detec ted
within the next 4096 frames, AUTODETECT will
be de-asserted until another sync code is detected.
The AUDIO bit in the Receiver Channel Status register is the logical OR of AUTODETECT and the
received channel status bit 1. If non-audio data is
detected, the data is still processed exactly as if it
were normal audio. It is up to the user to mute the
outputs as required.
9.5 AES3 Transmitter
The AES3 transmitter encodes and transmits audio
and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
Audio and control data are multiplexed together
and bi-phase mark encoded. The resulting bit
stream is then driven directly, or through a transformer, to an output connector.
The transmitter is usually clocked from the output
side clock domain of the sample rate converter.
This clock may be derived from the clock input pin
OMCK, or from the incoming data. In data flows
with no SRC, and where OMCK is asynchronous to
the data source, an interrupt bit is provided that will
go high every time a data sample is dropped or repeated.
The channel status (C) and user channel (U) bits in
the transmitted data stream ar e taken from storage
areas within the CS8420. The user can manipulate
the contents of the internal storage with a microcontroller. The CS8420 will also run in one of several automatic modes. The Appendix: Channel Status and User Data Buffer Management (page 72)
provides detailed descriptions of each automatic
mode, and describes methods for accessing the
storage areas. The transmitted user data can optionally be input via the U pin, under the control of a
control port register bit. Figure 22 shows the timing
requirements for inputting U data via the U pin.
9.5.1 Transmitted Frame and Channel Status Boundary Timing
The TCBL pin may be an input or an output, and is
used to control or indicate the start of transmitted
channel status block boundaries.
In some applications, it may be necessary to control
the precise timing of the transmitted AES3 frame
boundaries. This may be achieved in 3 ways:
a) With TCBL configured as an input, when TCBL
transitions high for >3 OMCK clocks, it will cause
a frame start, and a new channel status block start.
b) If the AES3 output comes from the AES3 input,
while there is no SRC, setting TCBL as output will
cause AES3 output frame boundaries to align with
AES3 input frame boundaries.
c) If the AES3 output comes from the serial audio
input port while the port is in slave mode, and
TCBL is set to output, then the start of the A channel sub-frame will be aligned with the leading edge
of ILRCK.
9.5.2 TXN and TXP Drivers
The line drivers are low skew, low impedance, differential outputs capable of driving cables directly.
Both drivers are set to ground during reset (RST =
low), when no AES3 transmit clock is provided,
and optionally under the control of a register bit.
The CS8420 also allows immediate mute of the
AES3 transmitter audio data via a control register
bit.
External components are used to terminate and isolate the external cable from the CS8420. These
components are detailed in the Appendix “External
DS245PP2 23
CS8420
y
TCBL
in or out
VLRCK
C, U, V
Input
Tsetup Thold
TCBL
in or out
VLRCK
U
Input
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CUV timing.
VLRCK duty cycle is 50%.
In stereo mode, VLRCK = AES3 frame rate. In mono mode, VLRCK = 2*AES3 frame rate
If the serial audio output port is in master mode, and TCBL is an output, and the SRC is not in use,
then VLRCK = OLRCK.
If the serial audio input port is in master mode, and TCBL is an input, and the SRC is not between
the serial audio input port and the AES3 transmitter, then VLRCK = ILRCK.
Otherwise, VLRCK needs to be externall
AES3 Transmitter in Stereo Mode
CUV CUV CUV CUV
Tsetup = >7.5% AES3 frame time
Thold = 0
AES3 Transmitter in Mono Mode
U
Tsetup Thold
created, if required
T setup = >15% AES3 frame time
Thold = 0
U
Figure 22. AES3 Transmitter Timing f or C, U and V pin input data
AES/SPDIF/IEC60958 Transmitter and Receiver
Components” on page 70.
9.6 Mono Mode Operation
Currently, the AES3 standard is being updated to
include options for 96 kHz sample rate operation.
One method is to double the frame rate of the current format. This results in a 96 kHz sample rate,
stereo signal carried over a single twisted pair cable. An alternate method is where the 2 sub-frames
in a 48 kHz frame rate AES3 signal are used to carry consecutive samples of a mono signal, resulting
in a 96 kHz sample rate stream. This allows older
equipment, whose AES3 transmitters and receivers
are not rated for 96 kHz frame rate operation, to
handle 96 kHz sample rate information. In this
“mono mode”, 2 AES3 cables are needed for stereo
data transfer. The CS8420 offers mono mode operation, both for the AES3 receiver and for the AES3
transmitter. Figure 23 shows the operation of mono
mode in comparison with normal stereo mode. The
receiver and transmitter sections may be independently set to mono mode via the MMR and MMT
control bits.
The receiver mono mode effectively doubles Fsi
compared to the input frame rate. The clock output
on the RMCK pin tracks Fsi, and so is doubled in
frequency compared to stereo mode. In mono
mode, A and B sub-frames are routed to the SRC
inputs as consecutive samples.
When the transmitter is in mono mode, either A or
B SRC consecutive outputs are routed alternately
to A and B sub-frames in the AES3 output stream.
Which channel status block is transmitted is also
selectable.
For the AES3 input to serial audio port output data
flow, in receiver mono mode, then the receiver will
24 DS245PP2
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