Cirrus Logic CS8420 User Manual
Digital Audio Sample Rate Converter
CS8420
Features
Complete IEC60958, AES3, S/PDIF, EIAJ
CP1201-compatible Transceiver with
Asynchronous Sample Rate Converter
Flexible 3-wire Serial Digital I/O Ports
8-kHz to 108-kHz Sample Rate Range
1:3 and 3:1 Maximum Input to Output Sample
Rate Ratio
128 dB Dynamic Range
-117 dB THD+N at 1 kHz
Excellent Performance at Almost a 1:1 Ratio
Excellent Clock Jitter Rejection
24-bit I/O Words
Pin and Microcontroller Read/Write Access to
Channel Status and User Data
Microcontroller and Stand-Alone Modes
General Description
The CS8420 is a stereo digital audio sample rate converter (SRC) with AES3-type and serial digital audio
inputs, AES3-type and serial digital audio outputs, and
includes comprehensive control ability via a 4-wire microcontroller port. Channel status and user data can be
assembled in block-sized buffers, making
read/modify/write cycles easy.
Digital audio inputs and outputs may be 24, 20, or 16
bits. The input data can be completely asynchronous to
the output data, with the output data being synchronous
to an external system clock.
The CS8420 is available in a 28-pin SOIC package in
both Commercial (-10º to +70º C) and Automotive
grades (-40º to +85º C). The CDB8420 Customer Demonstration board is also available for device evaluation
and implementation suggestions.
Please refer to “Ordering Information” on page 93 for ordering information.
Target applications include CD-R, DAT, MD, DVD and
VTR equipment, mixing consoles, digital audio transmission equipment, high-quality D/A and A/D
converters, effects processors, and computer audio
systems.
VA+
ILRCK
ISCLK
SDIN
RXP
RXN
http://www.cirrus.com
Serial
Audio
Input
Receiver
Misc.
Control
H/S
AGND
FILT RERR VD+
Clock &
Data
Recovery
RST OMCKEMPH U TCBL SDA/
RMCK
AES3
S/PDIF
Decoder
CDOUT
Copyright © Cirrus Logic, Inc. 2007
(All Rights Reserved)
Sample
Rate
Converter
C&Ubit
Data
Buffer
Control
Port &
Registers
SCL/
CCLK
AD1/
CDIN
AD0/CSINT
AES3
S/PDIF
Encoder
Output
Clock
Generator
DGND
Serial
Audio
Output
Driver
OLRCK
OSCLK
SDOUT
TXP
TXN
APRIL '07
DS245F4
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6
SPECIFIED OPERATING CONDITIONS .............................................................................................. 6
ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6
PERFORMANCE SPECIFICATIONS .................................................................................................... 7
DIGITAL FILTER CHARACTERISTICS .. ....................................... ... ... ... .... ... ... ... .... ... ...........................7
DC ELECTRICAL SPECIFICATIONS .................................................................................................... 7
DIGITAL INPUT CHARACTERISTICS ................................ ... .... ... ... ... ... .... ... ... ... .... ... ...........................8
DIGITAL INTERFACE SPECIFICATIONS ............................................................................................. 8
TRANSMITTER CHARACTERISTICS .................................................................................................. 8
SWITCHING CHARACTERISTICS .................................................. ... ... .... ... ... ..................................... 8
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS .............................................................. 9
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE ............................................. 10
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE ............................................... 11
2. TYPICAL CONNECTION DIAGRAM ................................................................................................... 12
3. GENERAL DESCRIPTION ................................................................................................................... 13
4. DATA I/O FLOW AND CLOCKING OPTIONS ..................................................................................... 14
5. SAMPLE RATE CONVERTER (SRC) .................................................................................................. 18
5.1 Dither ............................................................................................................................................. 18
5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register ..................................................... 18
6. THREE-WIRE SERIAL AUDIO PORTS ...............................................................................................19
7. AES3 TRANSMITTER AND RECEIVER .............................................................................................. 22
7.1 AES3 Receiver ............................................................................................................................... 22
7.1.1 PLL, Jitter Attenuation, and Varispeed .................................................................................. 22
7.1.2 OMCK Out On RMCK ........................................................................................................... 22
7.1.3 Error Reporting and Hold Function ............................... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ......22
7.1.4 Channel Status Data Handling .............. .................................................................... ............23
7.1.5 User Data Handling .. ... ... .... ... ... ... ... .... ... ....................................... ... ... ... .... ... ... ... ... .... ............ 23
7.1.6 Non-Audio Auto Detection ..................... ....................................... ................................... ...... 24
7.2 AES3 Transmitter ........................................................................................................................... 24
7.2.1 Transmitted Frame and Channel Status Boundary Timing ................................................... 24
7.2.2 TXN and TXP Drivers ............................................................................................................ 25
7.3 Mono Mode Operation ................................................................................................................... 25
8. AES3 TRANSMITTER AND RECEIVER .............................................................................................. 28
8.1 Sample Rate Converter ................................................................................................................. 28
8.2 Non-SRC Delay ............................................................................................................................. 29
9. CONTROL PORT DESCRIPTION AND TIMING ................................................................................. 30
9.1 SPI Mode ....................................................................................................................................... 30
9.2 I²C Mode ........................................................................................................................................ 31
9.3 Interrupts ........................................................................................................................................ 31
10. CONTROL PORT REGISTER BIT DEFINITIONS ............................................................................. 32
10.1 Memory Address Pointer (MAP) ......................................................... ... ... ... .... ... ... ... ... .... ... ....
10.2 Miscellaneous Control 1 (01h) ..................................................... ... .... ... ... ... .... ... ... ... ... .... ... ......... 34
10.3 Miscellaneous Control 2 (02h) ..................................................... ... .... ... ... ... .... ... ... ... ... .... ... ......... 35
10.4 Data Flow Control (03h) ............................................................................................................... 36
10.5 Clock Source Control (04h) .......................... .......................................... ... ... .... ... ... ...................... 37
10.6 Serial Audio Input Port Data Format (05h) ....................................................................... ............ 38
10.7 Serial Audio Output Port Data Format (06h) ................................................................................39
10.8 Interrupt 1 Register Status (07h) (Read Only) .............................................................................40
10.9 Interrupt Register 2 Status (08h) (Read Only) .............................................................................41
10.10 Interrupt 1 Register Mask (09h) ................................................................................................. 41
10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh) ............................... ...................... 41
10.12 Interrupt 2 Register Mask (0Ch) ................................................................................................. 42
CS8420
..... 32
2 DS245F4
CS8420
10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh) ..................................................... 42
10.14 Receiver Channel Status (0Fh) (Read Only) ............................................................................. 43
10.15 Receiver Error (10h) (Read Only) .............................................................................................. 44
10.16 Receiver Error Mask (11h) ......................................................................................................... 45
10.17 Channel Status Data Buffer Control (12h) .................................................................................45
10.18 User Data Buffer Control (13h) .................................................................................................. 46
10.19 Sample Rate Ratio (1Eh) (Read Only) ................................................................. ...................... 47
10.20 C-Bit or U-Bit Data Buffer (20h - 37h) ........................................................................................ 47
10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ............................................................... 47
11. SYSTEM AND APPLICATIONS ISSUES ........................................................................................... 48
11.1 Reset, Power Down and Start-up Options ................................................................................... 48
11.2 Transmitter Startup ...................................................................................................................... 48
11.3 SRC Invalid State ......................................................................................................................... 49
11.4 C/U Buffer Data Corruption .......................... ............................................. ................................... 49
11.5 Block-Mode U-Data D-to-E Buffer Transfers ............................................................................... 50
11.6 ID Code and Revision Code ........................................................................................................ 50
11.7 Power Supply, Grounding, and PCB layout ................................................................................. 50
11.8 Synchronization of Multiple CS8420s .......................................................................................... 50
11.9 Extended Range Sample Rate Conversion ........................................ ... ...................................... 50
12. SOFTWARE MODE - PIN DESCRIPTION ......................................................................................... 51
13. HARDWARE MODES .................. .... ... ... ... ... ....................................... ... .... ... ... ... .... ... ... ... ................... 55
13.1 Overall Description ....................................................................................................................... 55
13.1.1 Hardware Mode Definitions ................................................................................................. 55
13.1.2 Serial Audio Port Formats ................................................................................................... 55
13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input) ............................................ 56
13.2.1 Pin Description - Hardware Mode 1 .................................................................................... 57
13.3 Hardware Mode 2 Description ..................................................................................................... 59
13.3.1 Pin Description - Hardware Mode 2 .................................................................................... 61
13.4 Hardware Mode 3 Description ..................................................................................................... 63
13.4.1 Pin Description - Hardware Mode 3 .................................................................................... 65
13.5 Hardware Mode 4 Description ..................................................................................................... 67
13.5.1 Pin Description - Hardware Mode 4 .................................................................................... 69
13.6 Hardware Mode 5 Description ..................................................................................................... 71
13.6.1 Pin Description - Hardware Mode 5 .................................................................................... 72
13.7 Hardware Mode 6 Description ..............................................................................................
13.7.1 Pin Description - Hardware Mode 6 .................................................................................... 76
14. EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPONENTS ................ 78
14.1 AES3 Transmitter External Components ............................ ......................................................... 78
14.2 AES3 Receiver External Components ......................................................... ................................79
14.3 Isolating Transformer Requirements ............................................................................................ 80
15. CHANNEL STATUS AND USER DATA BUFFER MANAG EMENT ......................... ...................... ... 81
15.1 AES3 Channel Status(C) Bit Management .................................................................................. 81
15.1.1 Manually Accessing the E Buffer .........................................................................................82
15.1.2 Reserving the First 5 Bytes in the E Buffer ......................................................................... 83
15.1.3 Serial Copy Management System (SCMS) ......................................................................... 83
15.1.4 Channel Status Data E Buffer Access ................................................................................. 83
15.1.5 One-Byte Mode ............................................................. ... ... ... .... ... ... ... .... ............................ 84
15.1.6 Two-Byte Mode ............................................................. ... ... ... .... ... ...................................... 84
15.2 AES3 User (U) Bit Management .................................................................................................. 84
15.2.1 Mode 1: Transmit All Zeros ................................................................................................. 84
15.2.2 Mode 2: Block Mode .................................. .... ... ... ... .... ... ... ... ... ............................................. 84
15.2.3 IEC60958 Recommended U Data Format for Consumer Applications ............................... 85
15.2.4 Mode (3): Reserved ................................... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ...................... 85
15.2.5 Mode (4): IEC Consumer B ................................................................................................. 85
....... 74
DS245F4 3
16. PLL FILTER ........................................................................................................................................ 87
16.1 General ........................................................ ....................................... ... ... ... .... ... ......................... 87
16.2 External Filter Components ................................................................ ... ... ... .... ............................ 87
16.2.1 General ................................................................................................................................ 87
16.2.2 Capacitor Selection ............................................................................................................. 88
16.2.3 Circuit Board Layout ............................................................................................................ 88
16.3 Component Value Selection ........................................................................................................ 88
16.3.1 Identifying the Part Revision ................................................................................................ 88
16.3.2 Locking to the RXP/RXN Receiver Inputs ........................................................................... 89
16.3.3 Locking to the ILRCK Input ................................................................................................. 89
16.3.4 Jitter Tolerance .......................... ... ....... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ................... 90
16.3.5 Jitter Attenuation ................................................................................................................. 90
17. PARAMETER DEFINITIONS .............................................................................................................. 91
18. PACKAGE DIMENSIONS .................................................................................................................. 92
THERMAL CHARACTERISTICS AND SPECIFICATIONS ................................................................. 92
19. ORDERING INFORMATION .............................................................................................................. 93
20. REVISION HISTORY .......................................................................................................................... 93
LIST OF FIGURES
Figure 1.Audio Port Master Mode Timing ................................................................................................... 9
Figure 2.Audio Port Slave Mode and Data Input Timing .............................. .......................................... ..... 9
Figure 3.SPI Mode Timing ........................................................................................................................ 10
Figure 4.I²C Mode Timing ......................................................................................................................... 11
Figure 5.Recommended Connection Diagram for Software Mode ........................................................... 12
Figure 6.Software Mode Audio Data Flow Switching Options ............. ... ... ... .... ... ... ... .... ............................ 14
Figure 7.CS8420 Clock Routing ............................. ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ................................ 14
Figure 8.Serial Audio Input, using PLL, SRC Enabled .............................................................................. 16
Figure 9.Serial Audio Input, No PLL, SRC Enabled .................. .......................................... ...................... 16
Figure 10.AES3 Input, SRC Enabled ..... ... ... ... ... .... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ...................................... 16
Figure 11.Serial Audio Input, AES3 Input Clock Source, SRC Enabled ...................................................16
Figure 12.Serial Audio Input, SRC Output Clocked by AES3 Recovered Clock ....................................... 16
Figure 13.AES3 Input, SRC to Serial Audio Output, Serial Audio Input to AES3 Out ............................... 16
Figure 14.AES3 Input to Serial Audio Output, Serial Audio Input to AES3 Out, No SRC ......................... 17
Figure 15.AES3 Input to Serial Audio Output Only ................................................................................... 17
Figure 16.Input Serial Port to AES3 Transmitter ....................................................................................... 17
Figure 17.Serial Audio Input Example Formats ........................................................................................ 20
Figure 18.Serial Audio Output Example Formats ...................................................................................... 21
Figure 19.AES3 Receiver Timing for C & U Pin Output Data ................................................................... 23
Figure 20.AES3 Transmitter Timing for C, U and V Pin Input Data .......................................................... 26
Figure 21.Mono Mode Operation Compared to Normal Stereo Operation ............................................... 27
Figure 22.Control Port Timing in SPI Mode .............................................................................................. 30
Figure 23.Control Port Timing in I²C Mode ............................................................................................... 31
Figure 24.Hardware Mode 1 - Default Data Flow, AES3 Input ................................................................. 56
Figure 25.Hardware Mode 2 - Default Data Flow, Serial Audio Input .... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ... 59
Figure 26.Hardware Mode 3 - Transceive Data Flow, with SRC .............................................................. 63
Figure 27.Hardware Mode 4 - Transceive Data Flow, Without SRC ......................................................... 67
Figure 28.Hardware Mode 5 - AES3 Receiver Only .................................................................................71
Figure 29.Hardware Mode 6 - AES3 Transmitter Only ............................................................................. 74
Figure 30.Professional Output Circuit ....................................................................................................... 78
Figure 31.Consumer Output Circuit ............................. ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... ... ............. 78
Figure 32.TTL/CMOS Output Circuit ......................................................................................................... 79
Figure 33.Professional Input Circuit .......................................................................................................... 79
Figure 34.Transformerless Professional Input Circuit ......................................... ... ... .... ............................ 79
CS8420
4 DS245F4
Figure 35.Consumer Input Circuit ............................................................................................................. 80
Figure 36.TTL/CMOS Input Circuit ............................................................................................................ 80
Figure 37.Channel Status Data Buffer Structure ....................................................................................... 81
Figure 38.Channel Status Block Handling When Fso is Not Equal to Fsi .............................. ... .... ... ... ... ... 82
Figure 39.Flowchart for Reading the E Buffer ........................................................................................... 82
Figure 40.Flowchart for Writing the E Buffer ............................................................................................. 83
Figure 41.PLL Block Diagram ................................................................................................................... 87
Figure 42.Recommended Layout Example ............................................................................................... 88
Figure 43.Jitter Tolerance Template ......................................................................................................... 90
Figure 44.Revision D Jitter Attenuation ..................................................................................................... 90
Figure 45.Revision D1 Jitter Attenuation ................................................................................................... 90
LIST OF TABLES
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN ...................... 28
Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK ........................... 28
Table 3. Non-SRC Delay ........................................................................................................................... 29
Table 4. Summary of all Bits in the Control Register Map ........................................................................ 33
Table 5. Hardware Mode Definitions ......................................................................................................... 55
Table 6. Serial Audio Output Formats Available in Hardware Mode ......................................................... 55
Table 7. Serial Audio Input Formats Available in Hardware Mode ............................................................ 55
Table 8. Hardware Mode 1 Start-Up Options ............................................................................................ 56
Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function ............................................. ... ... ... .... ... ... ... ... 60
Table 10. HW Mode 2 Serial Audio Port Format Selection ....................................................................... 60
Table 11. Hardware Mode 2 Start-Up Options ............................. .... ... ... ... ... .... ... ...................................... 60
Table 12. Hardware Mode 3 Start-Up Options ............................. .... ... ... ... ... .... ... ...................................... 64
Table 13. Hardware Mode 4 Start-Up Options ............................. .... ... ... ... ... .... ... ...................................... 68
Table 14. Hardware Mode 5 Start-Up Options ............................. .... ... ... ... ... .... ... ...................................... 71
Table 15. HW 6 COPY/C and ORIG Pin Function ....................................................................................75
Table 16. HW 6 Serial Port Format Selection ........................................................................................... 75
Table 17. Second Line Part Marking .. .... ... ... ... ... .... .......................................... ... ... ... .... ... ... ... ... ................ 88
Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz ................................................................................... 89
Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* ...... .......................................................... ................89
Table 20. Locking to the ILRCK Input ....................................................................................................... 89
CS8420
DS245F4 5
CS8420
1. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical
performance characteristics and spe cif icat ion s ar e de riv e d from measurements taken at nominal supply voltages
and T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
AGND, DGND = 0 V, all voltages with respect to 0 V.
Parameter Symbol Min Typ Max Units
Power Supply Voltage VD+, VA+ 4.75 5.0 5.25 V
Ambient Operating Temperature: Commercial Grade
Automotive Grade
T
A
-10
-40
-
-
+70
+85
°C
°C
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Max Units
Power Supply Voltage VD+, VA+ - 6.0 V
Input Current, Any Pin Except Supplies, RXP/RXN (Note 1) I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storag e Temperature T
in
in
A
stg
-±10mA
-0.3 (VD+) + 0.3 V
-55 125 °C
-65 150 °C
Notes:
1. Transient currents of up to 100 mA will not cause SCR latch-up.
6 DS245F4
CS8420
PERFORMANCE SPECIFICATIONS
Parameter* Symbol Min Typ Max Units
Dynamic Range 120 128 - dB
Input Sample Rate (serial input port) Fsi 8 - 108 kHz
Output Sample Rate Fso 8 - 108 kHz
Output to Input Sample Rate Ratio 0.33 - 3
Total Harmonic Distortion + Noise
1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7
1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3
10 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7
10 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3
Peak idle channel noise component - - -140 dBFS
Resolution 16 - 24 bits
Gain Error -0.12 - 0 dB
THD+N
-
-
-
-
-
-
-
-
-117
-112
-110
-107
dB
dB
dB
dB
DIGITAL FILTER CHARACTERISTICS
Parameter* Symbol Min Typ Max Units
Passband Upsampling
Downsampling
Passband Ripple - - ±0.007 dB
Stopband (Downsampling ) 0.5465*Fso - Fsi/2 Hz
Stopband Attenuation 110 - - dB
Group Delay (Note 2) t
Group Delay Variation vs. Frequency Δt
Interchannel Phase Deviation - - 0.0 °
2. See “AES3 Transmitter and Receiver” on page 28.
gd
gd
0
0
- - 1.75 ms
--0.0μs
-
-
0.4535*Fsi
0.4535*Fso
DC ELECTRICAL SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters Symbol Min Typ Max Units
Power Down Mode (Note 3)
Supply Current in power down VA+
VD+
Normal Operation (Note 4)
Supply Current at 48 kHz F
Supply Current at 96 kHz F
and F
so
and F
so
si
si
VA+
VD+
VA+
VD+
-
-
-
-
-
-
20
20
3.7
66
7.0
125
-
-
-
-
-
-
Hz
Hz
μA
μA
mA
mA
mA
mA
3. Power Down Mode is defined as RST
4. Normal operation is defined as RST = HI.
DS245F4 7
= LO with all clocks and data lines held static.
DIGITAL INPUT CHARACTERISTICS
Parameters Symbol Min Typ Max Units
Input Leakage Current I
Differential Input Voltage, RXP to RXN V
in
TH
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters Symbol Min Max Units
High-Level Output Voltage (I
Low-Level Output Voltage (I
High-Level Output Voltage (I
Low-Level Output Voltage (I
= -3.2 mA), except TXP/TXN V
OH
= 3.2 mA), except TXP/TXN V
OH
= -21 mA), TXP, TXN (VD+) - 0.7 - V
OH
= 21 mA), TXP, TXN - 0.7 V
OH
High-Level Input Voltage, except RXP, RXN V
Low-Level Input Voltage, except RXP, RXN V
TRANSMITTER CHARACTERISTICS
Parameters Symbol Typ Units
TXP Output Resistance R
TXN Output Resistance R
OH
OL
IH
IL
-±10±15μA
200 - - mVpp
(VD+) - 1.0 - V
-0.4V
2.0 (VD+) + 0.3 V
-0.3 0.8 V
TXP
TXN
25 Ω
25 Ω
CS8420
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
pin Low Pulse Width 200 - - μs
RST
OMCK Frequency for OMCK = 512 * Fso 4.096 - 55.3 MHz
OMCK Low and High Width for OMCK = 512 * Fso 8.2 - - ns
OMCK Frequency for OMCK = 384 * Fso 3.072 - 41.5 MHz
OMCK Low and High Width for OMCK = 384 * Fso 12.3 - - ns
OMCK Frequency for OMCK = 256 * Fso 2.048 - 27.7 MHz
OMCK Low and High Width for OMCK = 256 * Fso 16.4 - - ns
PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz
RMCK output jitter (Note 5) -200-ps RMS
RMCK output duty cycle 40 50 60 %
RMCK Input Frequency (Note 6) 2.048 - 27.7 MHz
RMCK Input Low and High Width (Note 6) 16.4 - - ns
AES3 Transmitter Output Jitter - - 1 ns
5. Cycle-to-cycle jitter using 32-96 kHz external PLL components.
6. PLL is bypassed (RXD1:0 bits in the Clock Source Control register set to 10b), clock is input to the RMCK
pin.
8 DS245F4
CS8420
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid (Note 7) t
SDIN Setup Time Before ISCLK Active Edge (Note 7) t
SDIN Hold Time After ISCLK Active Edge (Note 7) t
dpd
ds
dh
Master Mode
O/RMCK to I/OSCLK active edge delay (Note 7, 8) t
O/RMCK to I/OLRCK delay (Note 9) t
smd
lmd
I/OSCLK and I/OLRCK Duty Cycle - 50 - %
Slave Mode
I/OSCLK Period (Note 10) t
I/OSCLK Input Low Width t
I/OSCLK Input High Width t
I/OSCLK Active Edge to I/OLRCK Edge
sckw
sckl
sckh
t
lrckd
(Note 7, 9, 11)
I/OLRCK Edge Setup Before I/OSCLK Active Edge
t
lrcks
(Note 7, 9, 12)
- - 25 ns
20 - - ns
20 - - ns
0 - 16 ns
0 - 17 ns
36 - - ns
14 - - ns
14 - - ns
20 - - ns
20 - - ns
7. The active edges of ISCLK and OSCLK are pro gram m ab le .
8. When OSCLK, OLRCK, ISCLK, and ILRCK are derived from OMCK they are clocked from its r ising edge.
When these signals are derived from RMCK, they are clocked from its falling edge.
9. The polarity of ILRCK and OLRCK is programmable.
10. No more than 128 SCLK per frame.
11. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
has changed.
12. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.
ISC L K
OSCLK
(outpu t)
ILRCK
OLRCK
(outpu t)
RMCK
(outpu t)
RMCK
(outpu t)
OMCK
(input)
t
smd
Hard ware Mod e
Software Mode
t
lm d
ILRCK
OLRCK
(input)
ISCLK
OSCLK
(input)
SDIN
SDOUT
t
lrckd lrcks
t
t
sckh
t
ds
t
dh
t
sckw
t
sckl
t
dpd
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
DS245F4 9
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI™ MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 13) f
CS
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 14) t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 15) t
Fall Time of CCLK and CDIN (Note 15) t
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
13. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK freq uency should be less than 128 Fso an d
less than 128 Fsi. This is dictated by the timing requirements necessary to access the Channel Status and
User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. The
minimum allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz
should be safe for all possible conditions.
14. Data must be held for sufficient time to bridge the transition time of CCLK.
15. For f
< 1 MHz.
sck
0-6.0MHz
1.0 - - μs
20 - - ns
66 - - ns
66 - - ns
40 - - ns
18 - - ns
- - 45 ns
- - 25 ns
- - 25 ns
--100ns
--100ns
CS8420
CS
t
css
t
scl
sch
t
csh
t
CCLK
t
r2
t
f2
CDIN
t
dsu
t
dh
t
pd
CDOUT
Figure 3. SPI Mode Timing
10 DS245F4
CS8420
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C® MODE
Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
SCL Clock Frequency fscl - - 100 kHz
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 16) t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
buf
hdst
low
high
sust
hdd
sud
r
f
susp
16. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
Repeated
Stop Start
Start
4.7 - - μs
4.0 - - μs
4.7 - - μs
4.0 - - μs
4.7 - - μs
0--μs
250 - - ns
- - 25 ns
- - 25 ns
4.7 - - μs
Stop
SDA
SCL
t
buf
t
hdst
t
low
t
high
t
hdd
Figure 4. I²C Mode Timing
t
sud
t
sust
t
hdst
t
f
t
r
t
susp
DS245F4 11
2. TYPICAL CONNECTION DIAGRAM
Ferrite *
Bead
0.1 Fμ
0.1 Fμ
VA+ VD+
RXP
RXN
CS8420
AES3/
SPDIF
Source
+5V
Analog
Supply *
Cable
Termination
TXP
TXN
+5V
Digital
Supply
Cable
Interface
CS8420
AES3/
SPDIF
Equipment
3-wire Serial
Audio Source
Clock Source
and Control
47kΩ
Hardware
Control
To other
CS8420's
ILRCK
ISCLK
SDIN
RMCK
OMCK
EMPH
RERR
RST
TCBL
SDA/CDOUT
SCL/CCLK
AD1/CDIN
/AD2
RFILT
CFILT CRIP
OLRCK
OSCLK
SDOUT
AD0/CS
INT
H/S
DGNDFILTAGND
3-wire Serial
Audio Input
Device
Microcontroller
U
* A separate analog supply is only necessary in applications where
RMCK is used for a jitter sensitive task. For applications where
RMCK is not used for a jitter sensitive task, connect VA+ to VD+
via a ferrite bead. Keep the decoupling capacitor between VA+
and AGND.
Figure 5. Recommended Connection Diagram for Software Mode
12 DS245F4
CS8420
3. GENERAL DESCRIPTION
The CS8420 is a fully asynchronous sample rate converter plus AES3 transceiver intended to be used in digital audio systems. Such systems include digital mixing consoles, effects processors, tape recorders, and computer multimedia systems. The CS8420 is intended for 16-, 20-, and 24-bit applications where the input sample rate is
unknown, or is known to be asynchronous to the system sample rate.
On the input side of the CS8420, AES3 or 3-wire serial format can be chosen. The output side produces both AES3
and 3-wire serial format. An I²C/SPI-compatible microcon troller interface allows full block processing of channel status and user data via block reads from the incoming AES3 data stream and block writes to the outgoing AES3 data
stream. The user can also access information decoded from the input AES3 data stream, such as the presence of
non-audio data and pre-emphasis, as well as control the various modes of the device. For users who prefer not to
use a micro-controller, six hardware modes have been provide d and documented towards the end of this data sheet.
In these modes, flexibility is limited, with pins providing some programmability.
When used for AES3-input/AES3-output applications, the CS8420 can automatically transceive user data that conforms to the IEC60958-recommended format. The CS8420 also allows access to the relevant bits in the AES3 data
stream to comply with the serial copy management system (SCMS).
The diagram on the cover of this data sheet shows the main functional blocks of the CS8420. Figure 5 shows the
supply and external connections to the device.
Familiarity with the AES3 and IEC60958 specifications are assumed throughout this document. Application Note 22:
Overview of Digital Audio Interface Data Structures, contains a tutorial on digital audio specifications. The paper An
Understanding and Implementation of the SCMS Serial Copy Management System for Dig ita l Audio Tra nsmissi on,
by Clif Sanchez, is an excellent tutorial on SCMS. It may be obtained from Cirrus Logic, Inc., or from the AES.
To guarantee system compliance, the proper standards documents should be obtained. The latest AES3 standard
should be obtained from the Audio Engineering So ciety (ANSI), the latest IEC6 0958 standard from the Inte rnational
Electrotechnical Commission and the latest EIAJ CP-1201 standard from the Japanese Electronics Bureau.
DS245F4 13
CS8420
T
4. DATA I/O FLOW AND CLOCKING OPTIONS
The CS8420 can be configured for nine connectivity alternatives, referred to as data flows. Each data flow has an
associated clocking set-up. Figure 6 shows the data flow switching, along with the control register bits which control
the switches. This drawing only shows the audio data paths for simplicity. Figure 7 shows the internal clock routing
and the associated control register bits. The clock routing constraints determine which data routing options are actually usable.
SPD1-0
ILRCK
ISCLK
SDIN
RXN
RXP
Serial
Audio
SRCD
Input
Sample
Rate
Converter
AES3
Receiver
AES3
Encoder
TXD1-0
Figure 6. Software Mode Audio Data Flow Switching Options
Serial
Audio
Output
TXOFFAESBP
OLRCK
OSCLK
SDOU
TXP
TXN
SDIN
ISCLK
ILRCK
RXP
SERIAL
AUDIO
INPUT
0
MUX
1
MUX
RXD0
01
PLL
SIMS
RMCKF
÷
SWCLK
UNLOCK
0
MUX
1
RXD1
MUX
01
SAMPLE
RATE
CONVERTER
INC
CHANNEL
STATUS
MEMORY
USER
BIT
MEMORY
MUX
1
CLK[1:0]
0
SERIAL
AUDIO
OUTPUT
AES3
TRANSMIT
OUTC
÷
SDOUT
OSCLK
OLRCK
TXN
TXP
OMCKRMCK
*Note: When SWCLK mode is enabled, signal input on OMCK is only output thr ough RM CK an d not
routed back through the RXD1 multiplexer; RMCK is not bi-directional in this mode.
Figure 7. CS8420 Clock Routing
14 DS245F4
CS8420
The AESBP switch allows a TTL level, bi-phase mark-encoded data stream connected to RXP to be routed to the
TXP and TXN pin drivers. The TXOFF switch causes the TXP and TXN outputs to be driven to ground
In modes including the SRC function, there are two audio-data-related clock domains. One domain includes the input side of SRC, plus the attached data source. The second domain includes the output side of the SRC, plus any
attached output ports.
There are two possible clock sources. The first known as the recovered clock, is the output of a PLL, and is connected to the RCMK pin. The input to the PLL can be either the incoming AES3 data stream or the ILRCK word rate
clock from the serial audio input port. The second clock is input via the OMCK pin , and would normally be a cr ystalderived stable clock. The Clock Source Control Register bits determine which clock is connected to which domain.
By studying the following drawings, and appropriately setting the Data Flow Control and Clock Source Control register bits, the CS8420 can be configured to fit a variety of application requirements.
The following drawings illustrate the possible valid data flows. The audio data flow is indicated by the thin lines; the
clock routing is indicated by the bold lines. The register settings for the Data Flow Control register and the Clock
Source Register are also shown for each data flow. Some of the register settings may appear to be not relevant to
the particular data flow in question, but have been assigned a particular state. This is done to minimize power consumption. The AESBP data path from the RXP pin to the AES3 output drivers, and the TXOFF control, have been
omitted for clarity, but are present and functional in all modes where the AES3 transmitter is in use.
Figures 8 and 9 show audio data enterin g via the serial audio input p ort, then passing throug h the sample rate converter, and then output both to the serial audio output port and to the AES3 transmitter. Figure 8 shows the PLL
recovering the input clock from ILRCK word clock. Figure 9 shows using a direct 256*Fsi clock input via the RMCK
pin, instead of the PLL.
Figure 10 shows audio data entering via the AES3 Receiver. The PLL locks onto the pre-ambles in the incoming
audio stream, and generates a 256*Fsi clock. The rate-converted data is the n output via the serial au dio output port
and via the AES3 transmitter.
Figure 11 shows the same data flow as Figure 8. The input clock is derived from an incoming AES3 data stream.
The incoming data must be synchronous to the AES3 data stream.
Figure 12 shows the same data flow as Figure 8. The input data must be synchronous to OMCK. The output data
is clocked by the recovered PLL clock from an AES3 input stream. This may be used to implement a “house sync”
architecture.
Figure 8 shows audio data entering via the AES3 receiver, passing through the sample rate converter, and then ex-
iting via the serial audio output port. Synchronous audio data may then be input via the serial audio input port and
output via the AES3 transmitter.
Figure 14 is the same as Figure 13, but without the sample rate converter. The whole data path is clocked via the
PLL generated recovered clock.
Figure 15 illustrates a standard AES3 receiver function, with no rate conversion.
Figure 16 shows a standard AES3 transmitter function, with no rate conversion.
DS245F4 15
CS8420
T
0
00
T
0
0
T
0
T
0
0
N
0
T
0
0
SDIN
ISCLK
ILRCK
Serial
Audio
Input
PLL
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
RMCK OMCK
Clock Source Control BitsData Flow Control Bits
00
00
Serial
Audio
Output
AES3
Encoder
&Driver
OUTC:
INC:
RXD1-0:
OLRCK
OSCLK
SDOU
TXP
TXN
0
0
SDIN
ISCLK
ILRCK
Serial
Audio
Input
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
RMCK OMCK
00
00
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Serial
Audio
Output
AES3
Encoder
&Driver
0
0
1
OLRCK
OSCLK
SDOU
TXP
TXN
Figure 8. Serial Audio Input, using PLL, SRC Enabled Figure 9. Serial Audi o Input, No PLL, SRC Enabled
RXN
RXP
AES3
Rx &
Decode
PLL
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
RMCK OMCK
Clock Source Control BitsDataFlow Control Bits
00
00
1
Serial
Audio
Output
AES3
Encoder
&Driver
OUTC:
INC:
RXD1-0:
OLRCK
OSCLK
SDOU
TXP
TXN
0
0
1
SDIN
ISCLK
ILRCK
RXN
RXP
Serial
Audio
Input
AES3
Rx
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
PLL
RMCK OMCK
00
00
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Serial
Audio
Output
AES3
Encoder
&Driver
0
0
OLRCK
OSCLK
SDOU
TXP
TXN
1
Figure 10. AES3 Input, SRC Enabled Figure 11. Serial Audio Input, AES3 Input Clock Source ,
ILRCK
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Serial
Audio
Input
ISCLKSDIN
AES3
Encoder
&Driver
0
0
1
TXP
TX
SDIN
ISCLK
ILRCK
Serial
Audio
Input
TXD1-0:
SPD1-0:
SRCD:
Sample
Rate
Converter
00
00
PLL
AES3
Rx
RXP RXN
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Serial
Audio
Output
AES3
Encoder
&Driver
RMCKOMCK
OLRCK
OSCLK
SDOU
TXP
TXN
1
1
1
Figure 12. Serial Audio Input, SRC Output Clocked by
AES3 Recovered Clock
OLRCKOSCLKSDOUT
Serial
Audio
Output
AES3
RXN
RXP
Sample
Rx &
Rate
Decode
Converter
PLL
RMCK OMCK
TXD1-0:
SPD1-0:
SRCD:
01
00
1
Figure 13. AES3 Input, SRC to Serial Audio Output, Serial
Audio Input to AES3 Out
16 DS245F4
CS8420
N
0
0
T
N
0
00
ISCLKSDIN
AES3
Encoder
&Driver
1
0
1
ILRCK
TXP
TX
RXN
RXP
AES3
Rx &
Decode
PLL
TXD1-0:
SPD1-0:
SRCD:
RMCK
01
10
OLRCKOSCLKSDOUT
Serial
Audio
Output
Serial
Audio
Input
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Figure 14. AES3 Input to Serial Audio Output, Serial Au-
dio Input to AES3 Out, No SRC
SDIN
ISCLK
ILRCK
Serial
Audio
Input
AES3
Encoder
&Driver
TXP
TX
RXN
RXP
AES3
Rx &
Decode
PLL
TXD1-0:
SPD1-0:
SRCD:
TXOFF:
RMCK
10
10
0
1
Clock Source Control BitsData Flow Control Bits
OUTC:
INC:
RXD1-0:
Serial
Audio
Output
1
0
01
OLRCK
OSCLK
SDOU
Figure 15. AES3 Input to Serial Audio Output Only
OMCK
Clock Source Control BitsData Flow Control Bits
TXD1-0:
SPD1-0:
SRCD:
01
01
OUTC:
INC:
RXD1-0:
0
1
Figure 16. Input Serial Port to AES3 Transmitter
DS245F4 17
CS8420
5. SAMPLE RATE CONVERTER (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to very high rate
and then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. The filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample
rates are greater than 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is
automatically band limited to avoid aliasing products in th e o utput. Careful design ensure s minim um ripp le a nd distortion products are added to the incoming signal. The SRC also determines the ratio between t he incoming and
outgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little
impact on the dynamic performance of the rate converter and has no influence on the output clock.
5.1 Dither
When using the AES3 input, and when using the serial audio input port in Left-Justified and I²S modes, all
input data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24
bits should have been done using an appropriate dither p rocess. If the serial audio input port is used to feed
the SRC, and the port is in Right-Justified mode, then the input data will be truncated to the SIRES bit setting
value. If SIRES bits are set to 16 or 20 bits, and the input data is 24 bits wide, truncation distortion will occur.
Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (say 16 instead of 20), the input words will be truncated, causing truncation distortion at low levels. In summary, there
is no dithering mechanism on the input side of the CS8 420, and care must be ta ken to ensure th at no truncation occurs.
Dithering is used internally where appropriate inside the SRC block.
The output side of the SRC can be set to 16, 20, or 24 bits. Optional dithering can be applied, and is auto-
matically scaled to the selected output word length. This dither is not correlated between left and right channels. It is recommended that the dither control bit be left in its default ON state.
5.2 SRC Locking, Varispeed and the Sample Rate Ratio Register
The SRC calculates the ratio between the input sample ra te and the output samp le rate and uses this information to set up various parameters inside the SRC block. The SRC takes some time to make this calculation. For a worst case 3:1 to 1:3 input sample rate transition, the SRC will take 9400/Fso to settle (195 ms
at Fso of 48 kHz). For a power-up situation, the SRC will start from 1:1; the worst case time becomes
8300/Fso (172 ms at Fso of 48 kHz).
If the PLL is in use (either AES3 or serial input port), the worst case locking time for the PLL and the SRC
is the sum of each locking time.
If Fsi is changing, for example in a varispeed application, the REUNLOCK interrupt will occur, and the SRC
will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data,
but at increased distortion levels. Once the incoming sample rate is stable, the REUNLOCK interrupt will
become false, and the SRC will return to normal levels of audio quality.
The VFIFO interrupt occurs if the data buffer in the SRC overflows, which can occur if the input sample rate
changes at >10%/second.
Varispeed at Fsi slew rates approaching 10%/sec is only supported when the input is via the serial audio
input port. When using the AES3 input, high frame rate slew rates will cause the PLL to lose lock.
The sample rate ratio is also made available as a register, accessible via the control port. The upper 2 bits
of this register form the integer part of the ratio, while th e lower 6 bits for m the fractional part. Since, in many
instances Fso is known, this allows the calculation of the incoming sample rate by the host microcontroller.
18 DS245F4
CS8420
6. THREE-WIRE SERIAL AUDIO PORTS
A 3-wire serial audio input port and a 3 -wire serial au dio output port is provid ed. Each port can be adjust ed to suit
the attached device via control registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolution, left or right justification of the data relative to left/right clock, optional 1-bit cell delay
of the 1st data bit, the polarity of the bit clock and the polarity of the le ft/right clock. By setting the appropriate control
bits, many formats are possible.
Figure 17 shows a selection of common input formats, along with the control bit settings. The clocking of the input
section of the CS8420 may be derived from the incoming ILRCK word rate clock, using the on-chip PLL. Th e PLL
operation is described in the AES receiver description on page 22. In the case of use with the serial audio input port,
the PLL locks onto the leading edges of the ILRCK clock.
Figure 18 shows a selection of common output formats, along with the control bit settings. A special AES3 direct
output format is included, which allows serial output port access to the V, U, and C bits e mbedded in the serial audio
data stream. The P bit is replaced by a bit indicating the location of the start of a block. This format is only available
when the serial audio output port is being clocked by the AES3 receiver-recovered clock. Also, the received-channel
status block start signal is only available in Hardware mode 5, as the RCBL pin.
In Master mode, the left/right clock and the serial bit clock are outputs, derived from the appropriate clock dom ain
master clock.
In Slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the
appropriate master clock, but the serial bit clock can be asynchronou s and discontinuous if required. By appropri ate
phasing of the left/right clock and control of the serial clocks, multiple CS8420’s can share one serial port. The
left/right clock should be continuous, but the duty cycle does not have to be 50%, provided that enough serial clocks
are present in each phase to clock all the data bits. When in Slave mode, the serial audio output port must be set to
left-justified or I²S data.
When using the serial audio output port in Slave mode with an OLRCK input which is asynchronous to the port’s
data source, then an interrupt bit is provided to indicate when repeated or dropped samples occur.
The CS8420 allows immediate mute of the serial audio output port audio data via a control register bit.
DS245F4 19
CS8420
ILRCK
Channel A Channel B
Left
Justified
ISCLK
(In)
MSB
LSB
Channel B
I²S
SDIN
ILRCK
ISCLK
MSB LSB
Channel A
(In)
SDIN
ILRCK
MSB LSB
Channel A Channel B
MSB
LSB
Right
Justified
ISCLK
(In)
SDIN
MSB
SIMS SISF SIRES1/0 SIJUST SIDEL SISPOL SILRPOL
Left-Justified X X 00 0 0 0 0
I²S XX00+0101
Right-Justified X X XX* 1 0 0 0
X = don’t care to match format, but does need to be set to the desired setting
+ I²S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
MSB LSBLSB
MSB
MSB
* not 11 - See Serial Input Port Data Format Register Bit Descript ions for an explanatio n of the meaning of e ach bit
Figure 17. Serial Audio Input Example Formats
20 DS245F4
CS8420
Left
Justified
(Out)
I²S
(Out)
Right
Justified
(Out)
AES3
Direct
(Out)
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
Channel A Channel B
MSB
MSB
Channel A
MSB
LSB
MSB
Channel A Channel B
MSB Extended MSB Extended
Channel A
LSB
Frame 191
MSB
MSB
LSB
Channel B
MSB
LSB
LSB
Frame 0
Channel B
MSB
Channel A
MSB MSB
LSB
LSBLSB
LSB
Channel B
MSB
LSB
MSB
CUVZCUVCUVCUV
Z
SOMS SOSF SORES1/0 SOJUST SODEL SOSPOL SOLRPOL
Left-Justified X X XX* 0 0 0 0
I²S XXXX*0101
Right-Justified 1 X XX* 1 0 0 0
AES3 DirectXX110000
X = don’t care to match format, but does need to be set to the desired setting
* not 11 - See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 18. Serial Audio Output Example Formats
DS245F4 21
CS8420
7. AES3 TRANSMITTER AND RECEIVER
The CS8420 includes an AES3-type digital audio receiver and an AES3-type digital audio transmitter. A comprehensive buffering scheme provides read/write a ccess to the channel status and user da ta. This buffering scheme is
described in “Channel Status and User Data Buffer Management” on page 81.
7.1 A ES3 Receiver
The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF),
and EIAJ CP-1201 interface standards. The receiver consists of a differe ntial input stage, accessed via pins
RXP and RXN, a PLL based clock recovery circuit, and a decoder which separates th e audio data from the
channel status and user data.
External components are used to termin ate an d isol ate the incoming data cables from the CS8420. These
components are detailed in “External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on
page 78.
7.1.1 PLL, Jitter Attenuation, and Varispeed
Please see “PLL Filter” on page 87 for general description of the PLL, selection of recommended PLL filter
components, and layout considerations. Figure 5 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter.
7.1.2 OMCK Out On RMCK
A special mode is available that allows the clock that is being input through the OMCK pin to be output
through the RMCK pin. This feature is controlled by the SWCLK bit in register 4 of the control registers.
When the PLL loses lock, the frequency of the VCO dro ps to 300 kHz. The SWCLK function allows the
clock from RMCK to be used as a clock in the system without any disrup tio n when inp ut is remo ve d from
the Receiver.
7.1.3 Error Reporting and Hold Function
While decoding the incoming AES3 data stream, the CS84 20 can identify several kinds of error, indicated
in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3
data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude
of the eye pattern opening, indicating a link that is close to generating errors. The BIP (bi-phase) err or bit
indicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity error.
The error bits are “sticky” - they are set on the first occurrence of the associated error and will remain set
until the user reads the register via the control port. This enables the register to log all unmasked errors
that occurred since the last time the register was read.
The Receiver Error Mask register allows masking of individual errors. The bits in this register serve as
masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will be reported in the receiver error register, will affect
the RERR pin, will invoke the occurrence of a RERR interrupt, and will affect the current audio sample
according to the status of the HOLD bits. The HOLD bits allow a choice of holding the previous sample,
replacing the current sample with zer o (mute ), or do no t chang e the curr ent audio sam ple. If a mask bit is
set to 0, the error is considered masked, meaning that its occurrence will not be reported in the receiver
error register, will not induce a pulse on RERR or generate a RERR interrupt, and will not affect the current
audio sample. The QCRC and CCRC errors do not affect the current audio sample, even if unmasked.
22 DS245F4
7.1.4 Channel Status Data Handling
g
The first 2 bytes of the Channel Status block are decoded into the Receiver Channel Status register. The
setting of the CHS bit in the Channel Status Data Buffer Control register determin es whether the channel
status decodes are from the A channel (CHS = 0) or B channel (CHS = 1).
The PRO (professional) bit is extracted directly. Also, for consumer data, the COPY (copyright) bit is extracted, and the category code and L bits a re dec oded to dete rmine SCMS status, indica ted by the ORIG
(original) bit. Finally, the AUDIO
Non-Audio Auto Detection section below.
bit is extracted, and used to set an AUDIO indicator, as described in the
CS8420
If 50/15 µs pre-emphasis is detected, then this is reflected in the state of the EMPH
The encoded sample word length channel status bits are decoded according to AES3-1992 or IEC 60958.
If the AES3 receiver is the data source for the SRC, then the SRC audio input data is truncated according
to the channel status word length settings. Audio data routed to the serial audio output port is unaffected
by the word length settings; all 24 bits are passed on as received.
“Channel Status and User Data Buffer Management” on pag e 81 describes the overall handling of CS and
U data.
7.1.5 User Data Handling
The incoming user data is bu ffered in a us er-acc essible buffer. Various automatic modes of re-transmitting received U data are provided. “Channel Status and User Data Buffer Management” on page 81 describes the overall handling of CS and U data.
Received U data may also be output to the U pin, under the control of a control register bit. Depending on
the data flow and clocking options selected, there may not be a clock available to qualify the U data output.
Figure 19 illustrates the timing.
If the incoming user data bits have been encoded as Q-channel subcode, the data is decoded and presented in 10 consecutive register locations. An interrupt may be enabled to indicate the decoding of a new
Q-channel block, which may be read via the control port.
RCBL
out
pin.
VLRCK
C, U
Output
RCBL and C output are only available in hardware mode 5.
RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames.
VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing.
VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate.
If no SRC is used, and the serial audio output port is in master mode, VLRCK = OLRCK.
If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required.
C, U transitions are ali
DS245F4 23
ned within 1% of VLRCKperiod to VLRCK edges
Figure 19. AES3 Receiver Timing for C & U Pin Output Data
±
7.1.6 Non-Audio Auto Detection
Since it is possible to convey non-audio data in an AES3 data stream, it is important to know whether the
incoming AES3 data stream is digital audio or other data. This information is typically conveyed in channel
status bit 1 (AUDIO
es, such as AC-3
set. The CS8420 AES3 receiver can detect such non-audio data. This is accomplished by looking for a
96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync
code is detected, an internal AUTODETECT signal will be asserted. If no additional sync codes are detected within the next 4096 frames, AUTODETECT will be de-asserted until another sync code is detected. The AUDIO
received channel status bit 1. If non-audio data is detected, the data is still processed exactly as if it were
normal audio. It is up to the user to mute the outputs as required.
), which is extracted automatically by the CS8420. However, cer tain non-audio sou rc-
®
or MPEG encoders, may not adhere to this convention, and the bit may not be properly
bit in the Receiver Channel Status register is the logical OR of AUTODETECT and the
7.2 AES3 Transmitter
The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and
bi-phase mark-encoded. The resulting bit stream is then driven directly, or through a transformer, to an
output connector.
The transmitter is usually clocked from the output side clock domain of the sample rate converter. This
clock may be derived from the clock input pin OMCK, or from the incoming data. In data flows with no
SRC, and where OMCK is asynchronous to the data source, an interrupt bit is provided that will go high
every time a data sample is dropped or repeated.
CS8420
The channel status (C) and user channel (U) bits in the transmitted data stream are taken from storage
areas within the CS8420. The user can manipulate the contents of the internal storage with a microcontroller. The CS8420 will also run in one of several automatic modes. “Channel Status and User Data Buffer
Management” on page 81 provides detailed descriptions of each automatic mode, and describes methods
for accessing the storage areas. The transmitted user da ta can optionally be input via the U pin, under the
control of a control port registe r bit . Figure 20 shows the timing requirements for inputting U data via the
U pin.
7.2.1 Transmitted Frame and Channel Status Boundary Timing
The TCBL pin may be an input or an output, a nd is used to control or indicate the star t of transmitted channel status block boundaries.
In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame
boundaries. This may be achieved in 3 ways:
1) With TCBL configured as an input, and TCBL transitions high for >3 OMCK clocks, it will cause a frame
start, and a new channel status block start.
2) If the AES3 output comes from the AES3 input, while there is no SRC, setting TCBL as output will cause
AES3 output frame boundaries to align with AES3 input frame boundaries.
3) If the AES3 output comes from the serial audio input port while the port is in Slave mode, and TCBL is
set to output, then the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.
24 DS245F4
7.2.2 TXN and TXP Drivers
The line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Both
drivers are set to ground during reset (RST
ally under the control of a register bit. The CS8420 also allows immediate mute of the AES3 transmitter
audio data via a control register bit.
External components are used to terminate and isolat e the exter nal ca ble from the CS8 420 . These components are detailed in “External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on
page 78.
7.3 Mono Mode Operation
Currently, the AES3 standard is being updated to include options for 96-kHz sample rate operation. One
method is to double the frame rate of the current format. This results in a
96-kHz sample rate, stereo signal carried over a sing le twisted pair cable. An alternate meth od is where the
2 sub-frames in a 48-kHz frame rate AES3 signal are used to carry consecutive samples of a mono signal,
resulting in a 96-kHz sample rate stream. This allows older equipment, whose AES3 transmitters and receivers are not rated for 96-kHz frame rate operation, to handle 96-kHz sample rate information. In this
“mono mode”, 2 AES3 cables are needed for stereo data transfer. The CS8420 offers mono mode operation, both for the AES3 receiver and for the AES3 transmitter. Figure 21 shows the operation of mono mode
in comparison with normal stereo mode. The receiver and transmitter sections may be independently set to
mono mode via the MMR and MMT control bits.
CS8420
= low), when no AES3 transmit clock is provided, and option-
The receiver mono mode effectively doubles Fsi compared to the input frame rate. The clo ck outp ut on th e
RMCK pin tracks Fsi, and so is do ubled in frequency comp ared to stereo mode. In m ono mode, A and B
sub-frames are routed to the SRC inputs as consecutive samples.
When the transmitter is in mono mode, either A or B SRC consecutive outputs are routed alternately to A
and B sub-frames in the AES3 output stream. Which channel status block is transmitted is also selectable.
For the AES3 input to serial audio port output data flow, in receiver mono mode, then the receiver will run
at a frame rate of Fsi/2, and the serial audio output port will run at Fsi. Identical data will appear in both left
and right data fields on the SDOUT pin.
For the serial audio input port to AES3 transmitter data flow, in transmitter mono mode, then the input port
will run at Fso audio sample rate, while the AES3 transmitter frame rate will be at Fso/2. The data from either
consecutive left, or right, positions will be selected for transmitting in A and B sub-frames.
DS245F4 25
CS8420
TCBL
In or Out
TCBL
In or Out
VLRCK
VLRCK
VCU
Input
SDIN
Input
TXP(N)
U
Input
SDIN
Input
TXP(N)
Output
Tth
Tsetup
VCU[0] VCU[1] VCU[2] VCU[3] VCU[4]
Data [4] Data [5] Data [6] Data [7] Data [8]
Data [0] Data [1] Data [2] Data [3] Data [4]Z Y X Y X
Tth
Data [4] Data [5] Data [6] Data [7] Data [8]
*Assume MMTLR = 0
Thold
AES3 Transmitter in Stereo Mode
U[0] U[2]
Data [0]* Data [2]* Data [4]*Z Y X
Tsetup => 7.5% AES3 frame time
Thold = 0
Tth > 3 OMCK if TCBL is Input
TXP(N)
Output
*Assume MMTLR = 1
Data [1]* Data [3]* Data [5]*ZYX
AES3 Transmitter in Mono Mode
Tsetup => 15% AES3 frame time
Thold = 0
Tth > 3 OMCK if TCBL is Input
VLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing.
VLRCK duty cycle is 50%
In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate.
If the serial audio input port is in slave mode and TCBL is an output, the VLRCK=ILRCK if SILRPOL=0 and
.
VLRCK= ILRCK if SILRPOL = 1.
If the serial audio input port is in master mode and TCBL i s an input, the VLRCK=ILRCK if SILRPOL=0 and
VLRCK= ILRCK if SILRPOL = 1.
Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data
26 DS245F4
CS8420
d
C
selected
SRC
RE
STEREO MODE
96kHz stereo
96kHz frame rate
AES3
Receiver
RECEIVER
MONO MODE
96kHz mono
48kHz frame rate
AES3
Receiver
EIVER
PLL
TRANSMITTER
STEREO MODE
96kHz
Fsi
In OutAA AA
BB BB
256x96kHz
SRC
96kHz
Fso
OMCK
AES3
Transmitter
(256, 384, or 512x 96kHz)
TRANSMITTER
MONO MODE
96kHz
Fsi
*
BB BB
In OutAA AA
SRC
96kHz
Fso
MMTLR
+
AES3
Transmitter
96kHz stereo
96kHz frame rate
96kHz mono
48kHz frame rate
PLL (x2)
A & B sub-frames data are time-multiplexed
*+
into consecutive samples
RECEIVER TIMING
Frame
Incoming
AES3
A1
B1
A2
STEREO
SRC Ain
SRC Bin
A1
B1
MONO
Ain & Bin
A1
B1
256x96kHz
B2
A2
B2
A2
B2
OMCK
Consecutive samples are alternately route
to A & B sub-fames
SRC Aout
SRC Bout
Outgoing
AES3
Outgoing
AES3
A selected
Outgoing
AES3
B
(256, 384, or 512x 96kHz)
TRANSMITTER TIMING
A1
B1
STEREO
MONO
A2
B2
Frame
A1 B1
A1 A2
B1 B2
A2 B2
Frame
Figure 21. Mono Mode Operation Compared to Normal Stereo Operation
DS245F4 27
8. AES3 TRANSMITTER AND RECEIVER
8.1 Sample Rate Converter
The equation for the group delay through the sample rate converter, with th e serial ports in Master mode is:
CS8420
((input interface delay + 43) / F
The unit of delay depends on the frame rate (sample rate) F
frames. The AES transmitter, th e serial input port, and th e serial outp ut port each have an inte rface del ay
of 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the start-up uncertainty of the
logic within the part.
When using multiple parts together, it is possible to start the parts simultaneously in a fashion that minimizes
the relative group delay between the parts. When multiple parts are started together in the proper way, the
variation in signal delay through the parts is ±1.5 μs.
To start the parts simultaneously, set up each one so that the PLL will lock, with the active input port driving
both output ports. Then simultaneously enable the RUN bits in all of the parts. TCBL on o ne of the CS8420
parts should be set as an output, while the remaining TCBL pins should be set as inputs. This synchronizes
the AES transmitter on all of the parts.
Depending upon software considerations, it may be advantageous to configure the registers so that an interrupt is generated on the INT pin when lock occurs. The control logic should ei ther poll the unlock bits until
all PLL’s are locked or wait for the interrupts to indicate that all are locked, depending on which approach
you’ve chosen.
When all of the PLL’s are locked, the CS8420’s should be advance d to the next state together. Dr ive all the
serial control ports together with the same clock and data. Change the configuration in register 03h accor ding to Table 1 or Table 2.
Register
(HEX)
01 01 or 00 01 or 00
03 95 81
04 41 41
11 10 10
) + ((43 + output interface delay ± 0.5) / Fso)
si
. The AES receiver has a interf ac e delay of 2
s
Initial Value
(HEX)
Value After Advancing to the Running
State, After the PLL’s are Locked (HEX)
Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN
Register
(HEX)
01 01 or 00 01 or 00
03 8A 80
04 40 40
11 10 10
Table 2. Minimizing Group Delay Through Multiple CS8420s When Lock in g to ILRCK
28 DS245F4
Initial Value
(HEX)
Value After Advancing to the Running
State, After the PLL’s are Locked (HEX)
8.2 Non-SRC Delay
The unit of delay depends on the frame rate (sample rate) Fs. The AES receiver has a interface delay of two
frames. The AES transmitter, the serial input port, and the serial output port each have an interface delay
of 1 frame. The ± 0.5 frame delay in the second half of the equation is due to the startup uncertainty of the
logic within the part.
1. All inputs are slaves and all outputs are masters, both with respect to the outside world.
2. The inputs and outputs are synchronous to one another.
CS8420
Path Delay (in units of a frame)
RX to TX 3 ± 1/128
Serial Input to TX 2 ± 1/128
RX to Serial Output 3 ± 1/128
Serial Input to Serial Output 2 ± 1/128
Table 3. Non-SRC Delay
DS245F4 29
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