Cirrus Logic CS8416-IZ, CS8416-IS, CS8416-CZ, CS8416-CS Datasheet
CS8416
192 kHz Digital Audio Interface Receiver
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible receiver
+3.3 V Analog Supply(VA)
+3.3 V to +5.0 V Digital Interface Supply (VL)
+3.3 V Digital Supply (VD)
8:2 S/PDIF Input MUX
AES/SPDIF input pins selectable in hardware
mode
3 General Purpose Outputs (GPO) allow signal
routing
Selectable signal routing to GPO pins
S/PDIF to TX inputs selectable in hardware mode
Flexible 3-wire serial digital output port
32 kHz to 192 kHz sample frequency range
Low jitter clock recovery
Pin and microcontroller read access to Channel
Status and User data
SPI or I2C control port Software Mode and
standalone Hardware Mode
Differential cable receiver
On-chip Channel Status data buffer memories
Auto-detection of compressed audio input
streams
Decodes CD Q sub-code
OMCK System Clock Mode
General Description
The CS8416 is a monolithic CMOS device which receives and decodes one of 8 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3 interface standards. The CS8416 has a serial digital audio output port and comprehensive control ability
through a selectable control port in Software Mode or
through selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access
easy.
GPO pins may be assigned to route a variety of signals
to output pins
A low jitter clock recovery mechanism yields a very clean
recoveredclockfromtheincomingAES3stream.
Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins
for channel status data.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and automotive audio systems.
ORDERING INFORMATION
CS8416-CS 28-pin SOIC -10 to +70°C
CS8416-CZ 28-pin TSSOP -10 to +70°C
CS8416-IS 28-pin SOIC -40 to +85°C
CS8416-IZ 28-pin TSSOP -40 to +85°C
VA+ AG ND FI LT
RXN
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
Receiver
8:2
MUX
Clock &
Data
Recovery
Misc.
Control
RST
Advance Product Information
Cirrus Logic, Inc.
http://www.cirrus.com
RMCK
AES3
S/PDIF
Decod er
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
VD+
SDA/
CDOUT
CopyrightCirrus Logic, Inc. 2002
VL+ DGND
De-emphasis
Filter
C&Ubit
Data Buffer
Control
Port &
Registe rs
SCL/
AD1/
CDIN
AD0/
CS
CCLK
(All Rights Reserved)
OMCK
Serial
Audi o
Outpu t
MUX
n:3
OLRCK
OSCLK
SDOUT
GPO0
GPO1
AD2/GPO2
AUG ‘02
DS578PP2
1
TABLE OF CONTENTS
1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 5
Power and Thermal Characteristics..........................................................................................5
Absolute Maximum Ratings ...................................................................................................... 5
Digital Characteristics............................................................................................................... 6
Switching Characteristics - Serial Audio Ports.......................................................................... 7
Switching Characteristics - Control Port - SPI Mode ................................................................ 8
Switching Characteristics - Control Port- I
2 TYPICAL CONNECTION DIAGRAMS .................................................................................... 10
3 GENERAL DESCRIPTION ......................................................................................................12
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 12
4 SERIAL AUDIO OUTPUT PORT ............................................................................................. 13
4.1 Slip/Repeat Behavior ....................................................................................................... 13
4.2 AES11 Behavior .............................................................................................................. 14
5 S/PDIF RECEIVER .................................................................................................................. 16
5.1 8:2 S/PDIF Input Multiplexer ............................................................................................16
5.2 PLL, Jitter Attenuation, and Clock Switching ................................................................... 16
5.2.1 OMCK System Clock Mode ................................................................................ 17
5.2.2 PLL External Components .................................................................................. 17
5.3 Error Reporting and Hold Function .................................................................................. 17
5.4 Channel Status Data Handling ......................................................................................... 18
5.5 User Data Handling .......................................................................................................... 18
5.5.1 Non-Audio Auto-Detection .................................................................................. 18
6 CONTROL PORT DESCRIPTION AND TIMING ..................................................................... 20
6.1 SPI Mode ......................................................................................................................... 20
2
6.2 I
C Mode .......................................................................................................................... 21
6.3 General Purpose Outputs ................................................................................................ 22
6.4 Interrupts ..........................................................................................................................22
7 CONTROL PORT REGISTER SUMMARY .............................................................................23
8 CONTROL PORT REGISTER BIT DEFINITIONS ................................................................... 25
8.1 Control0 (00h)................................................................................................................... 25
8.2 Control1 (01h)................................................................................................................... 25
CS8416
2
C format................................................................. 9
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are i n development and subject to development changes. Cirrus Logic, I nc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the informati on is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant i nformation to verify, before placing orders, that information being
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pertaining to warranty, patent infringement, and limitation of liability. No responsibility i s assumed by Cirrus f or the use of this informati on, i ncludi ng use of this
information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cir rus
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An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export li cense and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies describ ed in this material is subject to the PRC Foreign
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CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (" CRITICAL APPLICATIONS") . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logi c logo desi gns are trademarks of Cirrus Logic, Inc. All other brand and product names in this d ocument may be trademarks or service marks of their respective owners.
2 DS578PP2
CS8416
8.3 Control2 (02h)................................................................................................................... 26
8.4 Control3 (03h)................................................................................................................... 26
8.5 Control4 (04h)................................................................................................................... 27
8.6 Serial Audio Data Format (05h)........................................................................................ 27
8.7 Receiver Error Mask (06h) .............................................................................................. 29
8.8 Interrupt Mask (07h) ......................................................................................................... 29
8.9 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h) ................................................ 29
8.10 Receiver Channel Status (0Ah) ..................................................................................... 30
8.11 Format Detect Status (0Bh)............................................................................................ 30
8.12 Receiver Error (0Ch) ..................................................................................................... 31
8.13 Interrupt 1 Status (0Dh) ................................................................................................. 32
8.14 Q-Channel Subcode (0Eh - 17h) .................................................................................... 32
8.15 OMCK/RMCK Ratio (18h) .............................................................................................. 33
8.16 Channel Status Registers (19h - 22h) ............................................................................ 33
8.17 IEC61937 PC/PD Burst preamble (23h - 26h)................................................................ 33
8.18 CS8416 I.D. and Version Register (7Fh)........................................................................ 33
8.19 Memory Address Pointer (MAP)..................................................................................... 34
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................ 35
10 HARDWARE MODE .............................................................................................................. 37
10.1 Serial Audio Port Formats ............................................................................................. 37
11 PIN DESCRIPTION - HARDWARE MODE ........................................................................... 38
11.1 Hardware Mode Function Selection .............................................................................. 40
11.2 Hardware Mode Settings (Defaults & Controls) ............................................................. 40
12 APPLICATIONS .................................................................................................................... 42
12.1 Reset, Power Down and Start-up .................................................................................. 42
12.2 ID Code and Revision Code .......................................................................................... 42
12.3 Power Supply, Grounding, and PCB layout ................................................................... 42
13 PACKAGE DIMENSIONS ..................................................................................................... 43
14 APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS .............. 45
14.1 AES3 Receiver External Components ........................................................................... 45
14.2 Isolating Transformer Requirements ............................................................................. 45
15 APPENDIX B: CHANNEL STATUS BUFFER MANAGEMENT .......................................... 47
15.1 AES3 Channel Status (C) Bit Management ................................................................... 47
15.2 Accessing the E buffer ................................................................................................... 47
15.2.1 Serial Copy Management System (SCMS) ....................................................... 47
DS578PP2 3
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing....................................................................................... 7
Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 7
Figure 3. SPI Mode Timing.............................................................................................................. 8
Figure 4. I2C Mode Timing.............................................................................................................. 9
Figure 5. Typical Connection Diagram - Software Mode............................................................... 10
Figure 6. Typical Connection Diagram - Hardware Mode ............................................................. 11
Figure 7. AES3 Data Format ......................................................................................................... 14
Figure 8. Serial Audio Output Example Formats........................................................................... 15
Figure 9. C/U data outputs ............................................................................................................ 19
Figure 10. De-emphasis filter ........................................................................................................ 19
Figure 11. Control Port Timing In SPI Mode .................................................................................20
Figure 12. Control Port Timing in I
Figure 13. Hardware Mode Data Flow ..........................................................................................37
Figure 14. Professional Input Circuit ............................................................................................. 46
Figure 15. Transformerless Professional Input Circuit ..................................................................46
Figure 16. Consumer Input Circuit ................................................................................................ 46
Figure 17. S/PDIF MUX Input Circuit ............................................................................................ 46
Figure 18. TTL/CMOS Input Circuit............................................................................................... 46
Figure 19. Channel Status Data Buffer Structure .......................................................................... 47
Figure 20. Flowchart for Reading the E Buffer.............................................................................. 47
CS8416
2
C Mode .................................................................................. 21
LIST OF TABLES
Table 1. Delays by Frequency Values ................................................................................................. 14
Table 2. External PLL Component Values........................................................................................... 17
Table 3. GPO Pin Configurations ........................................................................................................ 22
Table 4. Hardware Mode Serial Audio Format Select ......................................................................... 41
4 DS578PP2
1 CHARACTERISTICS AND SPECIFICATIONS
POWER AND THERMAL CHARACTERISTICS
(AGND, DGND = 0 V, all voltages with respect to ground)
Parameter Symbol Min Typ Max Unit
Power Supply Voltage
Supply Current at 48 KHz frame rate
Supply Current at 192 KHz frame rate (Note 1)
Supply Current in Power Down
Ambient Operating Temperature: ‘-CS’ & ‘-CZ’ (Note 2)
‘-IS’ & ‘-IZ’ (Note 3)
CS8416
VA+ 3.13 3.3 3.46 V
VD+ 3.13 3.3 3.46 V
VL+ 3.13 3.3 5.5 V
IA - 5.7 - mA
ID - 5.9 - mA
IL - 2.8 - mA
IA - 9.4 - mA
ID - 23 - mA
-7.8-mA
IL
IA - 10 - uA
ID - 70 - uA
IL - 10 - uA
T
A
-10°
-40°
25°
-
70°
85°
°C
Notes: 1. Assumes that no digital inputs are left floating. It is recommended that all digital inputs be driven high
or low at all times.
2. ‘-CS’ and ‘-CZ’ parts are specified to operate over -10° C to 70° C but are tested at 25° C only.
3. ‘-IS’ and ‘-IZ’ parts are tested over the full -40° C to 85° C temperature range.
ABSOLUTE MAXIMUM RATINGS
(AGND, DGND = 0 V, all voltages with respect to ground)
Parameter Symbol Min Max Unit
Power Supply Voltage VD+, VA+, VL+ - 6 Volts
Input Current, Any Pin Except Supplies
(Note 4)
Input Voltage V
Ambient Operating Temperature
Notes: 4. Transient currents of up to 100mA will not cause SCR latch-up.
I
in
in
T
A
CS8416-C
CS8416-I
-10 10 mA
-0.3 VL+.03 Volts
-10°
-40°
70°
85°
°C
°C
DS578PP2 5
CS8416
DIGITAL CHARACTERISTICS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85 °C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.5 V
Parameter Symbol Min Typ Max Units
High-Level Input Voltage except RX
Low-Level Input Voltage except RX
Low-Level Output Voltage (I
High-Level Output Voltage (I
O
O
Input hysteresis V
Input Leakage Current I
Differential Input Sensitivity RXPn to RXN0 - 150 200 mV
SWITCHING CHARACTERISTICS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.5
V, Inputs: Logic 0 = 0V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
RST/Pin Low Pulse Width 200 - - uS
PLL Clock Recovery Sample Rate Range 30 - 200 kHz
RMCK Output Jitter (Time Deviation) - - 200 ps RMS
RMCK Output Duty-Cycle 45 50 55 %
:VIH2 - (VL+)+0.3 Volts
n
:VIL-0.3 - 0.8 Volts
n
=3.2mA) V
=3.2mA) V
=20pF)
L
OL
OH
H
IN
- - 0.5 Volts
(VL+) - 1 - VL+ Volts
0.25 - 1.0 Volts
-10 - 10 uA
)
6 DS578PP2
CS8416
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(TA= 25 °C for suffixes ‘CS’ & ’CZ’, TA= -40 to 85 °C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.5
V, Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid (Note 5)t
Master Mode
RMCK to OSCLK active edge delay (Note 5)t
RMCK to OLRCK delay (Note 6)t
OSCLK and OLRCK Duty Cycle - 50 - %
Slave Mode
OSCLK Period t
OSCLK Input Low Width t
OSCLK Input High Width t
OSCLK Active Edge to OLRCK Edge (Notes 5,6,7)t
OSCLK Edge Setup Before OSCLK Active-Edge (Notes 5,6,8)t
Notes: 5. In Software mode the active edges of OSCLK are programmable.
6. In Software mode the polarity of OLRCK is programmable.
7. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
8. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
=20pF)
L
dpd
smd
lmd
sckw
sckl
sckh
lrckd
lrcks
- - 15 ns
0 - 10 ns
0 - 10 ns
36 - - ns
14 - - ns
14 - - ns
10 - - ns
10 - - ns
OSCLK
(output)
OLRCK
(output)
RMCK
(output)
t
smd
t
lmd
OLRCK
(input)
OSCLK
(input)
SDOUT
t
lrckd
t
lrcks
t
sckh
t
sckw
t
sckl
t
dpd
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
DS578PP2 7
CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = VD+ = 3.3 V ± 5%, VL+ = 3.135 to 5.5V,
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Max Unit
CCLK Clock Frequency (Note 9)f
High Time Between Transmissions
CS
CS
Falling to CCLK Edge
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 10)t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 11)
Fall Time of CCLK and CDIN (Note 11)t
=20pF)
L
t
t
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
t
r2
r2
06.0MHz
1.0 - µs
20 - ns
66 - ns
66 - ns
40 - ns
15 - ns
-50ns
-25ns
-25ns
- 100 ns
- 100 ns
Notes: 9. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status memory. Access to the
control register file can be carried out at the full 6 MHz rate. The minimum allowable input sample rate
is 32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible
conditions.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
sck
<1 MHz.
CDOUT
CS
CCLK
CDIN
t
css
t
t
sch
scl
t
r2
t
dsu
t
f2
t
dh
t
pd
t
csh
Figure 3. SPI Mode Timing
8 DS578PP2
CS8416
SWITCHING CHARACTERISTICS - CONTROL PORT- I2CFORMAT
(TA= 25° C; VA+ = VD+ = 3.3 V ± 5%, VL = 3.135 V to 5.5 V Inputs: Logic 0 = GND, Logic 1 = VL,CL=20pF)
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 12)t
SDA Setup time to SCL Rising t
Rise Time of SCL and SDA t
Fall Time SCL and SDA t
Setup Time for Stop Condition t
Notes: 12. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
- 100 kHz
4.7 - µs
4.0 - µs
4.7 - µs
4.0 - µs
4.7 - µs
10 - ns
250 - ns
-25ns
-25ns
4.7 - µs
SDA
SCL
Stop Start
t
buf
t
hdst
t
low
t
high
t
hdd
Figure 4. I2CModeTiming
t
sud
Repeated
Start
t
t
sust
hdst
Stop
t
f
t
r
t
susp
DS578PP2 9
2 TYPICAL CONNECTION DIAGRAMS
+3.3V
*
+3.3V
Analog
Supply
Ferrite
Bead
*
10 Fµ
VL+
VL+
0.1 Fµ
AES3 /
**
S/PDIF
Sources
Microcontroller SCL / CCLK
1nF
VA+
RXN
RXP0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
RXP7
AD0 / CS
AD1 / CDIN
SDA / CDOUT
RST
10 Fµ 0.1 Fµ 1nF
VD+
CS8416
VL+
SDOUT
OLRCK
OSCLK
RMCK
OMCK
GPO0
GPO1
AD2/GPO2
0.1 Fµ
47KΩ
Clock Control
Clock Source
CS8416
+3.3V to +5V
1nF
Serial Audio
Input
Device
External
Interface
FILT DGNDAGND
Rflt
Cflt Crip
***
A seperate analog supply is only necessary in applications where RMCK is used for a jitter
*
sensitive tast. For applications where RMCK is not used for a jitter sensitive task, connect
VA+ to VD+ via a ferrite bead. Keep decoupling capacitors between VA+ and AGND.
Please see section 5.1 "8:2 S/PDIF Input Multiplexer" and Appendix
**
A for typical input configurations and recommended input circuits.
For best jitter performance connect the filter ground directly to the AGND pin.
***
SeeTable2forPLLfiltervalues.
Figure 5. Typical Connection Diagram - Software Mode
10 DS578PP2
+3.3V
Analog
Supply
**
Ferrite
Bead
VL+
VL+
**
10 Fµ
***
0.1 Fµ 1nF
AES3 /
S/PDIF
Sources
Hardware
Control
+3.3V
VD+
VA+
RXN
RXP0
RXP1
RXP2
RXP3
RST
RXSEL0
RXSEL1
TXSEL0
TXSEL1
NV/RERR
*
AUDIO
96KHZ
*
RCBL
*
*
U
C
*
10 Fµ 0.1 Fµ 1nF
VL+
OLRCK
OSCLK
SDOUT
CS8416
RMCK
*
OMCK Clock Source
TX
0.1 Fµ
Serial Audio
Input Device
47KΩ
Clock Control
External
Interface
CS8416
+3.3V to +5V
1nF
FILT DGNDAGND
Rflt
Cflt Crip
****
These pins must be pulled high to VL+ or low to DGND through a 47KΩ resistor.
*
A seperate analog supply is only necessary in applications where RMCK is used for a jitter
**
sensitive tast. For applications where RMCK is not used for a jitter sensitive task, connect
VA+ to VD+ via a ferrite bead. Keep decoupling capacitors between VA+ and AGND.
Please see section 5.1 "8:2 S/PDIF Input Multiplexer" and Appendix
***
A for typical input configurations and recommended input circuits.
For best jitter performance connect the filter ground directly to the AGND pin.
****
See Table 2 for PLL filter values.
Figure 6. Typical Connection Diagram - Hardware Mode
DS578PP2 11
CS8416
3 GENERAL DESCRIPTION
The CS8416 is a monolithic CMOS device which
receives and decodes audio data according to the
AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards.
The CS8416 utilizes an 8:2 multiplexer to select
between eight inputs for decoding and to allow an
input signal to be routed to an output of the
CS8416. Input data is either differential or singleended. A low jitter clock is recovered from the incoming data using a PLL. The decoded audio data
is output through a configurable, 3-wire output
port. The channel status and Q-channel subcode
portion of the user data are assembled in registers
and may be accessed through an SPI or I
Three General Purpose Output (GPO) pins are provided to allow a variety of signals to be accessed
under software control. In hardware mode, dedicated pins are used to select audio stream inputs for
decoding and transmission to a dedicated TX pin.
Hardware mode also allows direct access to channel status and user data output pins.
Figure 5 and Figure 6 show the power supply and
external connections to the CS8416 when configured for software and hardware modes. Please note
2
C port.
that all I/O pins, including RXN and RXP[7:0], operate at the VL+ voltage.
3.1 AES3 and S/PDIF Standards Documents
This document assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3, IEC60958,
and IEC61937 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org
or at www.ansi.org. Obtain a copy of the latest
IEC60958/61937 standard from ANSI or from the
International Electrotechnical Commission at
www.iec.ch
available from the Japanese Electronics Bureau.
Application Note 22: Overview of Digital Audio In-
terface Data Structures contains a useful tutorial
on digital audio specifications, but it should not be
considered a substitute for the standards.
The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as reprint 3518.
. The latest EIAJ CP-1201 standard is
12 DS578PP2
CS8416
4 SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The
port can be adjusted to suit the attached device setting the control registers. The following parameters
are adjustable: master or slave, serial clock frequency, audio data resolution, left or right justification of the data relative to left/right clock, optional
one-bit cell delay of the first data bit, the polarity of
the bit clock, and the polarity of the left/right clock.
By setting the appropriate control bits, many formats are possible.
Figure 8 shows a selection of common output for-
mats, along with the control bit settings. A special
AES3 direct output format is included, which allows the serial output port access to the V, U, and
C bits embedded in the serial audio data stream.
The P bit, which would normally be a parity bit, is
replaced by a Z bit, which is used to indicate the
start of each block. The received channel status
block start signal is also available as the RCBL pin
in hardware mode and through a GPO pin in software mode.
In master mode, the left/right clock (OLRCK) and
the serial bit clock (OSCLK) are outputs, derived
from the recovered RMCK clock. In slave mode,
OLRCK and OSCLK are inputs. OLRCK is normally synchronous to the appropriate master clock,
but OSCLK can be asynchronous and discontinuous if required. By appropriate phasing of OLRCK
and control of the serial clocks, multiple CS8416’s
can share one serial port. OLRCK should be continuous, but the duty cycle can be less than the
specified typical value of 50% if enough serial
clocks are present in each phase to clock all the data
bits. When in slave mode, the serial audio output
port cannot be set for right-justified data. The
CS8416 allows immediate mute of the serial audio
output port audio data by the MUTESAO bit of
Control Register 1.
4.1 Slip/Repeat Behavior
When using the serial audio output port in slave
mode with an OLRCK input that is asynchronous
to the incoming AES3 data, the interrupt bit OSLIP
(bit 5 in the Interrupt 1 Status register, 0Dh) is provided to indicate when repeated or dropped samples occur. Refer to Figure 7 for a AES3 data
format diagram.
When the serial output port is configured as slave,
depending on the relative frequency of OLRCK to
the input AES3 data (Z/X) preamble frequency, the
data will be slipped or repeated at the output of the
CS8416.
After a fixed delay from the Z/X preamble (a few
periods of the internal clock, which is running at
256Fs), the circuit will look back in time until the
previous Z/X preamble:
1) If during that time, the internal data buffer was
not updated, then a slip has occurred. Data from
the previous frame will be output and OSLIP
will be set to 1. Due to the OSLIP bit being
“sticky,” it will remain 1 until the register is
read. It will then be reset until another slip/repeat condition occurs.
2) If during that time the internal data buffer did
not update between two positive or negative
edges (depending on OLRPOL) of OLRCK,
then a repeat has occurred. In this case the buffer data was updated twice, so the part has lost
one frame of data. This event will also trigger
OSLIP to be set to 1. Due to the OSLIP bit being “sticky,” it will remain 1 until the register is
read. It will then be reset until another slip/repeat condition occurs.
3) If during that time, it did see a positive edge on
OLRCK (or negative edge if the SOLRPOL is
set to 1) then no slip or repeat has happened.
Due to the OSLIP bit being “sticky,” it will remain in its previous state until either the register is read or a slip/repeat condition occurs.
DS578PP2 13
Frame 191 Frame 0 Frame 1
CS8416
Channel A
X
Data
Y
Channel B
Data
Channel A
Z Y X Y
Data
Preambles
OLRCK (in slave mode)
Figure 7. AES3 Data Format
If the user reads OSLIP as soon as the event triggers, over a long period of time the rate of occurring INT will be equal to the difference in
frequency between the input AES data and the
slave serial output LRCK. The CS8416 uses a hysteresis window when a slip/repeat event occurs.
The slip/repeat is triggered when an edge of OLRCK passes a window size from the beginning of
the Z/X preamble. Without the hysteresis window,
jitter on OLRCK with a frequency very close to Fs
could slip back and forth, causing multiple slip/repeat events. The CS8416 uses a hysteresis window
to ensure that only one slip/repeat happens even
with jitter on OLRCK.
4.2 AES11 Behavior
When OLRCK is configured as a master, the positive or negative edge of OLRCK (depending on the
setting of SOLRPOL in register 05h) will be within
-1.0%(1/Fs) to 1.1%(1/Fs) from the start of the preamble X/Z. In master mode, the latency through the
part is dependent on the input sample frequency.
The delay through the part from the beginning of
the preamble to the active edge of OLRCK for the
various sample frequencies is given in Table 1.In
Channel B
Data
Channel A
Data
Channel B
Data
master mode without the de-emphasis filter engaged, the latency of the audio data will be 3
frames.
Fs (kHz) Delay (ns)
32 96.6
44.1 78.6
48 74.6
64 60.6
96 50.6
192 TBD
Table 1. Delays by Frequency Values
When OLRCK is configured as a slave any synchronized input within +/-28%(1/Fs) from the positive or negative edge of OLRCK (depending on
the setting of SOLRPOL in register 05h) will be
treated as being sampled at the same time. Since the
CS8416 has no control of the OLRCK in slave
mode, the latency of the data through the part will
be a multiple of 1/Fs plus the delay between OLRCK and the preambles.
Both of these conditions are within the tolerance
range set forth in the AES11 standard.
14 DS578PP2
CS8416
AES3
Direct
(Out)
Left
Justified
(Out)
2
IS
(Out)
Right
Justified
(Out)
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
LSB
Right
MSB
LSB
Right
Right
MSB
UC
VZ
Left
MSB LSB MSB LSB MSB
Left Right
MSB
MSB Extende d MSB Extended
LSB MSB LSB
VZ
MSB
MSB LSB
Left
UCLSB
LSB
Left
MSB
MSB Ex
LSB
SOMS* SOSF* SORES[1:0]* SOJUST* SODEL* SOSPOL* SOLRPOL*
Left Justified X X XX 0 0 0 0
2
S
I
XXXX0101
Right Justified 1 X XX 1 0 0 0
AES3 Direct X X 11 0 0 0 0
X = don’t care to match format, but does need to be set to the desired setting
* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 8. Serial Audio Output Example Formats
DS578PP2 15
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