Cirrus Logic CS8415A-IZ, CS8415A-IS, CS8415A-CZ, CS8415A-CS, CS8415A Datasheet
CS8415A
96 kHz Digital Audio Interface Receiver
Features
l Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible receiver
l +5 V Analog Supply(VA)
l +3 V to +5 V Digital Interface Supply (VL)
l 7:1 S/PDIF Input MUX
l Flexible 3-wire serial digital output port
l 8 kHz to 96 kHz sample frequency range
l Low jitter clock recovery
l Pin and microcontroller read access to
Channel Status and User data
l Microcontroller and standalone modes
l Differential cable receiver
l On-chip Channel Status and User data buffer
memories
l Auto-detection of compressed audio input
streams
l Decodes CD Q sub-code
l OMCK System Clock Mode
I
General Description
The CS8415A is a monolithic CMOS device which receives and decodes one of 7 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3. The CS8415A has a serial digital audio output
port and comprehensive control ability through a 4-wire
microcontroller port. Channel status and user data are
assembled in block sized buffers, making read access
easy.
A low jitter clock recovery mechanism yields a very
clean recovered clock from the incoming AES3 stream.
Stand-alone operation allows systems with no microcontroller to operate the CS8415A with dedicated output
pins for channel status data.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and
automotive audio systems.
ORDERING INFOMATION
CS8415A-CS 28-pin SOIC -10 to +70°C
CS8415A-CZ 28-pin TSSOP -10 to +70°C
CS8415A-IS 28-pin SOIC -40 to +85°C
CS8415A-IZ 28-pin TSSOP -40 to +85°C
CDB8415A Evaluation Board
VA+ AGND FILT RE RR
RXN0
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
Receiver
7:1
MUX
Misc.
Control
H/S
Clock &
Data
Recovery
RST
EMPH U SDA/
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
RMCK
AES3
S/PDIF
Decoder
CDOUT
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001
VL+ DGND
C&Ubit
Data
Buffer
Control
Port &
Registers
SCL/
AD1/
CCLK
CDIN
(All Rights Reserved)
OMCK
AD0/CSINT
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
MAY ‘01
DS470PP3
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
POWER AND THERMAL CHARACTERISTICS....................................................................... 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
DIGITAL CHARACTERISTICS ................................................................................................. 5
SWITCHING CHARACTERISTICS .......................................................................................... 5
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS................................................. 6
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE ...................................... 7
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE......................... 8
2. TYPICAL CONNECTION DIAGRAM ........................................................................................ 9
3. GENERAL DESCRIPTION ..................................................................................................... 10
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 10
3.2 PLL Applications Note ......................................................................................................10
4. SERIAL AUDIO OUTPUT PORT ............................................................................................ 10
5. AES3 RECEIVER .................................................................................................................... 13
5.1 7:1 S/PDIF Input Multiplexer ............................................................................................ 13
5.2 PLL, Jitter Attenuation, and Varispeed ............................................................................ 13
5.2.1 OMCK System Clock Mode ................................................................................ 13
5.2.2 PLL External Components .................................................................................. 13
5.3 Error Reporting and Hold Function .................................................................................. 14
5.4 Channel Status Data Handling ......................................................................................... 15
5.5 User Data Handling .......................................................................................................... 15
5.5.1 Non-Audio Auto-Detection .................................................................................. 15
5.6 Mono Mode Operation ..................................................................................................... 16
6. CONTROL PORT DESCRIPTION AND TIMING .................................................................... 17
6.1 SPI Mode ......................................................................................................................... 17
6.2 Two-Wire Mode ................................................................................................................ 18
6.3 Interrupts .......................................................................................................................... 18
7. CONTROL PORT REGISTER SUMMARY ............................................................................. 20
7.1 Memory Address Pointer (MAP) ....................................................................................... 20
8. CONTROL PORT REGISTER BIT DEFINITIONS .................................................................. 21
8.1 Control 1(1h) ..................................................................................................................... 21
8.2 Control 2 (2h) .................................................................................................................... 21
8.3 Clock Source Control (4h)................................................................................................. 22
8.4 Serial Audio Output Port Data Format (6h)....................................................................... 22
8.5 Interrupt 1 Status (7h) (Read Only)................................................................................... 23
8.6 Interrupt 2 Status (8h) (Read Only)................................................................................... 24
8.7 Interrupt 1 Mask (9h)......................................................................................................... 24
8.8 Interrupt 1 Mode MSB (Ah) and Interrupt 1 Mode LSB(Bh) .............................................. 24
8.9 Interrupt 2 Mask (Ch) ........................................................................................................ 25
8.10 Interrupt 2 Mode MSB (Dh) and Interrupt 2 Mode LSB(Eh)............................................ 25
8.11 Receiver Channel Status (Fh) (Read Only) .................................................................... 25
8.12 Receiver Error (10h) (Read Only) ................................................................................... 27
CS8415A
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of
this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS470PP3
CS8415A
8.13 Receiver Error Mask (11h) ............................................................................................. 28
8.14 Channel Status Data Buffer Control (12h) ...................................................................... 28
8.15 User Data Buffer Control (13h)....................................................................................... 29
8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ........................................... 29
8.17 OMCK/RMCK Ratio (1Eh) (Read Only).......................................................................... 29
8.18 C-bit or U-bit Data Buffer (1Fh - 37h) ............................................................................. 29
8.19 CS8415A I.D. and Version Register (7Fh) (Read Only) ................................................. 29
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 30
10. HARDWARE MODE .............................................................................................................32
10.1 Serial Audio Port Formats ............................................................................................. 32
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 33
12. APPLICATIONS .................................................................................................................. 35
12.1 Reset, Power Down and Start-up .................................................................................. 35
12.2 ID Code and Revision Code .......................................................................................... 35
12.3 Power Supply, Grounding, and PCB layout ................................................................... 35
13. PACKAGE DIMENSIONS ................................................................................................... 36
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS ............. 38
14.1 AES3 Receiver External Components ........................................................................... 38
14.2 Isolating Transformer Requirements ............................................................................. 38
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 40
15.1 AES3 Channel Status (C) Bit Management ................................................................... 40
15.2 Accessing the E buffer ................................................................................................... 40
15.2.1 Reserving the first 5 bytes in the E buffer ......................................................... 40
15.2.2 Serial Copy Management System (SCMS) ....................................................... 41
15.2.3 Channel Status Data E Buffer Access .............................................................. 41
15.3 AES3 User (U) Bit Management .................................................................................... 41
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ...................................................................................... 6
Figure 2. Audio Port Slave Mode and Data Input Timing................................................................ 6
Figure 3. SPI Mode Timing ............................................................................................................. 7
Figure 4. Two-Wire Mode timing ..................................................................................................... 8
Figure 5. Recommended Connection Diagram for Software Mode ................................................ 9
Figure 6. Serial Audio Output Example Formats........................................................................... 12
Figure 7. Jitter Attenuation Characteristics of PLL with 8-96 kHz Fs Filter Components.............. 14
Figure 8. Jitter Attenuation Characteristics of PLL with 32-96 kHz Fs Filter Components............ 14
Figure 9. AES3 Receiver Timing for C & U pin output data .......................................................... 16
Figure 10. Control Port Timing in SPI Mode ................................................................................. 17
Figure 11. Hardware Mode ........................................................................................................... 18
Figure 12. Control Port Timing in Two-Wire Mode........................................................................ 19
Figure 12. Professional Input Circuit ............................................................................................. 38
Figure 13. Transformerless Professional Input Circuit .................................................................. 38
Figure 14. Consumer Input Circuit ................................................................................................ 39
Figure 15. S/PDIF MUX Input Circuit ............................................................................................ 39
Figure 16. TTL/CMOS Input Circuit...............................................................................................39
Figure 17. Channel Status Data Buffer Structure.......................................................................... 40
Figure 18. Flowchart for Reading the E Buffer.............................................................................. 40
LIST OF TABLES
Table 1. PLL External Component Values .................................................................................... 14
Table 2. Control Register Map Summary...................................................................................... 20
Table 3. Equivalent Software Mode Bit Definitions ....................................................................... 32
Table 4. Hardware Mode Start-up Options ................................................................................... 32
DS470PP3 3
CS8415A
1. CHARACTERISTICS AND SPECIFICATIONS
POWER AND THERMAL CHARACTERISTICS (AGND, DGND = 0 V, all voltages with respect
to ground)
Parameter Symbol Min Typ Max Units
Power Supply Voltage VA+
VL+
Supply Current at 48 kHz frame rate VA+
VL+ = 3 V
VL+ = 5 V
Supply Current at 96 kHz frame rate VA+
VL+ = 3 V
VL+ = 5 V
Supply Current in power down Reset high, VA+
Reset high, VL+ = 3 V
Reset high, VL+ = 5 V
Ambient Operating Temperature : ‘-CS’ & ‘-CZ’ (Note 1)
‘-IS’ & ‘-IZ’ (Note 2)
Notes: 1. ‘-CS’ and ‘-CZ’ parts are specified to operate over -10° C to 70° C but are tested at 25° C only.
2. ‘-IS’ and ‘-IZ’ parts are tested over the full -40° C to 85° C temperature range.
T
A
4.5
2.85/4.5
-
-
-
-
-
-
-
-
-
-10
-40
5.0
3.0/5.0
6.3
30.1
46.5
6.6
44.8
76.6
20
60
60
25 70
5.5
3.15/5.5
-
-
-
-
-
-
-
-
-
85
V
V
mA
mA
mA
mA
mA
mA
µA
µA
µA
°C
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V, all voltages with respect to ground)
Parameter Symbol Min Max Units
Power Supply Voltage VL+,VA+ - 6.0 V
Input Current, Any Pin Except Supplies (Note 3) I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
in
in
A
stg
-±10mA
-0.3 (VL+) + 0.3 V
-55 125 °C
-65 150 °C
Notes: 3. Transient currents of up to 100mA will not cause SCR latch-up.
4 DS470PP3
CS8415A
DIGITAL CHARACTERISTICS
(TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = 5V±10%, VL+ = 3/5V ±5/10% )
Parameter Symbol Min Typ Max Units
High-Level Input Voltage, except RXP0, RXN0 V
Low-Level Input Voltage, except RXP0, RXN0 (Note 4) V
Low-Level Output Voltage, (Io=-20 uA) V
High-Level Output Voltage, (Io=20 uA) V
Input Leakage Current I
Differential Input Voltage, RXP0 to RXN0 V
IH
IL
OL
OH
in
TH
2.0 - (VL+) + 0.3 V
-0.3 - 0.4/ 0.8 V
--0.4V
(VL+) - 1 - - V
-±1±10µA
-200 -mV
Notes: 4. At 5V mode, V
= 0.8V (Max), at 3V mode, VIL =0.4V (Max).
IL
* Specifications are subject to change without notice.
SWITCHING CHARACTERISTICS
(TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = 5V±10%, VL+ = 3/5V ±5/10% , Inputs:
Logic 0 = 0V, Logic 1 = VL+; C
RST
pin Low Pulse Width 200 - - µs
PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz
RMCK output jitter - 200 - ps RMS
RMCK output duty cycle 40 50 60 %
= 20 pF)
L
Parameter Symbol Min Typ Max Units
DS470PP3 5
CS8415A
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = 5V±10%, VL+ = 3/5V ±5/10% , Inputs:
Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid (Note 5) t
Master Mode
RMCK to OSCLK active edge delay (Note 5) t
RMCK to OLRCK delay (Note 6) t
OSCLK and OLRCK Duty Cycle - 50 - %
Slave Mode
OSCLK Period (Note 7) t
OSCLK Input Low Width t
OSCLK Input High Width t
OSCLK Active Edge to OLRCK Edge (Note 5,6,8) t
OLRCK Edge Setup Before OSCLK Active Edge (Note 5,6,9) t
Notes: 5. The active edges of OSCLK are programmable.
6. The polarity OLRCK is programmable.
7. No more than 128 SCLK per frame.
8. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
9. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
= 20 pF)
L
dpd
smd
lmd
sckw
sckl
sckh
lrckd
lrcks
--20ns
0-10ns
0-10ns
36 - - ns
14 - - ns
14 - - ns
20 - - ns
20 - - ns
OSCLK
(output)
OLRCK
(output)
RMCK
(input)
t
smd
t
lmd
OLRCK
(input)
OSCLK
(input)
SDOUT
t
lrckd
t
lrcks
t
sckh
t
sckw
t
sckl
t
dpd
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
6 DS470PP3
CS8415A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = 5V±10%, VL+ = 3/5V ±5/10% , Inputs:
Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
= 20 pF)
L
CCLK Clock Frequency (Note 10) f
High Time Between Transmissions t
CS
CS
Falling to CCLK Edge t
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 11) t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 12) t
Fall Time of CCLK and CDIN (Note 12) t
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
0-6.0MHz
1.0 - - µs
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
--50ns
--25ns
--25ns
- - 100 ns
- - 100 ns
Notes: 10. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
<1 MHz.
sck
CS
t
t
sch
CCLK
CDIN
CDOUT
t
css
scl
t
r2
t
dsu
t
f2
t
dh
t
pd
t
csh
Figure 3. SPI Mode Timing
DS470PP3 7
CS8415A
SWITCHING CHARACTERISTICS - CONTROL PORT - Two-Wire MODE
(Note 13, TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VA+ = VL+ = 5V ±10%, Inputs: Logic 0
= 0 V, Logic 1 = VL+; C
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 14) t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
Notes: 13. The Two-Wire Mode is compatible with I
14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
= 20 pF)
L
Parameter Symbol Min Typ Max Units
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
2C®
protocol and is supported only at 5V mode.
- - 100 kHz
4.7 - - µs
4.0 - - µs
4.7 - - µs
4.0 - - µs
4.7 - - µs
0--µs
250 - - ns
--25ns
--25ns
4.7 - - µs
SDA
SCL
Stop Start
t
buf
t
hdst
t
low
Repeated
t
high
t
hdd
t
sud
Figure 4. Two-Wire Mode timing
Start
t
sust
t
hdst
Stop
t
f
t
r
t
susp
8 DS470PP3
2. TYPICAL CONNECTION DIAGRAM
Ferrite *
+5V
Analog
Supply *
Bead
0.1 Fµ
0.1 Fµ
VA+ V L+
+3V to
Digital
Supply
CS8415A
+5V
**
AES3/
SPDIF
Sources
Clock Control RMCK
Hardware
Control
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
RXN0
EMPH
RERR
RST
CS8415A
SDA/CDOUT
SCL/CCLK
AD1/CDIN
A2D
/
RFILT
CFILT CRIP
OLRCK
OSCLK
SDOUT
AD0/CS
INT
DGND2
H/S
DGNDFILTAGND
3-wire Serial
Audio Input
Device
Microcontroller
U
* A separate analog supply is only necessary in applications where RMCK is used
for a jitter sensitive task. For applications where RMCK is not used for a jitter
sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling
capacitor between VA+ and AGND.
Please see section 5.1 "7:1 S/PDIF Input Multiplexer" and Appendix A for typical
**
input configurations and recommended input circuits.
Figure 5. Recommended Connection Diagram for Software Mode
DS470PP3 9
CS8415A
3. GENERAL DESCRIPTION
The CS8415A is a monolithic CMOS device which
receives and decodes audio data according to the
AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards.
Input data is either differential or single-ended. A
low jitter clock is recovered from the incoming data
using a PLL. The decoded audio data is output
through a configurable, 3-wire output port. The
channel status and user data are assembled in block
sized buffers and may be accessed through an SPI
or Two-Wire microcontroller port. For systems
with no microcontroller, a stand alone mode allows
direct access to channel status and user data output
pins.
Target applications include AVR, CD-R, DAT,
DVD, multimedia speakers, MD and VTR equipment, mixing consoles, digital audio transmission
and receiving equipment, high quality D/A and
A/D converters, effects processors, set-top TV boxes, and computer audio systems.
Figure 5 shows the supply and external connections to the CS8415A, when configured for operation with a microcontroller.
3.1 AES3 and S/PDIF Standards Documents
tutorial on digital audio specifications, but it should
not be considered a substitute for the standards.
The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
3.2 PLL Applications Note
See Crystal Application Note 159: PLL Filter Optimization for the CS8415A, CS8420, and CS8427
by Patrick Muyshondt and Stuart Dudley Dimond
III for a tutorial on the CS8415A Phase-LockedLoop. This document gives equations for selecting
the proper PLL filter and guidelines on laying out
the PC board for the best performance.
4. SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The
port can be adjusted to suit the attached device setting the control registers. The following parameters
are adjustable: master or slave, serial clock frequency, audio data resolution, left or right justification of the data relative to left/right clock, optional
one-bit cell delay of the first data bit, the polarity of
the bit clock and the polarity of the left/right clock.
By setting the appropriate control bits, many formats are possible.
This data sheet assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and
IEC60958 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org
or www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest
EIAJ CP-1201 standard is available from the Japanese Electronics Bureau.
Crystal Application Note 22: Overview of Digital
Audio Interface Data Structures contains a useful
10 DS470PP3
Figure 6 shows a selection of common output formats, along with the control bit settings. A special
AES3 direct output format is included, which allows the serial output port access to the V, U, and
C bits embedded in the serial audio data stream.
The P bit is replaced by a Z bit that marks the start
of each block. The received channel status block
start signal is only available in hardware mode, as
the RCBL pin.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the recovered
RMCK clock. In slave mode, the left/right clock
and the serial bit clock are inputs. The left/right
clock must be synchronous to the appropriate mas-
CS8415A
ter clock, but the serial bit clock can be asynchronous and discontinuous if required. By appropriate
phasing of the left/right clock and control of the serial clocks, multiple CS8415A’s can share one serial port. The left/right clock should be continuous,
but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are
present in each phase to clock all the data bits.
When in slave mode, the serial audio output port
must not be set for right-justified data. When using
the serial audio output port in slave mode with an
OLRCK input which is asynchronous to the incoming AES3 data, then an interrupt bit(OSLIP) is provided to indicate when repeated or dropped
samples occur.
The CS8415A allows immediate mute of the serial
audio output port audio data by the MUTESAO bit
of Control Register 1.
DS470PP3 11
CS8415A
AES3
Direct
(Out)
Left
Justified
(Out)
2
I S
(Out)
Right
Justified
(Out)
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
LSB
Right
MSB
LSB
Right
MSB LSB
Right
MSB
UC
VZ
Left
MSB LSB MSB LSB MSB
Left Right
LSB
LSB
MSB
Left
MSB LSB
Left
MSB
UCLSB
VZ
MSB
LSB
SOMS* SOSF* SORES[1:0]* SOJUST* SODEL* SOSPOL* SOLRPOL*
Left Justified X X XX 0 0 0 0
2
I
S
XXXX0101
Right Justified 1 X XX 1 0 0 0
AES3 Direct X X 11 0 0 0 0
X = don’t care to match format, but does need to be set to the desired setting
* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 6. Serial Audio Output Example Formats
12 DS470PP3
CS8415A
5. AES3 RECEIVER
The CS8415A includes an AES3 digital audio receiver. A comprehensive buffering scheme provides read access to the channel status and user
data. This buffering scheme is described in Appendix B.
The AES3 receiver accepts and decodes audio and
digital data according to the AES3, IEC60958
(S/PDIF), and EIAJ CP-1201 interface standards.
The receiver consists of a differential input stage,
driven through pins RXP0 and RXN0, a PLL based
clock recovery circuit, and a decoder which separates the audio data from the channel status and
user data.
External components are used to terminate and isolate the incoming data cables from the CS8415A.
These components are detailed in Appendix A.
5.1 7:1 S/PDIF Input Multiplexer
The CS8415A employs a 7:1 S/PDIF Input Multiplexer to accommodate up to seven channels of input digital audio data. Digital audio data is singleended and input through the RXP0-6 pins. When
any portion of the multiplexer is implemented, unused RXP pins should be tied to ground, and RXN0
must be ac-coupled to ground. The multiplexer select line control is accessed through bits MUX2:0
in the Control 2 register. The multiplexer defaults
to RXP0. Therefore, the default configuration is for
a differential signal to be input through RXP0 &
RXN0. Please see Appendix A for recommended
input circuits.
5.2 PLL, Jitter Attenuation, and Varispeed
An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream.
There are some applications where low jitter in the
recovered clock, presented on the RMCK pin, is
important. For this reason, the PLL has been designed to have good jitter attenuation characteristics, shown in Figures 7 and 8. In addition, the PLL
has been designed to only use the preambles of the
AES3 stream to provide lock update information to
the PLL. This results in the PLL being immune to
data dependent jitter affects because the AES3 preambles do not vary with the data.
The PLL has the ability to lock onto a wide range
of input sample rates with no external component
changes. If the sample rate of the input subsequently changes, for example in a varispeed application,
the PLL will only track up to ±12.5% from the
nominal center sample rate. The nominal center
sample rate is the sample rate that the PLL first
locks onto upon application of an AES3 data
stream or after enabling the CS8415A clocks by
setting the RUN control bit. If the 12.5% sample
rate limit is exceeded, the PLL will return to its
wide lock range mode and re-acquire a new nominal center sample rate.
5.2.1 OMCK System Clock Mode
A special clock switching mode is available that allows the clock that is input through the OMCK pin
to be output through the RMCK pin. This feature is
controlled by the SWCLK bit in register 1 of the
control registers. When the PLL loses lock, the frequency of the VCO drops to 300 kHz. The clock
switching mode allows the clock input through
OMCK to be used as a clock in the system without
any disruption when the PLL loses lock, for example, when the input is removed from the receiver.
When SWCLK is enabled and this mode is implemented, RMCK is an output and is not bi-directional. This clock switching is done glitch free. Please
note that internal circuitry associated with RMCK
is not driven by OMCK. This means that OSCLK
and OLRCK continue to be derived from the PLL
and are not usable in this mode.
5.2.2 PLL External Components
The PLL behavior is affected by the external filter
component values. Figure 5 shows the recommended configuration of the two capacitors and
DS470PP3 13
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