Cirrus Logic CS8415A User Manual
CS8415A
96 kHz Digital Audio Interface Receiver
Features
! Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF-compatible Receiver
! +5.0 V Analog Supply (VA+)
! +3.3 V or +5.0 V Digital Interface (VL+)
! 7:1 S/PDIF Input MUX
! Flexible 3-wire Serial Digital Output Port
! 8-kHz to 96-kHz Sample Frequency Range
! Low-jitter Clock Recovery
! Pin and Microcontroller Read Access to
Channel Status and User Data
! Microcontroller and Standalone Modes
! Differential Cable Receiver
! On-chip Channel Status and User Data Buffer
Memories
! Auto-detection of Compressed Audio Input
Streams
! Decodes CD Q Sub-Code
! OMCK System Clock Mode
General Description
The CS8415A is a monolithic CMOS device which receives and decodes one of 7 channels of audio data
according to the IEC60958, S/PDIF, EIAJ CP1201, or
AES3. The CS8415A has a serial digital audio output
port and comprehensive control ability through a 4-wire
microcontroller port. Channel status and user data are
assembled in block-sized buffers, making read access
easy.
A low-jitter clock recovery mechanism yields a very
clean recovered clock from the incoming AES3 stream.
Stand-alone operation allows systems with no microcontroller to operate the CS8415A with dedicated
output pins for channel status data.
The CS8415A is available in a 28-pin TSSOP and SOIC
package in both Commerical (-10 to +70°C) and Industrial grades (-40 to +85° C). The CDB8415A Customer
Demonstration board is also available for device evaluation and implementation suggestions. Please ref er to
page 2 for ordering informa tion.
Target applications include A/V receivers, CD-R, DVD
receivers, multimedia speakers, digital mixing consoles,
effects processors, set-top boxes, and computer and
automotive audio systems.
VA+ AGND FILT RERR
RXN0
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
http://www.cirrus.com
Receiver
7:1
MUX
Misc.
Control
H/S
Clock &
Data
Recovery
RST
RMCK
AES3
S/PDIF
Decoder
EMPH U SDA/
CDOUT
Copyright © Cirrus Logic, Inc. 2005
(All Rights Reserved)
VL+ DGND
C&Ubit
Data
Buffer
Control
Port &
Registers
SCL/
CCLK
AD1/
CDIN
OMCK
AD0/CSINT
Serial
Audio
Output
OLRCK
OSCLK
SDOUT
AUGUST '05
DS470F4
CS8415A
ORDERING INFORMATION
Temp
Product Description Package Grade
28-
TSSOP
96 kHz Digital
CS8415A
2 DS470F4
Audio Interface
Receiver
28-SOIC Commercial -10 to +70°C
Commercial -10 to +70°C
Industrial -40 to +85°C YES
----
Range Pb-Free Container Order Number
YES
NO
YES
NO
Rail CS8415A-CZZ
Tape and Reel CS8415A-CZZR
Rail CS8415A-CZ
Tape and Reel CS8415A-CZR
Rail CS8415A-IZZ
Tape and Reel CS8415A-IZZR
Rail CS8415A-CSZ
Tape and Reel CS8415A-CSZR
Rail CS8415A-CS
Tape and Reel CS8415A-CSR
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 6
SPECIFIED OPERATING CONDITIONS.............................................................................................. 6
ABSOLUTE MAXIMUM RATINGS........................................................................................................6
DC ELECTRICAL CHARACTERISTICS ................ ............................................. .... ... ... ... ... .................. 6
DIGITAL INPUT CHARACTERISTICS..................................................................................................7
DIGITAL INTERFACE SPECIFICATIONS ............................................................................................ 7
SWITCHING CHARACTERISTICS.......................................................................................................7
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS ............................................................. 8
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE................................................... 9
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE...................................... ... ... ... ... 10
2. TYPICAL CONNECTION DIAGRAM .................................................................................................. 11
3. GENERAL DESCRIPTION .................................................................................................................. 12
3.1 AES3 and S/PDIF Standards Documents .................................................................................... 12
4. SERIAL AUDIO OUTPUT PORT ......................................................................................................... 13
5. AES3 RECEIVER ................................................................................................................................ 15
5.1 7:1 S/PDIF Input Multiplexer .. .... ... ... ... ... .... ............................................. ... ... .... ... ... ... ... .... ............ 15
5.2 OMCK System Clock Mode ............. ... ... .... ... ... ... .... ... ............................................. ... ... .... ... ......... 15
5.3 PLL, Jitter Attenuation, and Varispeed ......................................................................................... 15
5.4 Error Reporting and Hold Function ............................................................................................... 15
5.5 Channel Status Data Handling ..................................................................................................... 16
5.6 User Data Handling ...................................... ... ... .... ... ... ... ............................................. ................ 16
5.7 Non-Audio Auto-Detection ......................... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ............ 16
5.8 Mono Mode Operation ............... ... ... ... ... .... ... ............................................. ... .... ... ... ...................... 17
6. CONTROL PORT DESCRIPTION AND TIMING ................................................................................ 18
6.1 SPITM Mode ............. .... ... ............................................. ... .... ... ... ................................................... 18
6.2 I²C Mode ................................................................. ... ............................................. ...................... 19
6.3 Interrupts ......... ... ... ... .... ... ... ... .... ............................................. ... ... ................................................ 19
7. CONTROL PORT REGISTER SUMMARY ......................................................................................... 20
7.1 Memory Address Pointer (MAP) ............................. ............................................................. .........20
8. CONTROL PORT REGISTER BIT DEFINITIONS .............................................................................. 21
8.1 Control 1 (01h) ............... ... ............................................. .... ......................................................... 21
8.2 Control 2 (02h) .......... .............................................. ... ... ................................................................ 21
8.3 Clock Source Control (04h) .......................................................................................................... 22
8.4 Serial Audio Output Port Data Format (06h) .................................................................................22
8.5 Interrupt 1 Status (07h) (Read Only) ............................................................................................ 23
8.6 Interrupt 2 Status (08h) (Read Only) ............................................................................................ 24
8.7 Interrupt 1 Mask (09h) .................................................................................................................. 24
8.8 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) ..................................................... 24
8.9 Interrupt 2 Mask (0Ch) .................................................................................................................. 24
8.10 Interrupt 2 Mode MSB (0Dh) and Interrupt 2 Mode LSB (0Eh) ................................................... 25
8.11 Receiver Channel Status (0Fh) (Read Only) .............................................................................. 25
8.12 Receiver Error (10h) (Read Only) ............................................................................................... 26
8.13 Receiver Error Mask (11h) .......................................................................................................... 26
8.14 Channel Status Data Buffer Control (12h) ..................................................................................27
8.15 User Data Buffer Control (13h) ................................................................................................... 27
8.16 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) ........................................................28
8.17 OMCK/RMCK Ratio (1Eh) (Read Only) ...................................................................................... 28
8.18 C-bit or U-bit Data Buffer (20h - 37h) .......................................................................................... 28
8.19 CS8415A I.D. and Version Register (7Fh) (Read Only) ............................................................. 28
9. PIN DESCRIPTION - SOFTWARE MODE .......................................................................................... 29
10. HARDWARE MODE .......................................................................................................................... 31
10.1 Serial Audio Port Formats .......................................................................................................... 31
11. PIN DESCRIPTION - HARDWARE MODE ....................................................................................... 32
12. APPLICATIONS ............................................................................................................................... 34
12.1 Reset, Power Down and Start-Up .............................................................................................. 34
12.2 ID Code and Revision Code ....................................................................................................... 34
12.3 Power Supply, Grounding, and PCB Layout ..............................................................................34
CS8415A
DS470F4 3
CS8415A
13. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 RECEIVER COMPONENTS .......................... 35
13.1 AES3 Receiver External Components ........................................................................................ 35
13.2 Isolating Transformer Requirements .......................................................................................... 36
14. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........................ 37
14.1 AES3 Channel Status (C) Bit Management ................................................................................ 37
14.2 Accessing the E Buffer ............................................................................................................... 37
14.2.1 Reserving the First 5 Bytes in the E Buffer .............................. ...................................... 38
14.2.2 Serial Copy Management System (SCMS) .................................................................... 38
14.2.3 Channel Status Data E Buffer Access ........................................................................... 38
14.2.3.1 One-Byte Mode............................ ... ... ... .... ... ... ... ... .... ......................................... 38
14.2.3.2 Two-Byte Mode...................................................................... ... ... ... ................... 39
14.3 AES3 User (U) Bit Management ................................................................................................. 39
15. APPENDIX C: PLL FILTER ............................................................................................................... 40
15.1 General ....................... ... ... ... .... ... ... ............................................. ... .... ... ... ................................... 40
15.2 External Filter Components .............................. .... ... ... ... .... ... ... ... ... .... ... ...................................... 41
15.2.1 General ................ ... .... ............................................. ... ... ... .... ... ...................................... 41
15.2.2 Capacitor Selection ........................................................................................................ 41
15.2.3 Circuit Board Layout ...................... ... ... .... ... ... ... .... ... ... ............................................. ...... 41
15.3 Component Value Selection ....................................................................................................... 42
15.3.1 Identifying the Part Revision .......................................................................................... 42
15.3.2 External Components .............................. ... ... ................................................................ 42
15.3.3 Jitter Tolerance ................. ... ... .... ... ... ... .... ............................................. ... ... ... .... ... ......... 43
15.3.4 Jitter Attenuation ......... ... ............................................. ... ... .... ... ... ... .... ... ... ...................... 44
16. REVISION HISTORY ........................................................................................................................ 45
4 DS470F4
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ................................................................................................... 8
Figure 2. Audio Port Slave Mode and Data Input Timing............................................................................. 8
Figure 3. SPI Mode Timing .......................................................................................................................... 9
Figure 4. I²C Mode Timing ......................................................................................................................... 10
Figure 5. Recommended Connection Diagram for Software Mode ........................................................... 11
Figure 6. Serial Audio Output Example Formats........................................................................................ 14
Figure 7. AES3 ReceiverTiming for C & U Pin Output Data ...................................................................... 17
Figure 8. Control Port Timing in SPI Mode ................................................................................................ 18
Figure 9. Control Port Timing in I²C Mode ................................................................................................. 19
Figure 10. Hardware Mode ........................................................................................................................ 31
Figure 11. Professional Input Circuit.......................................................................................................... 36
Figure 12. Transformerless Professional Input Circuit............................................................................... 36
Figure 13. Consumer Input Circuit ............................................................................................................. 36
Figure 14. S/PDIF MUX Input Circuit ......................................................................................................... 36
Figure 15. TTL/CMOS Input Circuit............................................................................................................ 36
Figure 16. Channel Status Data Buffer Structure....................................................................................... 37
Figure 17. Flowchart for Reading the E Buffer........................................................................................... 38
Figure 18. PLL Block Diagram ................................................................................................................... 40
Figure 19. Recommended Layout Example.................................. .... ... ... ... ... .... ... ... ................................... 41
Figure 20. Jitter Tolerance Template......................................................................................................... 43
Figure 21. Revision A................................................................................................................................. 44
Figure 22. Revision A1............................................................................................................................... 44
Figure 23. Revision A2 using A1 Values.................................................................................................... 44
Figure 24. Revision A2 using A2* Values .................................................................................................. 44
CS8415A
LIST OF TABLES
Table 1. Control Register Map Summary................................................................................................... 20
Table 2. Equivalent Software Mode Bit Definitions.................................................................................... 31
Table 3. Hardware Mode Start-Up Options................ ... ... .... ... ............................................. ... ... .... ... ......... 31
Table 4. Second Line Part Marking............................................................................................................ 42
Table 5. Fs = 8 to 96 kHz........................................................................................................................... 42
Table 6. Fs = 32 to 96 kHz......................................................................................................................... 42
Table 7. Revision History........................................................................................................................... 45
DS470F4 5
CS8415A
1. CHARACTERISTICS AND SPECIFICATIONS
All Min/Max characteristics and specifications are guaranteed over the Specified Operat ing Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and
T
= 25°C.
A
SPECIFIED OPERATING CONDITIONS
AGND, DGND = 0 V, all voltages with respect to 0 V.
Parameter Symbol Min Typ Max Units
Power Supply Voltage
(Note 1)
Ambient Operating Temperature: Commercial Grade
Industrial Grade
VA+
VL+
T
A
4.5
2.85
-10
-40
5.0
3.3 or 5.0
-
-
5.5
5.5
+70
+85
V
V
°C
Notes:
1. I²C protocol is supported only in VL+ = 5.0 V mode.
ABSOLUTE MAXIMUM RATINGS
AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Max Units
Power Supply Voltage
Input Current, Any Pin Except Supplies (Note 2)
Input Voltage
Ambient Operating Temperature (power applied)
Storage Temperature
2. Transient currents of up to 100 mA will not cause SCR latch-up.
VL+,VA+ - 6.0 V
I
in
V
in
T
A
T
stg
-±10mA
-0.3 (VL+) + 0.3 V
-55 125 °C
-65 150 °C
DC ELECTRICAL CHARACTERISTICS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters Symbol Min Typ Max Units
Power-down Mode (Note 3)
Supply Current in power down V A+
VL+ = 3.3 V
VL+ = 5.0 V
-
-
-
Normal Operation (Note 4)
Supply Current at 48 kHz frame rate VA+
VL+ = 3.3 V
VL+ = 5.0 V
Supply Current at 96 kHz frame rate VA+
VL+ = 3.3 V
VL+ = 5.0 V
3. Power Down Mode is defined as RST
4. Normal operation is defined as RST
= LO with all clocks and data lines held static.
= HI.
-
-
-
-
-
-
6 DS470F4
20
60
60
6.3
30.1
46.5
6.6
44.8
76.6
-
-
-
-
-
-
-
-
-
µA
µA
µA
mA
mA
mA
mA
mA
mA
DIGITAL INPUT CHARACTERISTICS
Parameters Symbol Min Typ Max Units
Input Leakage Current
Differential Input Voltage, RXP0 to RXN0
DIGITAL INTERFACE SPECIFICATIONS
AGND = DGND = 0 V; all voltages with respect to 0 V.
Parameters Symbol Min Max Units
High-Level Output Voltage (IOH = -3.2 mA)
Low-Level Output Voltage (IOH = 3.2 mA)
High-Level Input Voltage, except RX
Low-Level Input Voltage, except RX
n
n
(Note 5)
CS8415A
I
in
V
TH
V
OH
V
OL
V
IH
V
IL
-±1±10µA
-200- mV
(VL+) - 1.0 - V
-0.4V
2.0 (VL+) + 0.3 V
-0.3 0.4/0.8 V
5. At 5.0 V mode, V
= 0.8 V (Max), at 3.3 V mode, VIL =0.4 V (Max).
IL
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
RST pin Low Pulse Width
PLL Clock Recovery Sample Rate Range
RMCK output jitter (Note 6)
RMCK output duty cycle
6. Cycle-to-cycle using 32 to 96 kHz external PLL filter components.
200 - - µs
8.0 - 108.0 kHz
- 200 - ps RMS
40 50 60 %
DS470F4 7
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
OSCLK Active Edge to SDOUT Output Valid (Note 7)
Master Mode
RMCK to OSCLK active edge delay (Note 7)
RMCK to OLRCK delay (Note 8)
OSCLK and OLRCK Duty Cycle
Slave Mode
OSCLK Period (Note 9)
OSCLK Input Low Width
OSCLK Input High Width
OSCLK Active Edge to OLRCK Edge (Note 7, 8, 10)
OLRCK Edge Setup Before OSCLK Active Edge
Notes 7, 8, 11
7. The active edges of OSCLK are program m ab le.
8. The polarity OLRCK is programmable.
t
dpd
t
smd
t
lmd
t
sckw
t
sckl
t
sckh
t
lrckd
t
lrcks
- - 20 ns
0 - 10 ns
0 - 10 ns
-50- %
36 - - ns
14 - - ns
14 - - ns
20 - - ns
20 - - ns
CS8415A
9. No more than 128 SCLK per frame.
10. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
has changed.
11. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.
OSCLK
(output)
OLRCK
(output)
t
smd
RMCK
(output)
Hardware Mode
RMCK
(output)
Software M ode
t
lm d
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
OLRCK
(input)
OSCLK
(input)
SDOUT
t
lrckd
t
lrcks
t
sckh
t
sckw
t
sckl
t
dpd
8 DS470F4
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 12)
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time (Note 13)
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN (Note 14)
Fall Time of CCLK and CDIN (Note 14)
12. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dictated by the timing requirements necessary to access the Channel Status and User Bit buffer memory.
Access to the control register file can be carried out at the full 6 MHz rate. The minimum allowable input
sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should be safe for all
possible conditions.
f
t
t
t
t
t
sck
csh
css
scl
sch
dsu
t
dh
t
pd
t
r1
t
f1
t
r2
t
f2
0-6.0MHz
1.0 - - µs
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
- - 50 ns
- - 25 ns
- - 25 ns
- - 100 ns
- - 100 ns
CS8415A
13. Data must be held for sufficient time to bridge the transition time of CCLK.
14. For f
<1 MHz.
sck
CS
CCLK
CDIN
CDOUT
t
css
t
t
sch
scl
t
r2
Figure 3. SPI Mode Timing
t
dsu
t
f2
t
dh
t
csh
t
pd
DS470F4 9
SWITCHING CHARACTERISTICS - CONTROL PORT - I²C MODE
(Note 15), Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF.
Parameter Symbol Min Typ Max Units
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 16)
SDA Setup Time to SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
15. I²C protocol is supported only in VL+ = 5.0 V mode.
16. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.
fscl - - 100 kHz
t
t
hdst
t
low
t
high
t
sust
t
hdd
t
sud
t
susp
buf
t
t
r
f
4.7 - - µs
4.0 - - µs
4.7 - - µs
4.0 - - µs
4.7 - - µs
0--µs
250 - - ns
- - 25 ns
- - 25 ns
4.7 - - µs
CS8415A
SDA
SCL
Stop Start
t
buf
t
hdst
t
low
t
high
t
hdd
Figure 4. I²C Mode Timing
t
sud
Repeated
Start
t
t
sust
hdst
Stop
t
f
t
r
t
susp
10 DS470F4
2. TYPICAL CONNECTION DIAGRAM
Ferrite *
+5.0 V
Analog
Supply*
Bead
0.1 Fµ
0.1 Fµ
VA+ VL+
CS8415A
+3.3 V or +5.0 V
Digital Supply
**
AES3/
SPDIF
Sources
Clock Control RMCK
Hardware
Control
RXP6
RXP5
RXP4
RXP3
RXP2
RXP1
RXP0
RXN0
EMPH
RERR
RST
CS8415A
SDA/CDOUT
SCL/CCLK
A2D
/
RFILT
CFILT CRIP
OLRCK
OSCLK
SDOUT
AD0/CS
AD1/CDIN
INT
DGND2
H/S
DGNDFILTAGND
3-wire Serial
Audio Input
Device
Microcontroller
U
* A separate analog supply is only necessary in applications where RMCK is used
for a jitter sensitive task. For applications where RMCK is not used for a jitter
sensitive task, connect VA+ to VD+ via a ferrite bead. Keep the decoupling
capacitor between VA+ and AGND.
Please see section 5.1 "7:1 S/PDIF Input Multiplexer" and Appendix A for typical
**
input configurations and recommended input circuits.
Figure 5. Recommended Connection Diagram for Software Mode
DS470F4 11
CS8415A
3. GENERAL DESCRIPTION
The CS8415A is a monolithic CMOS device which receives and decodes audio data according to the AES3,
IEC60958, S/PDIF, and EIAJ CP1201 inte rface standard s.
Input data is either differential or single-ended. A low-jitter clock is recovered from the incoming data using a PLL.
The decoded audio data is output through a configurable, 3-wire output port. The channel status and user data are
assembled in block-sized buffers and may be accessed through an SPI or I²C microcontroller port. For systems
with no microcontroller, a stand-alone mode allows direct access to channel status and user data output pins.
Target applications include AVR, CD-R, DAT, DVD, multimedia speakers, MD and VTR equipment, mixing consoles, digital audio transmission and receiving equipment, high-quality D/A and A/D converters, effects processors,
set-top boxes, and computer audio systems.
Figure 5 shows the supply and external connections to the CS8415A, when configured for operation with a micro-
controller.
3.1 AES3 and S/PDIF Standards Documents
This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to
have current copies of the AES3 and IEC60958 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org or
www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the International Electrotechnical
Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the Japanese Electronics
Bureau.
Cirrus Logic Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tu-
torial on digital audio specifications, but it should not be considered a substitute for the standards.
The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital
Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the AES as
preprint 3518.
12 DS470F4
CS8415A
4. SERIAL AUDIO OUTPUT PORT
A 3-wire serial audio output port is provided. The port can be adjusted to suit the att ached device setting the control
registers. The following parameters are adjustable: master or slave, serial clock frequency, audio data resolution,
left or right justification of the data relative to lef t/right clock, optio nal one-b it cell delay of the first dat a bit, the po larity of the bit clock, and the polarity of the left/right clock. By setting the appropriate control bits, many formats are
possible.
Figure 6 shows the selection of common output formats including the control bit settings. It should be noted that in
right-justified mode, the serial audio output data is "MSB extended". This means that in a sub-frame where the
MSB of the data is '1', all bits preceding the MSB in the sub-frame will also be '1'. Conversely , in a sub-frame where
the MSB of the data is '0', all bits preceding the MSB in the sub-frame will also be '0'.
A special AES3 direct output format is included, which allows the serial output port access to the V, U, and C bits
embedded in the serial audio data stream. The P bit is replaced by a Z bit that marks the subframe just prior to the
start of each block. The received channel sta tus block star t signal is only available in hardwar e mode, as the RCBL
pin.
In master mode, the left/right clock and the serial bit clock a re outputs, derived from the recovered RMCK clock. In
slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the
appropriate master clock, but the serial bit clock can be asynchronous and discontinuous if required. By appropriate phasing of the left/right clock and control of the serial clocks, multiple CS8415As can share one serial port. The
left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if
enough serial clocks are present in each phase to clock all the data bits. When in slave mode, the serial audio output port must not be set for right-justified data. When using the serial audio output port in slave mode with an
OLRCK input which is asynchronous to the incoming AES3 data, an interrupt bit (OSLIP) is provided to indicate
DS470F4 13
CS8415A
when repeated or dropped samples occur. The CS8415A allows immediate mute of the serial audio output port
audio data by the MUTESAO bit of Control Register 1.
Left
Justified
(Out)
I²S
(Out)
Right
Justified
(Out)
AES3
Direct
(Out)
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
OLRCK
OSCLK
SDOUT
Channel A Channel B
MSB
MSB
Channel A
MSB
LSB
MSB
Channel A Channel B
MSB Extended MSB Extended
Channel A
LSB
Frame 191
MSB
MSB
LSB
Channel B
MSB
LSB
LSB
Frame 0
Channel B
MSB
Channel A
MSB MSB
LSB
LSBLSB
LSB
Channel B
MSB
MSB
LSB
CUVZCUVZCUVCUV
SOMS* SOSF* SORES[1:0]* SOJUST* SODEL* SOSPOL* SOLRPOL*
Left Justified X X XX 0 0 0 0
I²S X X XX 0 1 0 1
Right Justified 1 X XX 1 0 0 0
AES3 Direct X X 11 0 0 0 0
X = don’t care to match format, but does need to be set to the desired setting
* See Serial Output Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 6. Serial Audio Output Example Formats
14 DS470F4
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