Cirrus Logic CS8406-IZ, CS8406-IS, CS8406-CZ, CS8406-CS Datasheet
CS8406
192 kHz Digital Audio Interface Transmitter
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible transmitter
+3.3 V Digital Supply (VD+)
+3.3 V to 5 V Digital Interface (VL+)
On-chip Channel Status and User bit buffer
memories allow block sized updates
Flexible 3-wire serial digital audio input port
Up to 192 kHz frame rate
Microcontroller write access to Channel
Status and User bit data
On-chip differential line driver
Generates CRC codes and parity bits
Standalone mode allows use without a
microcontroller
28-pin SOIC/TSSOP package
I
General Description
The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3,
IEC60958, S/PDIF, or EIAJ CP1201. The CS8406 accepts audio and digital data, which is then multiplexed,
encoded and driven onto a cable.
The audio data is input through a configurable, 3-wire input port. The channel status and user bit data are input
through an SPI or I
assembled in block sized buffers. For systems with no
microcontroller, a stand alone mode allows direct access to channel status and user bit data pins.
Target applications include A/V Receivers, CD-R, DVD
receivers, digital mixing consoles, effects processors,
set-top boxes, and computer and automotive audio
systems.
ORDERING INFORMATION
CS8406-CS 28-pin SOIC -10 to +70°C
CS8406-CZ 28-pin TSSOP -10 to +70°C
CS8406-IS 28-pin SOIC -40 to +85°C
CS8406-IZ 28-pin TSSOP -40 to +85°C
2
C microcontroller port, and may be
RXP
ILRCK
ISCLK
SDIN
Serial
Audio
Input
Misc.
Control
RST OMCKUSDA/
Advance Product Information
http://www.cirrus.com
VD
AD0/
CS
AES3
S/PDIF
Encoder
AD2H/S
C&Ubit
Data
Buffer
Control
Port &
Registers
SCL/
CDOUT
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CCLK
AD1/
CDIN
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
VL DGND
Driver
Output
Clock
Generator
INT
TXP
TXN
TCBL
AUG ‘02
DS580PP1
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................5
Power And Thermal Characteristics ......................................................................................... 5
Absolute Maximum Ratings ...................................................................................................... 5
Digital Characteristics............................................................................................................... 6
Switching Characteristics.......................................................................................................... 6
Switching Characteristics - Serial Audio Ports.......................................................................... 6
Switching Characteristics - Control Port - SPI Mode ................................................................ 8
Switching Characteristics - Control Port - I
2. TYPICAL CONNECTION DIAGRAMS ................................................................................... 10
3. GENERAL DESCRIPTION ..................................................................................................... 12
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 12
4. THREE-WIRE SERIAL INPUT AUDIO PORT ........................................................................12
5. AES3 TRANSMITTER ............................................................................................................ 14
5.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 14
5.2 TXN and TXP Drivers ......................................................................................................14
5.3 Mono Mode Operation ..................................................................................................... 14
6. CONTROL PORT DESCRIPTION AND TIMING ....................................................................16
6.1 SPI Mode .........................................................................................................................16
2
6.2 I
C Mode .........................................................................................................................17
6.3 Interrupts ..........................................................................................................................17
6.4 Memory Address Pointer (MAP) ...................................................................................... 18
7. CONTROL PORT REGISTER SUMMARY ............................................................................. 19
8. CONTROL PORT REGISTER BIT DEFINITIONS ..................................................................20
8.1 Control 1 (01h) .................................................................................................................. 20
8.2 Control 2 (02h) .................................................................................................................. 21
8.3 Data Flow Control (03h).................................................................................................... 21
8.4 Clock Source Control (04h)............................................................................................... 22
8.5 Serial Audio Input Port Data Format (05h)........................................................................ 22
8.6 Interrupt 1 Status (07h) (Read Only)................................................................................. 23
8.7 Interrupt 2 Status (08h) (Read Only)................................................................................. 24
8.8 Interrupt 1 Mask (09h)....................................................................................................... 24
CS8406
2
C Mode................................................................. 9
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative.
To find one nearest you go to <http://www.cirrus.com/corporate/contacts/sales.cfm>
IMPORTANT NOTICE
"Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are i n development and subject to development changes. Cirrus Logic, I nc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the informati on is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant i nformation to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility i s assumed by Cirrus f or the use of this informati on, i ncludi ng use of this
information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cir rus
and by furnishi ng this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property ri ghts. Ci rrus owns the copyrights of the information contained herein and gives consent for copies to be made of the info rmation only
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for general distribution, advertising or pr omotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export li cense and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies describ ed in this material is subject to the PRC Foreign
Trade Law and i s to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (" CRITICAL APPLICATIONS") . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Cirrus Logi c logo desi gns are trademarks of Cirrus Logic, Inc. All other brand and product names in this d ocument may be trademarks or service marks of their respective owners.
2 DS580PP1
CS8406
8.9 Interrupt 1 Mode MSB (Ah) and Interrupt 1 Mode LSB (Bh)............................................. 24
8.10 Interrupt 2 Mask (0Ch).................................................................................................... 24
8.11 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (Eh) ........................................ 25
8.12 Channel Status Data Buffer Control (12h) ...................................................................... 25
8.13 User Data Buffer Control (13h) ....................................................................................... 26
8.14 Channel Status bit or User bit Data Buffer (20h - 37h)................................................... 26
8.15 CS8406 I.D. and Version Register (7Fh) (Read Only) ................................................... 26
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 27
10. HARDWARE MODE ............................................................................................................. 29
10.1 Channel Status, User and Validity Data ........................................................................ 29
10.2 Serial Audio Port Formats ............................................................................................. 29
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 31
12. APPLICATIONS ................................................................................................................... 33
12.1 Reset, Power Down and Start-up .................................................................................. 33
12.2 ID Code and Revision Code .......................................................................................... 33
12.3 Power Supply, Grounding, and PCB layout ................................................................... 33
12.4 Synchronization of Multiple CS8406s ............................................................................ 33
13. PACKAGE DIMENSIONS .................................................................................................. 34
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ...... 36
14.1 AES3 Transmitter External Components ....................................................................... 36
14.2 Isolating Transformer Requirements ............................................................................. 36
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 37
15.1 AES3 Channel Status(C) Bit Management .................................................................... 37
15.1.1 Accessing the E buffer ...................................................................................... 37
15.1.2 Serial Copy Management System (SCMS) ....................................................... 38
15.1.3 Channel Status Data E Buffer Access .............................................................. 38
15.2 AES3 User (U) Bit Management .................................................................................... 38
15.2.1 Mode 1: Transmit All Zeros ............................................................................... 38
15.2.2 Mode 2: Block Mode ......................................................................................... 38
DS580PP1 3
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing....................................................................................... 7
Figure 2. Audio Port Slave Mode and Data Input Timing ................................................................ 7
Figure 3. SPI Mode timing............................................................................................................... 8
Figure 4. I
Figure 5. Recommended Connection Diagram for Software Mode............................................... 10
Figure 6. Recommended Connection Diagram for Hardware Mode .............................................11
Figure 7. Serial Audio Input Example Formats..............................................................................13
Figure 8. Control Port Timing in SPI Mode.................................................................................... 16
Figure 9. Control Port Timing in I
Figure 10. Hardware Mode Data Flow ..........................................................................................29
Figure 11. Professional Output Circuit (VL = 5 V)......................................................................... 36
Figure 12. Consumer Output Circuit (VL = 5 V) ............................................................................ 36
Figure 13. TTL/CMOS Output Circuit............................................................................................ 36
Figure 14. Channel Status Data Buffer Structure .......................................................................... 37
Figure 15. Flowchart for Writing the E Buffer ................................................................................37
2
C Mode timing ............................................................................................................... 9
2
C Mode .................................................................................... 17
LIST OF TABLES
Table 1. Control Register Map Summary ............................................................................................ 19
Table 2. Hardware Mode COPY/C and ORIG pin functions ................................................................29
Table 3. Hardware Mode Serial Audio Port Format Selection ............................................................. 30
Table 4. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode .... 30
CS8406
4 DS580PP1
1. CHARACTERISTICS AND SPECIFICATIONS
POWER AND THERMAL CHARACTERISTICS
(DGND = 0 V, all voltages with respect to ground, no load on output pins)
Parameter Symbol Min Typ Max Units
Power Supply Voltage VD+
VL+
Supply Current at 48 kHz frame rate VD+
VL+ = 3V
VL+ = 5V
Supply Current at 192 kHz frame rate (Note 1)VD+
VL+ = 3V
VL+ = 5V
Supply Current in power down Reset high, VD+
Reset high, VL+ = 3V
Reset high, VL+ = 5V
Ambient Operating Temperature:CS8406-CS & -CZ (Note 2)
CS8406-IS & -IZ (Note 3)
I
D
I
L
I
L
T
A
3.135
3.135
-
-
-
-
-
-
-
-
-
-10
-40
3.3
3.3 to 5.0
6.3
30.1
46.5
6.6
44.8
76.6
20
0
0
25 70
CS8406
3.465
5.5
7.8
37.6
58.1
-
-
-
-
-
-
85
V
V
mA
mA
mA
mA
mA
mA
µA
µA
µA
°C
Notes: 1. Assumes that no inputs are left floating. It is recommended that all digital inputs be driven high or low
at all times.
2. -CS’ and ‘-CZ’ parts are specified to operate over -10 ° C to 70° C but are tested at 25° C only.
3. ‘- IS’ and ‘-IZ’ parts are tested over the full -40°C to 85°C temperature range.
ABSOLUTE MAXIMUM RATINGS
(DGND = 0 V, all voltages with respect to ground)
Parameter Symbol Min Max Units
Power Supply Voltage VD/VL+ - 6.0 V
Input Current, Any Pin Except Supply (Note 4)I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
Notes: 4. Transient currents of up to 100 mA will not cause SCR latch-up.
in
in
A
stg
-±10mA
-0.3 (VL+) + 0.3 V
-55 125 °C
-65 150 °C
DS580PP1 5
CS8406
DIGITAL CHARACTERISTICS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.25 V)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage V
Low-Level Input Voltage V
Input Hysteresis V
Low-Level Output Voltage, (Io=-3.2 mA), except TXP, TXN V
High-Level Output Voltage, (Io=3.2 mA), except TXP, TXN V
Input Leakage Current I
Output High Voltage, TXP, TXN (21mA at V
(15mA at V
Output Low Voltage, TXP, TXN (21mA at V
(17mA at V
TXP Output Resistance V
TXN Output Resistance V
=5.0V)
L
=3.3V)
L
=5.0V)
L
=3.3V)
L
=5.0V
L
V
=3.3V
L
=5.0V
L
V
=3.3V
L
R
R
IH
IL
IH
OL
OH
in
TXP
TXN
2.0 - (VL+) + 0.3 V
-0.3 - 0.8 V
0.25 V
--0.4V
(VL+) - 1 - - V
-±1±10µA
(VL+) - 0.7
(VL+) - 0.7
-0.4
-
-
-
-
(VL+) - 0.4
(VL+) - 0.4
0.4
26.5
33.5
26.5
33.5
VL
VL
0.7
0.7
-
-
-
-
V
V
V
V
Ω
Ω
Ω
Ω
SWITCHING CHARACTERISTICS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.25 V,
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
=20pF)
L
Parameter Symbol Min Typ Max Units
RST
pin Low Pulse Width 200 - - µs
OMCK Frequency for OMCK = 512*Fs 4.1 - 98.4 MHz
OMCK Low and High Width for OMCK = 512*Fs 4.1 - - ns
OMCK Frequency for OMCK = 384*Fs 3.1 - 73.8 MHz
OMCK Low and High Width for OMCK = 384*Fs 5.4 - - ns
OMCK Frequency for OMCK = 256*Fs 2.0 - 49.2 MHz
OMCK Low and High Width for OMCK = 256*Fs 8.1 - - ns
Frame Rate 32 - 192 kHz
AES3 Transmitter Output Jitter - 200 - ps
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.25 V,
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
SDIN Setup Time Before ISCLK Active Edge (Note 5)t
SDIN Hold Time After ISCLK Active Edge (Note 5)t
Master Mode
OMCK to ISCLK active edge delay (Note 5)t
OMCK to ILRCK delay (Note 6)t
ISCLK and ILRCK Duty Cycle - 50 - %
=20pF)
L
ds
dh
smd
lmd
5--ns
5--ns
0 - 10 ns
0 - 10 ns
6 DS580PP1
Parameter Symbol Min Typ Max Units
Slave Mode
ISCLK Period t
ISCLK Input Low Width t
ISCLK Input High Width t
ISCLK Active Edge to ILRCK Edge (Note 7)t
ILRCK Edge Setup Before ISCLK Active Edge (Note 8)t
sckw
sckl
sckh
lrckd
lrcks
Notes: 5. The active edge of ISCLK is programmable.
6. The polarity of ILRCK is programmable.
7. This delay is to prevent the previous ISCLK edge from being interpreted as the first one after ILRCK has
changed.
8. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
CS8406
36 - - ns
14.4 - - ns
14.4 - - ns
10 - - ns
10 - - ns
ISCLK
(output)
ILRCK
(output)
OMCK
(input)
t
smd
t
lmd
ILRCK
(input)
ISCLK
(input)
SDIN
t
lrckd
t
lrcks
t
sckh
t
t
dh
ds
t
t
sckw
sckl
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
DS580PP1 7
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 3.3 V ± 5%, VL+ = 3.135 V to 5.25 V,
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 9)f
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
CCLK Low Time t
CCLK High Time (Note 10)t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 11 )t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 12)t
Fall Time of CCLK and CDIN (Note 12)t
=20pF)
L
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
0-6.0MHz
1.0 - - µs
20 - - ns
66 - - ns
MAX (1/256 FS+ 8, 66) ns
40 - - ns
15 - - ns
- - 50 ns
- - 25 ns
- - 25 ns
- - 100 ns
- - 100 ns
Notes: 9. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate.
10. T
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
must be greater than the larger of the two values, either 1/256FS + 8ns, or 66Tns.
sch
<1MHz.
sck
CS
t
t
css
scl
t
sch
t
csh
CCLK
t
r2
t
f2
CDIN
t
dsu
t
dh
t
pd
CDOUT
Figure 3. SPI Mode timing
8 DS580PP1
CS8406
SWITCHING CHARACTERISTICS - CONTROL PORT - I2CMODE
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 3.3 V ± 5%, VL = 3.135 V to 5.25 V,
Inputs: Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
=20pF)
L
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
- - 100 kHz
4.7 - - µs
4.0 - - µs
4.7 - - µs
4.0 - - µs
4.7 - - µs
0--µs
250 - - ns
- - 25 ns
- - 25 ns
4.7 - - µs
SDA
SCL
Stop Start
t
buf
t
hdst
t
low
t
high
t
hdd
Figure 4. I2CModetiming
t
sud
Repeated
Start
t
sust
t
hdst
Stop
t
f
t
r
t
susp
DS580PP1 9
2. TYPICAL CONNECTION DIAGRAMS
+3.3V
0.1 Fµ
VD VL
AES3 /
S/PDIF
Source
RXP
CS8406
+3.3V to +5V
0.1 Fµ
Serial
Audio
Source
Clock Source
and Control
Microcontroller
To/from other
CS8406's
ILRCK
ISCLK
SDIN
OMCK
AD0 / CS
AD1 / CDIN
AD2
SCL / CCLK
SDA / CDOUT
RST
INT
TCBL
CS8406
DGND
TXP
TXN
H/S
Transmission
Interface
U
47KΩ
User Data
Source
Figure 5. Recommended Connection Diagram for Software Mode
10 DS580PP1
+3.3V
CS8406
+3.3V to +5V
Serial
Audio
Source
Clock Source
and Control
CData
Source
Hardware
Control
0.1 Fµ
ILRCK
ISCLK
SDIN
OMCK
COPY/C
SFMT0
SFMT1
APMS
TCBLD
RST
CEN
EMPH
AUDIO
ORIG
TCBL
VD VL
CS8406
DGND
H/S
TXP
TXN
0.1 Fµ
Transmission
Interface
U
47KΩ
V
47KΩ
User Data
Source
Validity
Source
To/from other
CS8406's
Figure 6. Recommended Connection Diagram for Hardware Mode
DS580PP1 11
CS8406
3. GENERAL DESCRIPTION
The CS8406 is a monolithic CMOS device which
encodes and transmits audio data according to the
AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts audio, channel
status and user data, which is then multiplexed, encoded, and driven onto a cable.
The audio data is input through a configurable, 3wire input port. The channel status bits and user bit
data are input through an SPI or I2C Mode microcontroller port and may be assembled in separate
block sized buffers.
For systems with no microcontroller, a stand alone
mode allows direct access to channel status and
user data input pins.
Target applications include CD-R, DAT, DVD,
MD and VTR equipment, mixing consoles, digital
audio transmission equipment, high quality A/D
converters, effects processors, set-top TV boxes,
and computer audio systems.
Figure 5 shows the supply and external connec-
tions to the CS8406 when configured for operation
with a microcontroller.
3.1 AES3 and S/PDIF Standards Documents
This data sheet assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and
IEC60958 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org
or www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest
EIAJ CP-1201 standard is available from the Japanese Electronics Bureau.
Crystal Application Note 22: Overview of Digital
Audio Interface Data Structures contains a useful
tutorial on digital audio specifications, but it should
not be considered a substitute for the standards.
The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached
device through the control registers. The following
parameters are adjustable:
• Masterorslave
• Serial clock frequency
• Audio data resolution
• Left or right justification of the data relative to
left/right clock
• Optional one-bit cell delay of the first data bit
• Polarity of the bit clock
• Polarity of the left/right clock. (By setting the
appropriate control bits, many formats are possible).
Figure 7 shows a selection of common input for-
mats with the corresponding control bit settings.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the OMCK input pin master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be synchronous to the OMCK master clock, but the serial
bit clock can be asynchronous and discontinuous if
required. The left/right clock should be continuous,
but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are
present in each phase to clock all the data bits.
12 DS580PP1
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