Cirrus Logic CS8405A-IZ, CS8405A-IS, CS8405A-CZ, CS8405A-CS, CS8405A Datasheet
CS8405A
96 kHz Digital Audio Interface Transmitter
Features
Complete EIAJ CP1201, IEC-60958, AES3,
S/PDIF compatible transmitter
+5 V Digital Supply(VD)
+3 V to 5 V Digital Interface (VL)
On-chip Channel Status and User bit buffer
memories allow block sized updates
Flexible 3-wire serial digital audio input port
Up to 96 kHz frame rate
Microcontroller write access to Channel
Status and User bit data
On-chip differential line driver
Generates CRC codes and parity bits
Standalone mode allows use without a
microcontroller
I
General Description
The CS8405A is a monolithic CMOS device which encodes and transmits audio data according to the AES3,
IEC60958, S/PDIF, or EIAJ CP1201. The CS8405A accepts audio and digital data, which is then multiplexed,
encoded and driven onto a cable.
The audio data is input through a configurable, 3-wire input port. The channel status and user bit data are input
through an SPI or Two-Wire microcontroller port, and
may be assembled in block sized buffers. For systems
with no microcontroller, a stand alone mode allows direct access to channel status and user bit data pins.
Target applications include A/V Receivers, CD-R, DVD
receivers, digital mixing consoles, effects processors,
set-top boxes, and computer and automotive audio
systems.
ORDERING INFORMATION
CS8405A-CS 28-pin SOIC -10 to +70°C
CS8405A-CZ 28-pin TSSOP -10 to +70°C
CS8405A-IS 28-pin SOIC -40 to +85°C
CS8405A-IZ 28-pin TSSOP -40 to +85°C
CDB8415A Evaluation Board
RXP
ILRCK
ISCLK
SDIN
Serial
Audio
Input
Misc.
Control
RST OMCKUTCBLSDA/
Preliminary Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
VD+
AD0/
CS
AES3
S/PDIF
Encoder
AD2H/S
C&Ubit
Data
Buffer
Control
Port &
Registers
SCL/
CDOUT
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CCLK
AD1/
CDIN
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
VL+ DGND
Driver
Output
Clock
Generator
INT
TXP
TXN
JUN ‘02
DS469PP4
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 4
POWER AND THERMAL CHARACTERISTICS....................................................................... 4
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4
DIGITAL CHARACTERISTICS................................................................................................. 5
SWITCHING CHARACTERISTICS .......................................................................................... 5
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS.................................................6
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE...................................... 7
SWITCHING CHARACTERISTICS - CONTROL PORT - TWO-WIRE MODE.........................8
2. TYPICAL CONNECTION DIAGRAM ........................................................................................ 9
3. GENERAL DESCRIPTION ..................................................................................................... 10
3.1 AES3 and S/PDIF Standards Documents ........................................................................ 10
4. THREE-WIRE SERIAL INPUT AUDIO PORT ........................................................................ 10
5. AES3 TRANSMITTER ............................................................................................................ 12
5.1 Transmitted Frame and Channel Status Boundary Timing .............................................. 12
5.2 TXN and TXP Drivers ......................................................................................................12
5.3 Mono Mode Operation .....................................................................................................12
6. CONTROL PORT DESCRIPTION AND TIMING .................................................................... 14
6.1 SPI Mode ......................................................................................................................... 14
6.2 Two-Wire Mode ...............................................................................................................15
6.3 Interrupts ..........................................................................................................................15
7. CONTROL PORT REGISTER SUMMARY ............................................................................. 16
7.1 Memory Address Pointer (MAP) .......................................................................................16
8. CONTROL PORT REGISTER BIT DEFINITIONS ..................................................................17
8.1 Control 1 (1h).................................................................................................................... 17
8.2 Control 2 (2h).................................................................................................................... 18
8.3 Data Flow Control (3h)...................................................................................................... 18
8.4 Clock Source Control (4h).................................................................................................19
8.5 Serial Audio Input Port Data Format (5h).......................................................................... 19
8.6 Interrupt 1 Status (7h) (Read Only)...................................................................................20
8.7 Interrupt 2 Status (8h) (Read Only)...................................................................................21
8.8 Interrupt 1 Mask (9h)......................................................................................................... 21
CS8405A
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product inf ormation describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are i n development and subject to development changes. Cirrus Logic, I nc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and l imitation of liability. No responsibil ity is assumed by Cirrus f or the use of this information, includi ng use of this
information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cir rus
and by furnishi ng this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the i nformation contained herein and gives consent for copies to be made of the information only
for use within your or ganization with respect to Cirrus integrated circui ts or ot her parts of Cir rus. This consent does not ext end to ot her copying such as copying
for general distribution, advertising or pr omotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controll ed under the "Foreign Exchange and Forei gn Trade Law" i s to be exported or taken out of Japan. An export l icense and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies describe d in this material is subject to the PRC Foreign
Trade Law and i s to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Ci rrus Logi c logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
2 DS469PP4
CS8405A
8.9 Interrupt 1 Mode MSB (Ah) and Interrupt 1 Mode LSB(Bh).............................................. 21
8.10 Interrupt 2 Mask (Ch)...................................................................................................... 21
8.11 Interrupt 2 Mode MSB (Dh) and Interrupt Mode 2 LSB(Eh) ........................................... 22
8.12 Channel Status Data Buffer Control (12h) ...................................................................... 22
8.13 User Data Buffer Control (13h) ....................................................................................... 23
8.14 Channel Status bit or User bit Data Buffer (20h - 37h)................................................... 23
8.15 CS8405A I.D. and Version Register (7Fh) (Read Only) ................................................. 23
9. PIN DESCRIPTION - SOFTWARE MODE ............................................................................. 24
10. HARDWARE MODE ............................................................................................................. 26
10.1 Channel Status, User and Validity Data ........................................................................ 26
10.2 Serial Audio Port Formats ............................................................................................. 26
11. PIN DESCRIPTION - HARDWARE MODE .......................................................................... 28
12. APPLICATIONS ................................................................................................................... 30
12.1 Reset, Power Down and Start-up .................................................................................. 30
12.2 ID Code and Revision Code .......................................................................................... 30
12.3 Power Supply, Grounding, and PCB layout ................................................................... 30
12.4 Synchronization of Multiple CS8405As ......................................................................... 30
12.4 ORDERING INFORMATION ......................................................................................... 30
13. PACKAGE DIMENSIONS .................................................................................................. 31
14. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER COMPONENTS ...... 33
14.1 AES3 Transmitter External Components ....................................................................... 33
14.2 Isolating Transformer Requirements ............................................................................. 33
15. APPENDIX B: CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT ........... 34
15.1 AES3 Channel Status(C) Bit Management .................................................................... 34
15.1.1 Accessing the E buffer ...................................................................................... 34
15.1.2 Serial Copy Management System (SCMS) ....................................................... 35
15.1.3 Channel Status Data E Buffer Access .............................................................. 35
15.2 AES3 User (U) Bit Management .................................................................................... 35
15.2.1 Mode 1: Transmit All Zeros ............................................................................... 35
15.2.2 Mode 2: Block Mode ......................................................................................... 35
LIST OF FIGURES
Figure 1. Audio Port Master Mode Timing ...................................................................................... 6
Figure 2. Audio Port Slave Mode and Data Input Timing................................................................ 6
Figure 3. SPI Mode timing............................................................................................................... 7
Figure 4. Two-Wire Mode timing..................................................................................................... 8
Figure 5. Recommended Connection Diagram for Software Mode ................................................ 9
Figure 6. Serial Audio Input Example Formats ............................................................................. 11
Figure 7. AES3 Transmitter Timing for C, U and V pin input data ................................................ 13
Figure 8. Control Port Timing in SPI Mode ................................................................................... 14
Figure 9. Control Port Timing in Two-Wire Mode.......................................................................... 15
Figure 10. Hardware Mode ...........................................................................................................26
Figure 11. Professional Output Circuit.......................................................................................... 33
Figure 12. Consumer Output Circuit ............................................................................................. 33
Figure 13. TTL/CMOS Output Circuit............................................................................................ 33
Figure 14. Channel Status Data Buffer Structure.......................................................................... 34
Figure 15. Flowchart for Writing the E Buffer................................................................................ 34
DS469PP4 3
CS8405A
1. CHARACTERISTICS AND SPECIFICATIONS
POWER AND THERMAL CHARACTERISTICS (DGND = 0 V, all voltages with respect to
ground)
Parameter Symbol Min Typ Max Units
Power Supply Voltage VD+
VL+
Supply Current at 48 kHz frame rate VD+
VL+ = 3V
VL+ = 5V
Supply Current at 96 kHz frame rate VD+
VL+ = 3V
VL+ = 5V
Supply Current in power down Reset high, VD+
Reset high, VL+ = 3V
Reset high, VL+ = 5V
Ambient Operating Temperature:CS8405-CS & -CZ (Note 1)
CS8405-IS & -IZ (Note 2)
T
A
4.5
2.85
-
-
-
-
-
-
-
-
-
-10
-40
5.0
-
6.3
30.1
46.5
6.6
44.8
76.6
20
60
60
25 70
5.5
5.5
-
-
-
-
-
-
-
-
-
85
mA
mA
mA
mA
mA
mA
µA
µA
µA
V
V
°C
Notes: 1. -CS’ and ‘-CZ’ parts are specified to operate over -10 ° C to 70° C but are tested at 25° C only.
2. ‘- IS’ and ‘-IZ’ parts are tested over the full -40°C to 85°C temperature range.
ABSOLUTE MAXIMUM RATINGS (DGND = 0V, all voltages with respect to ground)
Parameter Symbol Min Max Units
Power Supply Voltage VD/VL+ - 6.0 V
Input Current, Any Pin Except Supply (Note 3) I
Input Voltage V
Ambient Operating Temperature (power applied) T
Storage Temperature T
Notes: 3. Transient currents of up to 100 mA will not cause SCR latch-up.
in
in
A
stg
-±10mA
-0.3 (VL+) + 0.3 V
-55 125 °C
-65 150 °C
4 DS469PP4
CS8405A
DIGITAL CHARACTERISTICS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage V
Low-Level Input Voltage (Note 4) V
Low-Level Output Voltage, (Io=-3.2 mA), except TXP, TXN V
High-Level Output Voltage, (Io=3.2 mA), except TXP, TXN V
Input Leakage Current I
Output High Voltage, TXP, TXN (I
Output Low Voltage, TXP, TXN (I
= 14 mA) (VL+) - 0.7 (VL+) - 0.4 - V
OH
=14mA) - 0.4 0.7 V
OL
IH
IL
OL
OH
in
2.0 - (VL+) + 0.3 V
-0.3 - 0.4/0.8 V
--0.4V
(VL+) - 1 - - V
-±1±10µA
Notes: 4. At 5V mode, V
= 0.8V (Max), at 3V mode, VIL=0.4V (Max).
IL
SWITCHING CHARACTERISTICS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs:
Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
RST
pin Low Pulse Width 200 - - µs
OMCK Frequency for OMCK = 512*Fs 4.1 - 55.3 MHz
OMCK Low and High Width for OMCK = 512*Fs 7.2 - - ns
OMCK Frequency for OMCK = 384*Fs 3.1 - 41.5 MHz
OMCK Low and High Width for OMCK = 384*Fs 9.6 - - ns
OMCK Frequency for OMCK = 256*Fs 2.0 - 27.7 MHz
OMCK Low and High Width for OMCK = 256*Fs 14.4 - - ns
Frame Rate 8.0 - 108.0 kHz
AES3 Transmitter Output Jitter - - 1 ns
=20pF)
L
DS469PP4 5
CS8405A
SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs:
Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
SDIN Setup Time Before ISCLK Active Edge (Note 5) t
SDIN Hold Time After ISCLK Active Edge (Note 5) t
Master Mode
OMCK to ISCLK active edge delay (Note 5) t
OMCK to ILRCK delay (Note 6) t
ISCLK and ILRCK Duty Cycle - 50 - %
Slave Mode
ISCLK Period (Note 7) t
ISCLK Input Low Width t
ISCLK Input High Width t
ISCLK Active Edge to ILRCK Edge (Note 5,6,8) t
ILRCK Edge Setup Before ISCLK Active Edge (Note 5,6,9) t
=20pF)
L
ds
dh
smd
lmd
sckw
sckl
sckh
lrckd
lrcks
20 - - ns
20 - - ns
0 - 10 ns
0 - 10 ns
36 - - ns
14 - - ns
14 - - ns
20 - - ns
20 - - ns
Notes: 5. The active edge of ISCLK is programmable.
6. The polarity of ILRCK is programmable.
7. No more than 128 SCLK per frame.
8. This delay is to prevent the previous ISCLK edge from being interpreted as the first one after ILRCK has
changed.
9. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.
ISCLK
(output)
ILRCK
(output)
t
smd
OMCK
(input)
t
lmd
Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing
ILRCK
(input)
ISCLK
(input)
SDIN
t
lrckd
t
lrcks
t
sckh
t
t
dh
ds
t
t
sckw
sckl
6 DS469PP4
CS8405A
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
(TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs:
Logic 0 = 0 V, Logic 1 = VL+; C
Parameter Symbol Min Typ Max Units
CCLK Clock Frequency (Note 10) f
High Time Between Transmissions t
CS
Falling to CCLK Edge t
CS
CCLK Low Time t
CCLK High Time t
CDIN to CCLK Rising Setup Time t
CCLK Rising to DATA Hold Time (Note 11) t
CCLK Falling to CDOUT Stable t
Rise Time of CDOUT t
Fall Time of CDOUT t
Rise Time of CCLK and CDIN (Note 12) t
Fall Time of CCLK and CDIN (Note 12) t
=20pF)
L
sck
csh
css
scl
sch
dsu
dh
pd
r1
f1
r2
f2
0-6.0MHz
1.0 - - µs
20 - - ns
66 - - ns
66 - - ns
40 - - ns
15 - - ns
- - 50 ns
- - 25 ns
- - 25 ns
- - 100 ns
- - 100 ns
Notes: 10. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is
dictated by the timing requirements necessary to access the Channel Status and User Bit buffer
memory. Access to the control register file can be carried out at the full 6 MHz rate. The minimum
allowable input sample rate is 8 kHz, so choosing CCLK to be less than or equal to 1.024 MHz should
be safe for all possible conditions.
11. Data must be held for sufficient time to bridge the transition time of CCLK.
12. For f
sck
<1 MHz.
CS
t
t
css
scl
t
sch
t
csh
CCLK
t
r2
t
f2
CDIN
t
dsu
t
dh
t
pd
CDOUT
Figure 3. SPI Mode timing
DS469PP4 7
CS8405A
SWITCHING CHARACTERISTICS - CONTROL PORT - Two-Wire MODE
(Note 13, TA= 25 °C for suffixes ‘CS’ &’CZ’, TA= -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = VL+ = 5V ±10%, Inputs: Logic 0
= 0V, Logic 1 = VL+; C
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time (prior to first clock pulse) t
Clock Low Time t
Clock High Time t
Setup Time for Repeated Start Condition t
SDA Hold Time from SCL Falling (Note 14) t
SDA Setup Time to SCL Rising t
Rise Time of Both SDA and SCL Lines t
Fall Time of Both SDA and SCL Lines t
Setup Time for Stop Condition t
Notes: 13. Two-Wire Mode is compatible with the I
14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
= 20pF)
L
Parameter Symbol Min Typ Max Units
scl
buf
hdst
low
high
sust
hdd
sud
r
f
susp
2C®
protocol and is supported only at 5V mode.
- - 100 kHz
4.7 - - µs
4.0 - - µs
4.7 - - µs
4.0 - - µs
4.7 - - µs
0--µs
250 - - ns
- - 25 ns
- - 25 ns
4.7 - - µs
SDA
SCL
Stop Start
t
buf
t
hdst
t
low
t
high
t
hdd
Figure 4. Two-Wire Mode timing
t
sud
Repeated
Start
t
sust
t
hdst
Stop
t
f
t
r
t
susp
8 DS469PP4
2. TYPICAL CONNECTION DIAGRAM
CS8405A
+5V Supply
AES3 Data
Source
3-wire Serial
Audio Source
Clock Source
and Control
Hardware
Control
To other
CS8405's
0.1 Fµ
VD+ VL+
RXP
ILRCK
ISCLK
SDIN
OMCK
NC1
NC2
NC3
NC4
NC5
RST
TCBL
0.1 Fµ
CS8405A
SDA/CDOUT
AD0/CS
SCL/CCLK
AD1/CDIN
DGND2
DGND3
TXP
TXN
DGNDDGND4
AD2
U
INT
H/S
+3V to
+5V
Supply
Cable
Interface
Microcontroller
AES3/
SPDIF
Equipment
Figure 5. Recommended Connection Diagram for Software Mode
DS469PP4 9
CS8405A
3. GENERAL DESCRIPTION
The CS8405A is a monolithic CMOS device which
encodes and transmits audio data according to the
AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8405A accepts audio, channel status and user data, which is then multiplexed,
encoded, and driven onto a cable.
The audio data is input through a configurable, 3wire input port. The channel status bits and user bit
data are input through an SPI or Two-Wire Mode
microcontroller port and may be assembled in separate block sized buffers.
For systems with no microcontroller, a stand alone
mode allows direct access to channel status and
user data input pins.
Target applications include CD-R, DAT, DVD,
MD and VTR equipment, mixing consoles, digital
audio transmission equipment, high quality A/D
converters, effects processors, set-top TV boxes,
and computer audio systems.
Figure 5 shows the supply and external connections to the CS8405A when configured for operation with a microcontroller.
3.1 AES3 and S/PDIF Standards Documents
This data sheet assumes that the user is familiar
with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and
IEC60958 specifications on hand for easy reference.
The latest AES3 standard is available from the Audio Engineering Society or ANSI at www.aes.org
or www.ansi.org. Obtain the latest IEC60958 standard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest
EIAJ CP-1201 standard is available from the Japanese Electronics Bureau.
Crystal Application Note 22: Overview of Digital
Audio Interface Data Structures contains a useful
tutorial on digital audio specifications, but it should
not be considered a substitute for the standards.
The paper An Understanding and Implementation
of the SCMS Serial Copy Management System for
Digital Audio Transmission, by Clifton Sanchez, is
an excellent tutorial on SCMS. It is available from
the AES as preprint 3518.
4. THREE-WIRE SERIAL INPUT AUDIO PORT
A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the attached
device through the control registers. The following
parameters are adjustable:
• Masterorslave
• Serial clock frequency
• Audio data resolution
• Left or right justification of the data relative to
left/right clock
• Optional one-bit cell delay of the first data bit
• Polarity of the bit clock
• Polarity of the left/right clock. (By setting the
appropriate control bits, many formats are possible).
Figure 6 shows a selection of common input formats with the corresponding control bit settings.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the OMCK input pin master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be synchronous to the OMCK master clock, but the serial
bit clock can be asynchronous and discontinuous if
required. The left/right clock should be continuous,
but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are
present in each phase to clock all the data bits.
10 DS469PP4
CS8405A
Left
Justified
(In)
2
IS
(In)
Right
Justified
(In)
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
ILRCK
ISCLK
SDIN
Left
Right
MSB LSB MSB LSB MSB
Left Right
MSB
Left
LSB MSB LSB
MSB LSB
LSB
MSB
Right
LSB
MSB
SIMS* SISF* SIRES[1:0]* SIJUST* SIDEL* SISPOL* SILRPOL*
Left Justified X X 00+ 0 0 0 0
2
S
I
XX00+0 1 0 1
Right Justified X X XX 1 0 0 0
X = don’t care to match format, but does need to be set to the desired setting
2
S can accept an arbitrary number of bits, determined by the number of ISCLK cycles
+I
* See Serial Input Port Data Format Register Bit Descriptions for an explanation of the meaning of each bit
Figure 6. Serial Audio Input Example Formats
DS469PP4 11
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