Cirrus Logic CS8402A-IS, CS8402A-IP, CS8402A-CS, CS8402A-CP, CS8401A-IS Datasheet

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CS8401A CS8402A

Digital Audio Interface Transmitter

Features

Monolithic Digital Audio Interface Transmitter

Supports: AES/EBU, IEC958, S/PDIF, & EIAJ CP-340 Professional and Consumer Formats

Host Mode and Stand Alone Modes

Generates CRC Codes and Parity Bits

On-Chip RS422 Line Driver

Configurable Buffer Memory (CS8401A)

Transparent Mode Allows Direct Connection of CS8402A and CS8412 or CS8401A and CS8411A

CS8401A

SCK

FSYNC SDATA

RD/WR

A4-A0

D7-D0

7 8

14 16

5 8

Audio

Serial Port

Configurable

Buffer

Memory

Description

The CS8401/2A are monolithic CMOS devices which encode and transmit audio data according to the AES/EBU, IEC958, S/PDIF, & EIAJ CP-340 interface standards. The CS8401/2A accept audio and digital data, which is then multiplexed, encoded and driven onto a cable. The audio serial port is double buffered and capable of supporting a wide variety of formats.

The CS8401A has a configurable internal buffer memory, loaded via a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data.

The CS8402A multiplexes the channel, user, and validity data directly from serial input pins with dedicated input pins for the most important channel status bits.

ORDERING INFORMATION

See page 30.

INT

MUX

MCK

Prescaler

RS422

Driver

TXP

TXN

CS8402A

SCK

FSYNC SDATA

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

7 8

M223M122M0

Audio

Serial Port

Registers

MUX

Dedicated Channel

Status Bits

(All Rights Reserv ed)

CBL24TRNPT

MCK

RST

RS422

Driver

TXP

TXN

NOV ‘93

DS60F1

CS8401A CS8402A

ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground.)

Parameter Symbol Min Max Units

DC Power Supply VD+ 6.0 V Input Current, Any Pin Except Supply Note 1 I

Digital Inpu t Voltage V Ambient Operat ing Temper ature (po wer applie d) T Storage Temperature T

Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up.

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal oper ation is not g uaran teed a t thes e extre mes.

IND

stg

-0.3 VD+ V

-55 125

-65 150

10 mA

RECOMMENDED OPERATING CONDITIONS

(GND = 0V; all voltages with respect to ground)

Parameter Symbol Min Typ Max Units

DC Voltage VD+ 4.5 5.0 5.5 V Supply Current Note 2 I Ambient Ope rating Temper ature: CS8401/2A-C P or - CS Note 3 T

CS8401/2A-IP or -IS -40 85

Power Consumption Note 2 P

Notes: 2. Drivers open (unlo aded). The ma jority of pow er is used in the load con nected to th e drivers.

3. The ’-CP’ and ’-CS’ pa rts are spec ified to ope rate over 0 to 70 °C but are tested at 25 °C only. The ’-IP’ and ’-I S’ parts are te sted over the full -40 to 85 °C temperature range.

02570

1.5 5 mA

7.5 25 mW

DIGITAL CHARACTERISTICS

(TA = 25 °C for suffixes ’CP’ & ’CS’, TA = -40 to 85 °C for ’IP’ & ’IS’; VD+ = 5V ± 10%)

Parameter Symbol Min Typ Max Units

High-Level Input Voltage V Low-Level Input Voltage V High-Level Output Voltage (IO = 200µA) V Low-Level Ou tput V oltage (IO = 3.2mA) V Input Leakage Current I Master Clock Frequency: CS8401A Note 4 MCK 22 MHz

CS8402A Note 4 7.1 M Hz

Master Clock Duty Cycle CS8401/2A 40 60 %

Notes: 4. MCK for the CS8401 must be 128, 192, 256, or 384× the input word rate based on M0 and M1 in control register 2. MCK for the CS8402A must be 128× the input word rate, except in Transparent Mode where MCK is

256x the input word rate.

Specifications are subject to change without notice.

2 DS60F1

2.0 VDD+0.3 V

-0.3 +0.8 V

VDD-1.0 V

0.4 V

1.0 10

CS8401A CS8402A

DIGITAL CHARACTERISTICS - RS422 DRIVERS

(TXP, TXN pins only; VD+ = 5V ±10%)

Parameter Symbol Min Typ Max Units

Output High V oltag e IOH = -30 mA V Output Low Voltage IOL = 30 mA V

VD+- 0.7 VD+ - 0.4 V

0.4 0.7 V

SWITCHING CHARACTERISTICS - CS8401A PARALLEL PORT

(TA = 25 °C for suffixes ’-CP’ and ’-CS’; TA = -40 to 85 °C for suffixes ’-IP’ and ’-IS’)

Parameter Symbol Min Typ Max Units

ADDRESS valid to CS low t CS high to ADDRESS invalid t RD/WR valid to CS low t CS low to RD/WR invalid t CS low t DATA valid to CS rising RD/WR low (writing) t CS high to DATA in valid RD/WR low (writing) t CS falling to DATA valid RD/WR high (reading) t CS rising to DATA Hi-Z RD/WR high (reading) t

adcss csadh rwcss

csrwi

csl dcssw csdhw

csddr csdhr

13.5 ns 0ns

10 ns 35 ns 35 ns 32 ns

0ns

5ns

35 ns

A4 - A0

RD/WR

Writing

D7 - D0

RD/WR

Reading

D7 - D0

adcss

csl

csddr

csrwi

rwcss

CS8401A Parallel Port Timing

dcssw

csadh

csdhw

csdhr

DS60F1 3

SWITCHING CHARACTERISTICS - SERIAL PORTS

(TA = 25 °C for suffixes ’-CP’ and ’-CS’; TA = -40 to 85 °C for suffixes ’-IP’ and ’-IS’; Inputs: Logic 0 = GND, logic 1 = VD+; C

Parameter Symbol Min Typ Max Units

SCK Frequency Master Mode Notes 5,6 t

Slave Mode Note 6 12.5 MHz

= 20 pF)

sckf

CS8401A CS8402A

IWR×64 Hz

SCK Pulse Width Low Slave Mode Note 6 t SCK Pulse Width High Slave Mode Note 6 t SCK rising to FSYNC edge delay Notes 6,7 t SCK rising to FSYNC edge setup Notes 6,7 t SDATA valid to SCK rising setup Note 7 t SCK rising to SDATA hold time Note 7 t

sckl

sckh

sfds

sfs sss ssh

25 ns 25 ns 20 ns 20 ns 20 ns 20 ns

C, U, V valid to SCK rising setup CS8402A

non-CD Mode Notes, 7,8 t

css

0ns

SCK rising to C, U, V hold time CS8402A

non-CD mode Notes 7, 8 t U valid to SBC rising setup CS8402A, CD mode Note 8 t SBC rising to U hold time CS8402A, CD mode Note 8 t

scs uss

suh

50 ns

0ns

80 ns

RST Pulse Width CS8402A 150 ns

Notes: 5. The input word rate, IWR, refers to the frequency at which stereo audio input samples are input to

the part. (A stere o pair is two au dio sample s.) Theref ore, in Maste r mode, the re are always 32 SCK periods in one audio sa mple.

6. Master mode is defined as SCK and FSY NC being ou tputs. In Sla ve mode they are inputs . In the CS8401A, control reg. 3 bit 1, MSTR, se lects mast er. In the CS8402 A, only form at 0 is master.

7. The table ab ove assume s data is outp ut on the fall ing edge and latched on the r ising edge . In both parts the edge is selectable. The table is defined for the CS8401A with control reg. 3 bit 0, SCED, set to one, and for the CS 8402A in for mats 4 thro ugh 7. F or the other format s, the table a nd fig ure edg es must be rever sed (i e. "ris ing" t o "falli ng" an d vice versa) .

8. The diagr ams show SB C rising coi ncident wit h the first rising edge of SCK after FSYNC transi tions. This is true for all modes except FSF0 & 1 both equal 1 in the CS8401A, and format 4 in the CS8402A. In these modes SBC is delayed one full SCK period.

FSYNC

sfs

SCK

SDATA

sfds

sss

sckh

sckl

ssh

Serial Input Timing - Slave Mode

4 DS60F1

FSYNC

CS8401A CS8402A

CS8402A

non-CD mode

CD mode

SCK

SDATA

C,U,V

SBC

sfds

sss

css

uss

sfs

ssh

sch

suh

sckf

Serial Input Timing - Master Mode & C, U, V Port

Audio

Data

Processor

Audio Data

Processor

Micro-

controller

+5V

Clock

External

5 k

7 6 8

15 14 16

FSYNC SCK SDATA INT

CS RD/WR

MCK

CS8401A

VD+

GND

TXP

A0 - A4

D0 - D7

TXN

Figure 1. CS8401A Typical Connection Diagram

+5V

0.1 uF

Transmitter

Circuit

See Appendix B

DS60F1 5

CS8401A CS8402A

Audio

Data

Processor

Micro-

controller

unused

Channel

Status Bits

Control

External

Clock

7 6 8

15 10 11

9 16

MCK

FSYNC SCK SDATA

CBL

CS8402A

C U V RST

8 Dedicated C.S. Bits

+5V

VD+

GND

TRNPT

M2 M1 M0

TXP

TXN

18 24

23 22 21

0.1 uF

Serial Port

Mode Select

Transmitter

Circuit

See Appendix B

Figure 2. CS8402A Professional & Consumer Modes Typical Connection Diagram

Audio

Data

Processor

Decoder

Subcode

Port

Reset

Control

Channel

Status Bits

Control

FSYNC

SCK

SDATA

SBF

SBC

RST

8 Dedicated C.S. Bits

External

Clock

MCK

CS8402A

+5V

VD+

GND

M2 M1 M0

TXP

TXN

0.1 uF

23 22 21

See Appendix B

Serial Port

Mode Select

Transmitter

Circuit

Figure 3. Consumer CD Submode Typical Connection Diagram

6 DS60F1

CS8401A CS8402A

GENERAL DESCRIPTION

The CS8401A/2A are monolithic CMOS circuits that encode and transmit audio and digital data according to the AES/EBU, IEC 958 (S/PDIF), and EIAJ CP-340 interface standards. Both chips accept audio and control data separately; multiplex and biphase-mark encode the data internally; and drive it, directly or through a tran sfo rme r, to a tra nsm iss ion lin e. T he CS8401A is fully software programmable through a parallel port and contains buffer memory for control data, while the CS8402A has dedicated pins for the most important control bits and a serial input port for the C, U, and V bits.

Familiarity with the AES/EBU and IEC 958 specifications are assumed throughout this data sheet. Many terms such as channel status, user data, auxiliary data, professional mode, etc. are not defined. The Application Note, Overview of AES/EBU Digital Audio Interface Data Structures, provides an overview of the AES/EBU and IEC 958 specifications and is included for clarity; however, it is not meant to be a complete reference, and the complete standards should be obtained from the Audio Engineering Society or ANSI for the AES/EBU document, and the International Electrotechnical Commission for the IEC document.

Line Drivers

CS8401A DESCRIPTION

The CS8401A accepts 16- to 24-bit audio samples through a configurable serial port, and channel status, user, and auxiliary data through an 8-bit parallel port. The parallel port allows access to 32 bytes of internal memory which is used to store control information and buffer channel status, user, and auxiliary data. This data is multip lexed with the audio data from the serial port, the parity bit is generated, and the bit stream is biphase-mark encoded and driven through an RS422 line driver. A block diagram of the CS8401A is shown in Figure 4. In accordance with the professional definition of channel status, the CRCC code (C.S. byte 23) can be internally generated.

Parallel Port

The parallel port accesses one status register, three control registers, and 28 bytes of dual port buffer memory. The address bus, and RD/WR line must be valid w he n CS goes low. If RD/WR is low, the value on the data bus wi ll be written into the buffer memory at the specified address. If RD/WR is high, the value in the buffer memory, at the specified address, is placed on the data bus. The detailed timing for reading and writing the CS8401A can be found in the Digital Switching Characteristics table. The memory space is allocated as shown in Figure 5. There are three defined buffer memory modes selectable by two bits in control register 2.

The RS422 line drivers for both the CS8401A and CS8402A are low skew, low impedance, dif-

ferential outputs capable of driving 110 Ω transmission lines with a 4 volt peak-to-peak signal when configured as shown in Appendix A. To prevent possible short circuits, both drivers are set to ground when no master clock (MCK) is provided. They can also be disabled by reset-

Status and Control Registers

Upon power up the CS8401A control registers contain all zeros. Therefore, the part is initially in reset and is muted. One’s must be written to control register 2, bits RST and MUTE, before the part will transmit data. The remaining regis-

ters are not initialized on power-up and may contain random data.

ting the device (RST = low). Appendix A contains more information on the line drivers. A

0.1 µF capacitor, with short leads, should be placed as close as possible to the VD+ and GND pins.

DS60F1 7

The first register, shown in Figure 6, is the status register in which only three bits are valid. The lower three bits contain flags indicating the position of the transmit pointer in the buffer memory. These flags

CS8401A

INT

8 6 7

21-24, 1-4 9-13

14 16

Interrupt

Control

Read

Address

Generator

Serial

Port

Logic

Control

and Flags

4 X 8

Buffer

Memory

28 X 8

Figure 4. CS8401A Block Diagram

SDATA

SCK FSYNC D0-D7

A4-A0

RD/WR

may be used to avoid contention between the transmit pointer reading the data and the user updating the buffer memory. Besides indicating the byte location being transmitted, the flags indicate the block of memory the part is currently addressing, thereby telling the user which block is free to be written to. Each flag has a corresponding mask bit (control register 1) which, when set, allows a transition on the flag to generate a pulse on the interrupt pin. Flag 0 and flag 1 cause interrupts on both edges whereas flag 2 causes an interrupt only on the rising edge. Timing and further explanation of the flags can be found in the buffer memory section.

The two most significant bits of control register 1, BKST and TRNPT, are used for Transparent Mode operation of the CS8401A. Transparent Mode is used for those applications where it is useful to maintain frame alignment between the received and transmitted audio data signals. In Transparent Mode (TRNPT = "1") the MCK, FSYNC, SCK and SDATA inputs of the CS8401A can be connected to their corresponding outputs of the CS8411. In Transparent Mode, FSYNC synchronizes the transmitter and the receiver. The data delay through the CS8401A

Audio

Aux

C Bits

CRC

U Bits

Validity

Preamble

Parity

Mux

Biphase

Mark

Encoder

Timing

Driver

IMCK

Prescaler

MCK

Line

TXP TXN

is set so that three frame delays occur from the input of the CS8411 to the output of the CS8401A. In Transparent Mode, 32 SCK’s are required per subframe.

Channel status block alignment between the CS8411 and the CS8401A is accomplished by setting BKST high at the occurrence of the Flag 2 rising edge of the CS8411. If FSYNC is a left/right signal, BKST is sampled once per frame; if FSYNC is a wo rd clock, BKST is sampled once per subframe. A low to high transition of BKST (based on two successive internal samples) resets the channel status block boundary to the beginning.

Control register 2, shown in Figure 8, contains various system level functions. The two most significant bits, M1 and M0, select the frequency at the MCK pin as shown in Table 1. As an example, if the audio sample frequency is 44.1 kHz and M0 and M1 are both zero, MCK would then

be 128× the audio sample rate or 5.6448 MHz. The next bit (5) in control register 2, V, indicates the validity of the current audio sample. According to the

8 DS60F1

digital audio specifications, V = 0 signifies the audio signal is suitable for conversion to analog. B1 and B0 select one of three modes for the buffer memory. The different modes are shown in Figure 5 and the bit combinations in Table 2. More information on the different modes can be found in the Buffer Memory section. Bit 2, CRCE, is the channel status CRCC enable and should only be used in professional mode. When CRCE is high, the

0 1 2 3 4 5 6 7 8

1st Four

Bytes of

C. S. Data

B C

R E S S

10 11 12 13 14 15 16 17 18

19 1A 1B 1C 1D 1E

20 Bytes

Channel

Figure 5. CS8401A Buffer Memory Modes

Status register 0 Control Register 1 Control Register 2 Control Register 3

User Data

1st Four Bytes of

C. S. Data

Last

Status

Data

Auxiliary

Data

0123

Memory Mode

1st Four Bytes of

Left C. S.

Data

Left C. S. Data

1st Four Bytes of

Right

C. S. Data

Right

C. S. Data

U N D E F I N E D

CS8401A

X:00

FLAG2: High for first four bytes of channel status FLAG1: Memory mode dependent - See figure 11 FLAG0: High for last two bytes of user data.

Figure 6. Status Regist er

X:01 BKST: Causes realignment of data block when set to "1".

TRNPT: Selects Transparent Mode appropriately setting data MASK2: Interrupt mask for FLAG2. A "1" enables the interrupt.

MASK1: Interrupt mask for FLAG1. MASK0: Interrupt mask for FLAG0.

delay through device

Figure 7. Contro l Re gister 1

X:02 M1: with M0, selects MCK frequency.

M0: with M1, selects MCK frequency. V: Validity bit of current sample. B1: with B0, selects the buffer memory mode. B0: with B1, selects the buffer memory mode. CRCE: Channel status CRC Enable. Professional mode only. MUTE: When clear, transmitted audio data is set to zero. RST: When clear, drivers are disabled, frame counters cleared.

Figure 8. Contro l Re gister 2

M1 M0 MCLK

00128 01192 10256 11384

Input Word Rate

Table 1. MCLK Frequencies

B1 B0 Mode Buffer Memory Contents

0 0 0 Channel Status 0 1 1 Auxiliary Da ta 1 0 2 Independent Channel Status 1 1 3 Reserved

Table 2. Buffer Memory Modes

MASK0MASK1MASK2TRNPTBKST

01234567

FLAG0FLAG1FLAG2

01234567

RSTMUTECRCEM0M1 V B1 B0

DS60F1 9

CS8401A

channel status data cyclic redundancy check characters are generated independently for channels A and B and are transmitted at the end of the channel status block. When MUTE (bit 1) is low, the transmitted audio data is forced to zero. Both RST and MUTE are set to zero upon power up.

When RST is low, the differential line drivers are set to ground and the block counters are reset to the beginning of the first block. In order to properly synchronize the rest of the CS8401A to the audio serial port, the transmit timing counters, which include the flags in the status register, are not enabled after RST is set high until eight and one half SCK periods after the active edge (first edge after reset is exited) of FSYNC.

When FSYNC is configured as a left/right signal (FSF1 = 1), the counters and flags are not enabled until the right sample is being entered (during which the previous left sample is being transmitted). This guarantees that channel A is left and Channel B is right as per the digital audio interface specs.

of the formats delineate each channel’s data and do not indicate the particular channel. The other two formats also indicate the specific channel. The formats are shown in Figure 10. Bit 1, MSTR, determines whether FSYNC and SCK are inputs, MSTR low, or outputs, MSTR high. Bit 0, serial clock edge select, SCED, selects the edge that audio data gets latched on. When SCED is low, the falling edge of SCK latches data in the chip and when SCED is high, the rising edge is used.

The multitude of combinations allow for a zero glue logic interface to almost all DSP’s, encoder chips, and standard serial data formats.

Serial Port

The serial port is used to enter audio data and consists of three pins: SCK, SDATA, and FSYNC. The serial port is double buffered with SCK clocking in the data from SDATA, and FSYNC delineating audio samples and may define the particular channel, left or right.

Control register 3 contains format information for the serial audio input channel. The MSB is unused and the next three bits, SDF2-SDF0, select the format for the serial input data with respect to FSYNC. There are five valid combinations of these bits as shown in Figure 10. The next two bits, FSF1 and FSF0, select the format of FSYNC. Two

01234567

X:03 SDF2: with SDF0 & SDF1, select serial data format.

SDF1: with SDF0 & SDF2, select serial data format. SDF0: with SDF1 & SDF2, select serial data format. FSF1: with FSF0, select FSYNC format. FSF0: with FSF1, select FSYNC format. MSTR: When set, SCK and FSYNC are outputs. SCED: When set, rising edge of SCK latches data.

When clear, falling edge of SCK latches data.

SDF1

Figure 9. Contro l Re gister 3

SCEDMSTRFSF0SDF2 SDF0 FSF1

Control register 3, shown in Figure 9, configures the serial port. All the various formats are illustrated in Figure 10. When FSF1 is low, FSYNC only delineates audio samples. When FSF1 is high, it delineates audio samples and specifies the channel. When FSF1 is low and the port is a master (MSTR = 1), FSYNC is a square wave output. When FSF1 is low and the port is a slave (input), FSYNC can be a square wave or a pulse provided the active edge, as defined in Figure 10, is properly positioned with respect to SDATA.

Bits 4, 5, and 6, SDF0-SDF2, define the format of SDATA and is also described in Figure 10. The five allowable formats are MSB first, MSB last, 16-bit LSB last, 18-bit LSB last, and 20-bit LSB last. The MSB first and MSB last formats accept any word length from 16 to 24 bits. The word length is controlled by providing trailing zeros in MSB first mode and leading zeros in

10 DS60F1

CS8401A

SDF 210 (bit)

000

001

010

100

110 FSF

10 (bit) 00

01 10 11

Name MSB First

MSB Last

LSB Last 16

LSB Last 18

LSB Last 20

MSTR

FSYNC Input

FSYNC Output

Left Sample

MSB LSB MSB LSB MSB

LSB LSBMSB LSBMSB

LSB

24 bits, incl. Aux 24 bits, incl. Aux

16 Bits

18 Bits

20 Bits

MSB LSB MSB LSB

16 Clocks 16 Clocks

32 Clocks 32 Clocks

Right Sample

16 Bits

18 Bits

20 Bits

FSYNC Output

32 Clocks

Figure 10. CS8401A Serial Port SDATA and FSYNC Timing

MSB last mode, or by restricting the number of SCK periods between samples to the sample word length. The 16-, 18-, and 20-bit LSB-last modes require at least 16, 18, or 20 SCK periods per sample respectively. As a master, 32 SCK periods are output per sample.

FSYNC must be derived from MCK via a DSP using the same clock or by external counters. If FSYNC moves (jitters) with respect to MCK by more than 4 MCK periods, the CS8401A may reset the channel status block and flags. Appendix C contains more information on the relationship of FSYNC and MCK.

Buffer Memory

In all buffer modes, the status register and control registers are located at addresses 0-3

32 Clocks

respectively, and the user data is buffered in locations 4-7. The parallel port can access any location in the user data buffer at any time; however, care must be taken not to modify a location when that location is being read internally. This internal reading is done through the second port of the buffer and is done in a cyclic manner.

Reset initializes the internal pointer to 04H (Hex). Data is read from this location and stored in an 8-bit shift register which is shifted once per audio sample. (An audio sample is defined as a single channel, not a stereo pair.) The byte is transmitted LSB first, D0 being the first bit. After transmitting 8 samples, i.e. 8 user bits, the address pointer is incremented and the next byte of user data is loaded into the shift register. After transmitting all four bytes, 32 audio sam-

DS60F1 11

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