Cirrus Logic CS7666-KQ Datasheet
CS7666
Digital Color-Space Processor for CCD Cameras
Features
l
ITU-601 Compliant Image Formatting
l
ITU-656 and SMPTE-125/M Transport
l
Provides Separate HREF and VREF (or
alternately HSYNC and VSYNC) Signals
l
I2C Control Interface
l
Limited Secondary I2C Bus Master
l
Automatic White Balance
l
Programmable Gamma Correction
l
Programmable Interpolation
l
Programmable Luma Gain and Saturation
Control
l
Fully Programmable Color Separation Matrix
Coefficients
l
Supports up to 1440, active pixels per line,
with no limitation on Vertical Size
l
Pin and software compatible with the CS7665
l
Programmable "Color Killer" circuit
l
Highly integrated for low part count cameras
I
Description
The CS7666 is a low-power Digital Color-Space Processor for CCD cameras. It provides all necessary digital
image processing for standard four-color interline transfer CCD imagers. The CS7666 processes the magenta,
yellow, cyan, and green (MYCG) CCD imager data into
YCrCb formatted component digital video. Internal processing includes color separation, automatic white
balance, user programmable gamma correction, programmable scaling (interpolation), and output
formatting. Also, a special "Co lor Killer " circuit eliminates
false colors during saturation. The digital output of the
CS7666 can be configured to comply with the ITU-601,
ITU-656 and SMPTE-125/M standards. Additionally,
HREF and VREF (or HSYNC and VSYNC) output pins
are provided to support older analog video encoders and
the current ZV-Port defi nition.
The CS7666 is designed to work directly with the
CS7615 CCD Imager Analog Process or, a nd i s a dro p in
replacement for the CS7665.
ORDERING INFORMATION
CS7666-KQ 0° to 70° C 64-pin TQFP
(10 mm x 10 mm x 1.4 mm)
CCD
DATA
SECONDARY
2
I
C BUS
DEFORMATTER
I2C INTERFACE
PRIMARY
I2C BUS
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
COLOR SEPARATION
AND ANITALIASING
GAMMA
CORRECTION
REGISTER PLL AND OUTPUT
BLOCK CLOCK DRIVER TIMING
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1998
WHITE
BALANCE
SCALER
XTAL
(All Rights Reserved)
AWB
CONTROL
OUTPUT
FORMATTER
YCrCb
DATA
VREF/VSYNC
HREF/HSYNC
JUL ‘98
DS302PP1
1
TABLE OF CONTENTS
CHARACTERISTICS AND SPECIFICATIONS ...................................................3
DIGITAL CHARACTERISTICS.................................................................... 3
SWITCHING CHARACTERISTICS ............................................................. 3
POWER CONSUMPTION ........................................................................... 3
CONTROL PORT CHARACTERISTICS.....................................................4
RECOMMENDED OPERATING CHARACTERISTICS...............................5
ABSOLUTE MAXIMUM RATINGS ..............................................................5
GENERAL D E SC R IPTION .................................. ....................................... ......... 6
Overview ......... ......... ....... ......... ......... .......... ...... .......... ......... ....... ......... ....... 6
The 640 Pixel Horizontal Line .....................................................................7
Embedded ITU-656 EAV and SAV Timing ...............................................10
Individual Timing and Synchronization Signals ........................................11
HREFOUT /HSYNC ......... ....... ......... ......... ......... ....... .......... ......... ....... ....... 11
VREFOUT/VSYNC ................................................................................... 11
Digital Output Formats ..............................................................................11
Internal Horizontal Scaler .........................................................................14
CLKIN and CLKIN2X Input Timing ...........................................................14
CLKOUT ................................................................................................... 15
INTERNAL PROCESSING ................................................................................15
Input Data Format and Chroma Separator ...............................................15
Color Saturation Control ........................................................................... 15
White Balance and Gamma Correction .............................. ......................15
Chroma K ill ................. ............................. ....................................... .......... 16
Internal Filters ...........................................................................................16
INTERNAL REGISTER STRUCTURE AND USER INTERFACE .....................16
Operating CS7666 in Normal I2C Configuration (Three-Byte Mode) .......16
Station Address ..................................................................................17
Write Operations in Three-Byte Mode ................................................17
Address S e t O p e ra ti o n .. ............................. ....................................... . 17
Read Operations in Three-Byte Mode ...............................................17
Operating CS7666 in Four-Byte I2 C Confi guration ................. ...........17
Write Operations in Four-Byte mode ..................................................18
Read Operations in Four-Byte Mode .................................................18
Initializing Slave Devices on Secondary I2C bus from an EPROM ..........19
Controlling the Configuration Process ......................................................19
Reserved Registers and Test Pins ...........................................................20
PIN DESCR I P T IO N S ................................. ....................................... ................. 34
Power Supp ly Connec t io n ... ....................................... ............................. . 34
Input Data and Clocks ...................................................................... .. ......35
I2C Serial Control ..................................................................................... 35
Digital Video Outputs and Clocking ..........................................................36
Miscellaneous ........................................................................................... 38
DEFINIT IONS .. ....... ....... .... ....... ....... ....... .... ....... ....... ..... ....... ....... ...... ..... ....... ..... 39
PACKAGE DIMENSIONS ..................................................................................40
CS7666
2 DS302PP1
CS7666
CHARACTERISTICS AND SPECIFICATIONS
DIGITAL CHARACTERISTICS
(TA = 25 °C; VDD = 5 V; CL = 30 pF; Input Levels: logic 0 = 0 V, logic 1 = VDD.)
Parameter Symbol Min Typ Max Unit
Logic Inputs
High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I
Input Pin Capacitance C
IH
IL
IN
DI
Input Clamp Voltage - -0.7 - V
Logic Outputs
High-Level Output Voltage @ IOH = 2mA V
Low-Level Output Voltage @ I
= 2mA V
OL
High-Z Leakage Current I
OH
OL
Z
VDD - 0.8 - - V
--0.8V
- - 10.0 µA
-10-pF
VDD - 0.4 - - V
0.4 - - V
- - 10.0 µA
SWITCHING CHARACTERISTICS
(TA = 25 °C; VDD = 5 V; CL = 30 pF; Input Levels: logic 0 = 0 V, logic 1 = VDD.)
Parameter Symbol Min Typ Max Unit
Digital Input
CLKIN2X Frequency Range (Note 1) f
Input Data setup time, DI[9:0] t
Input Data hold time, DI[9:0] t
CLK2X
S1
H1
Digital Output
Channel A/B Digital Data Output Clock Interleaved Dat a
f
CLKOUT
Parallel Data
Channel A/B Output Hold Time t
Channel A/B Output Propag ation Delay t
Digital Output Rise Time with 30 pF load t
Digital Output Fall Time with 30 pF load t
Notes: 1. CLKIN, f
CLK
, is f
/2 in non-interpolat ed mode and f
CLK2X
OH
PD
R
F
* 2/5 in interpolated mode.
CLK2X
POWER CONSUMPTION
(TA = 25 °C; VDD = 5 V; CL = no load; Input Levels: logic 0 = 0 V, logic 1 = VDD.)
Parameter Symbol Min Typ Max Unit
Normal Mode I
Low Power Mode I
DD
DD
--30MHz
5--ns
5--ns
-
-
-
-
30
15
MHz
MHz
-0-ns
-1.95ns
-15-ns
-15-ns
- 80 100 mA
-716mA
Specifications are subject to change without notice
DS302PP1 3
CLKIN2X
CLKIN
Mosaic
Input Data
DI[9:0]
CLKOUT
Output Data
DOA[9:0]
DOB[9:0]
CS7666
t
H2
t
S2
t
t
H1
S1
Input Timing Diagram
t
PD
t
OH
Output Timing Diagram
CONTROL PORT CHARACTERISTICS
(TA = 25 °C; VDD = 5 V; Input Levels: logic 0 = 0 V, logic 1 = VDD.)
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Bus Free Time Between Transmissions t
St art Condition Hold Time t
Clock Pulse Width High
Low
Setup Time for Repeat Star t Condition t
SDAIN Hold Time from SCL Falling t
SDAIN Setup Time from SCL Rising t
SDAIN and SCL Rise Time t
SDAIN and SCL Fall Time t
Setup Time for Stop Condition t
Stop Start
SDA
SCL
t
buf
t
hdst
t
high
SCL
buf
hdst
t
high
t
low
sust
hdd
sud
r
f
susp
Repeated
Start
-400kHz
1.3 - µs
0.6 - µs
0.6
1.3
-
-
µs
µs
0.6 - µs
0-µs
0.1 - µs
-1.0µs
-0.3µs
0.6 - µs
Stop
t
hdst
t
f
t
susp
t
low
t
hdd
t
sud
t
sust
t
r
I2C Timing Diagram
4 DS302PP1
CS7666
RECOMMENDED OPERATING CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Power Supply Voltage V
DD
Ground to Ground Voltage Differential - - 10 mV
Digital Input Rise/Fall Time - - 10 ns
CLKIN Level Setup to CLKIN2X Rising (non-interpolated) t
CLKIN Level Hold after CLKIN2X Rising (non-interpolated) t
S2
H2
Digital Input Voltage Range 0 - V
Operating Temper ature Range T
A
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
Power Supply Voltage V
Digital Input Voltage Range GND - 0.3 V
Forced Digital Output Current - 50 mA
Sustained Digital Output Voltage GND - 0.3 V
Output Short Circuit Current - - mA
Operating Temper ature Range T
Lead Solder Temperature (10 s duration) - +260 °C
Storage Temperature Range -65 +160 °C
DD
A
4.5 5.0 5.5 V
8--ns
8--ns
DD
0-70°C
-0.3 7.0 V
+ 0.3 V
DD
+ 0.3 V
DD
070°C
V
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
DS302PP1 5
CS7666
GENERAL DESCRIPTION
Overview
The CS7666 forms the hea rt of a fo ur chip dig ital
CCD Camera. The four chips include the CCD imager, the CS7615 CCD digitizer, the CS7666 color
space proces s or, and a vertical drive in terface-chip
for the CCD image r. Most four-phase C CD imagers (and their associated vertical drives) can be
used with the CS7615 digitizer and the CS7666
processor to form a simple and cost-effective
YCrCb output format digi tal ca mera. The CS7615
and CS7666 together support imager formats rang-
ing from 175× 175 pixels up to 1 000x1000 pixels.
Timing control is located in the CS7615 analog
processor, while the CS7666 synchronizes itself by
decoding the timing cues embedded in the CS7615
data stream. Al terna tel y, th e CS 7666 a ccep ts hori zontal and vertical timing signals on pin inputs.
The block dia gram i n Figure 1 illustra tes a typ ical
system interconnect.
CS7666
Image
Processor
+5V
6
Vertic al
Drive
CCD
512x480
+18V to +12 V
Timing
6
CS7615
CDS/ADC
I2C I2C
CCD
Bias
Figure 1. Typical 4-Chip Digital CCD Camera
CS4954
Video
Codec
2
C
2
I
Bus
The CS7666 is a CCD camera color separation and
color-space processor designed to process the fourcolor mosai c CCD image r data into ITU-601 compliant 4:2:2 YCr Cb digital component vi deo. The
CS7666 timing control is based on the built-in crystal oscillator or on the master clock provided by the
CS7615, and provides formatted component digital
video compliant with SMPTE-125 and ITU-656
transport protocols.
The CS7666 prov ides co lor separa tion of stand ard
MYCG chroma blo ck data from in dustry standard
four-color CCD imagers. Gamma correction and
white balance adjustment functions are also included in the CS7666. The YCrCb (luminance and
chrominace) data is output at the scaled CCD pixel
rate in 20 -bit format, or at twic e the scaled pixel
rate in 10-bit format (see discussion on Digital Output Formats). The YCrCb output data from the
CS7666 confo rms to t he ITU-65 6 parall el com ponent digital video recommendation with embedded
synchronization (see Embedded EAV and SAV
discussion). External horizontal and vertical synchronization signals are also provided to support
ITU-601 interfaces, as well a s t he PC-Card Zoom Video standard being used in notebook computers.
The CS7666 incorporates an internal horizontal
scaler which may be turned on to increase the horizontal pixel count of the popular 360 (CIF) and 512
horizontal pixe l per line imagers. The most com -
CCD
DATA
SECONDARY
2
I
C BUS
DEFORMATTER
I2C INTERFACE
PRIMARY
I2C BUS
COLOR SEPARATION
AND ANITALIASING
GAMMA
CORRECTION
REGISTER PLL AND OUTPUT
BLOCK CLOCK DRIVER TIMING
WHITE
BALANCE
SCALER
XTAL
AWB
CONTROL
OUTPUT
FORMATTER
YCrCb
DATA
VREF/VSYNC
HREF/HSYNC
Figure 2. CS7666 Block Diagram
6 DS302PP1
CS7666
mon target resolutions for the scaler are 640 and
720 pixels per line (square and rectangular pixel
formats), but it is possible to pro vide gener ic scaling of M/N where M and N are values from 1 to 31.
The CS7615 and CS 7666 chip set supports a wide
range of imager form ats while providi ng an output
format that fol lows the IT U-601 C ompon en t Digi tal Video recommendation. The ITU-601 document primarily spe cifies horizontal resolutions o f
720 active h orizonta l pixels (which i s require d for
broadcast television compatibility). However,
many of today’s digital video receivers are capable
of operatin g wi th a wide range of vi deo image formats. Even th ough the se dig ital video rec eive rs allow image formats not specified in the ITU601/656 recommendation, all of these receivers expect the basic ITU-601/656 protocol to be followed
in terms of data seque nce an d timin g cue s. Th is is
the case with the CS7666, where all output formats
follow the ITU-601/656 recommendation even if
the image form ats differ in ho rizontal and ve rtical
pixel dimensi ons.
The 640 Pixel Horizontal Line
The following di scussion assumes th at a 512 horizontal pixel class ima ger has be en sel ected for t he
camera, the CS 7615 h as b een progra mme d to pro vide 512 ac ti ve pixels an d 112 inacti ve pixels, and
that the intern al 4 :5 h orizonta l sca ler ha s bee n en -
abled (scaler mode 1). Many other imager/scaler
combinations are possible, but the digital video format would not be significantly different than the
640x480 case described.
Transmitte d durin g each active line a re 1280 multiplexed luminance and chrominance values (640
luminance, 320 chrominance Cr, and 320 chrominance Cb values). Eight of the remaining 280 interface clock intervals are used to transmit
synchronizing i nforma tion . The first of th ese 156 0
interface clock intervals is designated line 0 word 0
for the purpose of reference only. The 1560 sample
words per total line are therefore numbered 0
through 1559. Interva ls 0 through 1279, inc lusive,
contain vid eo data.
The inte rface clock intervals o cc urring durin g digital blanking are designated 1280 through 1559. Intervals 1280 through 1283 are reserved for the endactive-video (EAV) timing reference. Intervals
1556 through 1559 are reserved for the start-of-active-video (SAV ) timing reference. Figure 3 indicates the val ues of th e ti ming re fere nce si gnal s (F,
V, H) for an entire frame of interlaced video. Please
note the scan lines are numbered 1 through 525
consecutively in the time domain (spatially they are
interlaced ). Table 1 defines t he 1560 samples of a
single scan line of video.
DS302PP1 7
CS7666
Lines 1 to 19 V=1
Lines 20 to 263
V=0
Lines 264 to 282 V=1
Lines 283 to 525
V=0
EAV
H=1
640
SAV
H=0
Vertical Blanking
Active Vid e o
Field 1
Blanking
Horizontal
Vertical Blanking
Active Vid e o
Field 2
Blanking
Horizontal
0
779
Figure 3. Horizontal and Vertical Timing States
(640×480 resolution)
F=0
Lines
4 to 265
F=1
Lines
266 to 3
639
8 DS302PP1
CS7666
Word Data Content Pixel Notes
1280 1111 1111 640 EAV
1281 0000 0000 EAV
1282 0000 0000 EAV
1283 1FV1 P3P2P1P0 641 EAV
1284 1000 0000 642 Fro pixels 642 to 777
1285 0001 0000
1286 1000 0000
1287 0001 0000 643
1552 1000 0000 776
1553 0001 0000
1554 1000 0000
1555 0001 0000 777
1556 1111 1111 778 SAV
1557 0000 0000 SAV
1558 0000 0000 SAV
1559 1FV0 P3P2P1P0 779 SAV
0 Cb0 0 St a rt of Digital Vide o
1 Y0 For VBLANK line 1 to 19
2Cr0
3Y1 1
4Cb2 2
5Y2
6Cr2
7Y3 3
2n Cbn n For active pixels 20
2n + 1 Yn
2n + 3 Crn
Yn+1 n+1
1272 Cb636 636
1273 Y636
1274 Cr636
1275 Y637 637
1276 Cb638 638
1277 Y638
1278 Cr638
1279 Y639 End of Digital VIdeo
Table 1. Detail of Scan Line for 640x480 Image
Cr = Cb = 80h
Y = 10h
and 264 to 283
Cr = Cb = 80h
Y = 10h
through 263 and 283 to
525 for n=even from pix-
els 0 to 638
DS302PP1 9
CS7666
Embedded ITU-656 EAV and SAV Timing
The lines in Figure 3 are numbe red 1 through 525.
Video data is not present on lines 1 to 19 or 264 to
282, which constitute the vertical blanking periods.
The vertical blanking is in full line increments,
where Y samples are set to 10h, while Cb and Cr
samples a re set to 80h. The interval startin g with
EAV and ending with SAV is the digital horizontal
synchronizati on, whi ch occ urs on e ve ry line.
It is implicit that the timing reference signals are
contiguous with the video data and continue
through the vertical blanking interval. Each timing
reference signal consists of the four-word sequence
in Table 2 . The first three words are a preamble,
followed by a fourth wo rd indica ting a) even fie ld
(field 2) identification, b) state of vertical blanking,
and c) sta te of ho rizon tal blank in g. T able 1 deta ils
the timing reference format. The protected bit
states are dependent on the F, V, and H bits according to Table 3.
Value Description
First Byte FFh Fixed
Second Byte 00h Fixed
Third Byte 00h Fi xed
Fourth Byte xyh See Table 3
Table 2. Timing Reference Signal
Protected State Bits - In Ta bles 3 and 4, H, V, an d
F bits provide all the necessary timing and state information . Bits 0 to 3 provide error detection an d
correction information. The protection bits allow
for correction o f single-bit error s and detection of
two-bit errors. The F or field bit indicates which of
the interlaced fields is active, the first/odd field
which contai ns 262 l ines, or the sec ond/eve n fiel d
which contains 263 lines.
Bit Position Word 1281
and 1556
7 1001Fixed
6 1 0 0 F F = 0 during Field 1/ODDF = 1
5 1 0 0 V V = 0 during Active VideoV = 1
4 1 0 0 H H = 1 at end of Active VideoH = 0
3 1 0 0 P3 see Protected Bits State Table 4
2 1 0 0 P2 see Protected Bits State Table 4
1 1 0 0 P1 see Protected Bits State Table 4
0 1 0 0 P0 see Protected Bits State Table 4
Bit 7 Bit 6 (F) Bit 5 (V) Bit 4 (H) Bit 3 (P3) Bit 2 (P2) Bit 1 (P1) Bit 0 (P0)
10000000
10011101
10101011
10110110
11000111
11011010
11101100
11110001
Word 1281
and 1557
Table 3. EAV and SAV Timing Reference Signal Detail.
Table 4. EAV and SAV Protected Bit States Detail.
Word 1282
and 1558
Word 1283
and 1589
during Field 2/EVEN
during Vertical Blanking
at start of Active Video
Description
10 DS302PP1
CS7666
Individual Timing and Synchronization Signals
In addition to the embedded EAV and SAV timing
signals, the CS7666 provides individual synchronization output signals which are employed by many
video encode r circuits. T hese synch ronization signals are typically used to interface the ITU-656 digital video stream to other components and
subsystems. The individual synchronization signals include HREFOUT and VREFOUT.
HREFOUT/HSYNC
HREFOUT is an active-high signal indicating
when active pixel data is being transmitted on
DOA[9:0] or DOB[9:0]. HREFOUT is low whe n
non-active pi c ture d ata i s be ing tr an smi tted durin g
horizontal blanking. Depending on the mode of operation, the HREFOUT signal follows either the
HREFIN signal or the HREF defined by t he EAV
and SAV code.
The HREFOUT pin may also be configured to provide a HSYNC output tha t provides an active low
pulse for 64 pixel clocks whose falling edge occurs
16 pixel clocks after the end of active video for
NTSC (12 clocks for PAL) as per the ITU-R
BT.601 specification. HSYNC is chosen by setting
the Operation Control Register II (07h) HS_SEL
bit (bit 0) to a value of 1. This pin may be inverted
by setting the H_INV bit (register 07h bit2) to a
value of 1. Th e HSY NC signa l ma y be dela yed by
0, 0.5, 1, or 1.5 pixel clocks by setting H_SFT[1-0]
appropriately (register 07h bits 5 and 4.)
VREFOUT/VSYNC
VREFOUT is an output signal that is active high
when the CS7666 i s put ting out a ctiv e video l ines.
The active-low portion of this signal defines the
vertical bla nki ng period. If the VS_SEL bit i n register 07h is set, this output pin produc es a vertical
sync signal that i s com pati bl e with curr en t PAL or
NTSC analog systems. See Figure 4. This signal is
active for 3 line times in NTSC mode (bit 5 of register 04h = 0) and 2.5 line times in PAL mode (bit5
of register 0 4h = 1.) This line may be inverted by
setting the V_INV bit (register 07h) to a value of 1.
Alternate ly, wh en the ZV mod e bit in re giste r 06h
is set, this output behaves as a VSYNC signal appropriate for ZV ports. In the ZV mode, the
VSYNC signal is active-high during the first six
horizontal line periods of every field. The transition
in VSYNC signal lags the HREF signal’s rising
edge during odd fields a nd leads the rising edge of
HREF during even fi el ds.
Digital Output Formats
The CS7666 outputs data in a 20-Bit wide format at
the output pixel clock rate. Alternately, the data can
be multiplexed in a 10-bit format at a 2x output pixel clock rat e. Figures 5 and 6 detail the c lock and
data relationships. The output data transitions on
the falling edge of the clock such that the rising
edge of th e clock can be used to latc h the data i nt o
subsequent circuit ry.
The CS7666 del ivers 4:2: 2 compone nt digit al video output data in YCrCb format. The data conforms
to the ITU-R BT.656 specification. The Y component range is 16-235 (8-bit data) and the Cr and Cb
component ranges are 16-240 (8-bi t data). However, by setting CLIP_OFF (register 07h bit 6) to a
value of 1, the output data can be extended to a
range of 1-254 (8-bit data). Only 00 a nd FF are restricted to all o w digital timing codes.
The digital outputs can be configured for 10-bit interleaved Y and CrCb data, or for 20-bit parallel
operation. The INTERL bit of the Operational Control Register 06h determines which output format is
active. Logic 0 places the CS7666 in interleave
mode with output data on channel "A." Logic 1
places the CS7 666 in non -in terlea ve d mode where
luminance data is output on channel "A" and
chrominance data is ou tput on chann el "B."
DS302PP1 11
Line
HSYNC
NTSC Vert ical Timing (odd field)
525 1 2
3 4
5 6
7 8
CS7666
9 10
VSYNC
VSYNC ZV Mode
VREF
Line
HSYNC
VSYNC
VSYNC ZV Mode
VREF
Line
HSYNC
NTSC Vertical Timing (even field)
263 264 265 266 267 268 269 270 271 272 273
PAL Vertical Timing (odd field)
624 625 1
2 3
3H
9H
3H
9H
6H
4 5
6H
6 7
23
VSYNC
VSYNC ZV Mode
VREF
Line
HSYNC
VSYNC
VSYNC ZV Mode
VREF
PA L Vertical Timing (even field)
311 312 313 314 315 316 317 318 319 336
2.5H
6H
24H
2.5H
6H
25H
Figure 4. Vertical Timing
12 DS302PP1
24.5454MHz
CLKOUT
SAV
DO [9-0]
A
Line 3 Pixel 776
to Line 4 Pixel 3
DO [9-0]
A
Line 263 Pixel 638
to Line 264 Pix el 645
DO [9-0]
A
Line 525 Pixel 638
to Line 1 Pixel 645
NOTE: EAV, SAV, and Blanking data values are based on the 8 MSB’s of the output data, the two LSBs are considered fractional.
Cb638 Y638 Cr638 Y639 FFh 00h 00h 9Dh 80h 1 0h 80h 10h 80h 10h
FFh 00h 00h ABh 80h 10h 80h 10h 80h 10h80h 10h 80h 10h
EAV
FFh 00h 00h F1h 80h 10h 80h 10h 80h 10h80h 10h 80h 10h
EAV
CS7666
12.2727MHz
CLKOUT
HREF
DO [9-0]
A
DO [9-0]
B
Figure 5. 2x Pixel Clock, 10-Bit interleaved Output Format for 640x480 Image Format.
10h Y0 Y1 Y2 Y3 Y4 Y633 Y634 Y635 Y636 Y637 Y638 Y639 10h
80h Cb0 Cr0 Cb2 Cr2 Cb4 Cb632 Cr634 Cb634 Cr636 Cb636 Cr638Cb638 80h
NOTE: EAV, SAV, and Blanking data values are based on the 8 MSB’s of the output data, the two LSBs are considered fractional.
Figure 6. 1x Pixel Clock, 20-Bit Parallel Output Format for 640x480 Image Format.
DS302PP1 13
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