Cirrus Logic CS7654-KQ Datasheet
CS7654
CCD Color-Space Processor with Analog Output
Features
l ITU-601 Compliant Image Formatting
l ITU-656 and SMPT E-125/M Transport s
2
l I
C Control Interface
l Limited Secondary I
l Automatic White Balance
l Programmable Gamma Correction
l Programmable Interpolation
l Programmable Luma Gain and Saturation
Control
l Fully Programmable Color Separation Matrix
Coefficients
l Supports up to 1440, active pixels per line,
with no limitation on Vertical Size
l Programmable "Chroma Kill" circ uit
l Highly integrated for low part count camer as
l Three DACs providing simultaneous composite,
S-video outputs
l Multi-standard su pport for N TSC-M, NTS C-
JAPAN, PAL (B, D, G, H, I, M, N, Combinatio n N)
l On-chip voltage r eference generator m odes, tri-
state DACs and p ower down mode.
2
C Bus Master
Description
The CS7654 is a low-power Digital Color-Space Processor for CCD cameras. It provides all the necessary digital
image processing for sta nda rd four- color in terline tr ansfer CCD imagers. The CS 765 4 p roce sses t he mag enta ,
yellow, cyan, and green (MYCG) CCD imager data int o
YCrCb formatted c omponent digital video a nd into a nalog PAL or NTSC. Internal processing includes color
separation, autom atic white balance, user p rogrammable gamma correction, programmable scaling
(interpolation), digital output formatting and encoding
function for analo g outp ut. Al so, a speci al " Chroma Kill"
circuit eliminates false colors during saturation. Video
output can be formatted to be compatible with NTSC-M,
NTSC-J, PAL-B,D,G,H,I,M,N, and Combination N systems. Closed Caption is suppo rted in NTSC. Three 10bit DACs provide two channels for an S-Video output
port and one composite video outputs.A High-speed I
compatible control interface is provided for in system design.
A general purpose I/O port is als o av aila ble to he lp c onserve valuable b oard space and to pro vide up to eight
“boot” configurations.The CS7654 is designed to work
directly with the CS7615 CCD Imager Analog Processor.
ORDERING INFORMATION
CS7654-KQ 0° to 70° C 64-pin TQFP
(10 mm x 10 mm x 1.4 mm)
I
2
C
CCD
MOSAIC
DATA
SECONDARY
2
C BUS
I
DEFORMATTER
I2C INTERFACE
PRIMARY
I2C BUS
COLOR
SEPARATION
AND
ANITALIASING
GAMMA
CORRECTION
REGISTER
BLOCK
Preliminary Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
WHITE
BALANCE
SCALER
PLL AND
CLOCK
DRIVER
XTAL
AWB
CONTROL
OUTPUT
FORMATTER
EXTERNAL
TIMING
INTERPOLATION
AND FILTER
CHROMA
VIDEO
FORMATTER
LUMA
INTERPOLATION
AND DELAY
10-BIT
DAC
10-BIT
Σ
DAC
10-BIT
DAC
CHROMA
COMPOSITE
LUMA
VREF/
VSYNC
HREF/
HSYNC
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1998
(All Rights Reserved)
DS330PP2
MAY ‘99
1
TABLE OF CONTENTS
CHARACTERISTICS/SPECIFICATIONS.............................. ...... ....... ...... ....... .... 4
DIGITAL CHARACTERISTICS....................................................................4
SWITCHING CHARACTERISTICS ........................................................ ..... 4
POWER CONSUMPTION ..... ....... ...... ....... ...... ...... ....... ............................... 5
POWER CONSUMPTION ..... ....... ...... ....... ...... ...... ....... ............................... 6
CONTROL PORT CHARACTERISTICS ..................................................... 6
RECOMMENDED OPERATING CHARACTERISTICS...............................7
ABSOLUTE MAXIMUM RATINGS.............................................................. 7
GENERAL DESCRIPTION .................................................................................. 8
Overview ......................... ................................ ................................ ............ 8
Digital Output Formats ..............................................................................11
Internal Horizontal Scaler ......................................................................... 11
CLKIN2X Input Timing ..............................................................................12
CLKOUT_GRG ..................... .......................................................... .......... 12
INTERN.AL PROCESSING ............................................................................... 13
Input Data Format and Chroma Separator ............................................... 13
White Balance and Gamma Correction ....................................................13
Chroma Kill ...............................................................................................13
Internal Filters ...........................................................................................14
Analog Video Timing Generator ...............................................................14
Color Subcarrier Synthesizer ....................................................................14
Chroma Path ............................................................................................. 14
Luma Path ................................................................................................14
Digital to Analog Converters .....................................................................15
Voltage Reference ....................................................................................15
Current Reference ................ ....... ...... ....... ...... ...... ....... ...... ....... ...... ..........15
Closed Caption Insertion .......................................................................... 15
Control Registers ......................................................................................16
Testability .................................................................................................. 16
OPERATIONAL DESCRIPTION ........................................................................ 16
Reset Hierarchy . ...... ....... ...... ....... ...... ....... ...... .......................................... 16
Vertical Timing ............................................................ ....... ...... ....... ... 16
NTSC Interlaced .................................................................................17
PAL Interlaced ....................................................................................18
Progressive Scan ............................................................................... 18
Digital Video Input Modes ......................................................................... 18
Multi-standard Output Format Modes .......................................................20
Subcarrier Generation ..............................................................................20
Color Bar Generator .................................................................................20
Super White/Super Black support ............................................................. 21
FILTER RESPONSES ................................................................................ 23
CS7654
Preliminary produc t informat ion des cribes p roducts w hich are in product ion, but for which f ull char acteriz ation dat a is not yet avai lable. Adv anced
product inf ormat ion des crib es pro ducts wh ich ar e in deve lopmen t and s ubjec t to deve lopmen t cha nges. Ci rrus Lo gic, I nc. has made be st ef forts
to ensure t ha t the informat ion contained i n this document is accurate and reliabl e. H ow ev er, the infor m at i on is subject t o c hange without no t i c e
and is provid ed “AS IS” without warranty of any k i nd (express or im plied). No responsibility is assume d by Cirrus Logic , Inc. for the use of this
information, no r for in fringe ments of pate nts or other rights of third partie s. This d ocume nt is t he prop erty of Cirrus Logic , Inc. and implies no
license unde r pat ents , co pyr ight s, t rade mar ks, or tra de secr ets. N o part of t his pu bl icat io n may be copi ed, repr oduc ed, sto red i n a retrieval system, or trans m it ted, in any form or by any mean s (electronic, mec hanical, photographic, or otherwise). Furthermore, no part of this publication
may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of
Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners
which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
INTERNAL REGISTER STRUCTURE AND USER INTERFACE ..................... 25
Operating CS7654 in Normal I2C Configuration (Three-Byte Mode) ....... 25
Station Address .................................................................................. 25
Write Operations in Three-Byte Mode ............................................... 25
Address Set Operation ....................................................................... 26
Read Operations in Three-Byte Mode ............................................ ... 2 6
Operating CS7654 in Four-Byte I2C Configuration ............................ 26
Write Operations in Four-Byte mode ................................................. 26
Read Operations in Four-Byte Mode ....................................... ....... ... 27
Initializing Slave Devices on Secondary I2C bus from an EPROM .......... 27
Controlling the Configuration Process ...................................................... 28
Reserved Registers and Test Pins ........................................................... 29
General Purpose I/O Port ......................................................................... 29
ANALOG ........................... ....... ...... ....... ...... ....... ...... ...... .................................... 30
Analog Timing .......................................................................................... 30
VREF .............................. ................................................... ....................... 30
ISET-DAC ....................... ............. ................... ................... .................... ... 30
DACs ........................................................................................................ 30
Luminance DAC ................................................................................. 30
Chrominance DAC ............................................................................. 31
COMP_VID DAC ................................................................................ 31
REGISTER DESCRIPTION ............................................................................... 32
BOARD DESIGN AND LAYOUT CONSIDERATIONS ..................................... 53
Power and Ground Planes ....................................................................... 53
Power Supply Decoupling ........................................................................ 53
Digital Interconnect ................................................................................... 53
Analog Interconnect ................................................................................. 53
Analog Output Protection ......................................................................... 54
ESD and Latch up Protection ................................................................... 54
External DAC Output Filter ....................................................................... 54
PIN DESCRIPTIONS ......................................................................................... 55
PACKAGE DIMENSIONS ................................................................................. 60
CS7654
3
CHARACTERISTICS/SPECIFICATIONS
CS7654
DIGITAL CHARACTERISTICS (T
1 = V
DD
.)
= 25 °C; VDD = 5 V; CL = 30 pF; Input Levels: logic 0 = 0 V, logic
A
Parameter Symbol Min Typ Max Unit
Logic Inputs
High-Level Input Voltage V
Low-Level Input Volt age V
Input Leakage Current I
Input Pin Capacitance C
IH
IL
IN
DI
VDD - 0.8 - - V
--0.8V
- - 10.0 µA
-10-pF
Input Clamp Voltage - -0.7 - V
Logic Outputs
High-Level Output Source Current @ IOH = 1mA V
Low-Level Output Sink Current @ I
= 1mA V
OL
High-Z Leakage Current I
SWITCHING CHARACTERISTICS (T
logic 1 = V
DD
.)
= 25 °C; VDD = 5 V; CL = 30 pF; Input Levels: logic 0 = 0 V,
A
OH
OL
Z
VDD - 0.4 - - V
0.4 - - V
- - 10.0 µA
Parameter Symbol Min Typ Max Unit
Digital Input
CLKIN2X Frequency Range f
Input Data setup time, DI[9:0] t
Input Data hold time, DI[9:0] t
CLK2X
S1
H1
-2730MHz
5--ns
5--ns
Digital Output
Channel A/B Digital Data Output Clock Interleaved Data
Channel A/B Output Hold Time t
Channel A/B Output Propagation Delay t
Digital Output Rise Time with 30 pF load t
Digital Output Fall Time with 30 pF load t
f
CLKOUT_GRG
OH
PD
R
F
--30MHz
-0-ns
-1.95ns
-15-ns
-15-ns
.
Specifications are subject to change without notice
4
CLKIN2X
CLKIN
Mosaic
Input Data
DI[9:0]
CLKOUT
Output Data
DOA[9:0]
DOB[9:0]
t
H2
t
S2
tH1t
S1
Input Timing Diagram
t
PD
t
OH
Output Timing Diagram
CS7654
POWER CONSUMPTION (
TA = 25 °C; VDD = 5 V; CL = no load; Input Levels: logic 0 = 0 V, logic 1 = VDD.)
Parameter Symbol Min Typ Max Unit
Power Supply
Supply Voltage VAA 4.75 5.0 5.25 V
Digital Supply Current (Encoder) IAA1 - 70 mA
Analog Supply (Encoder) Low-Z (Note 1) IAA2 - 100 - mA
Power Supply Rejection Ratio PSRR - 0.02 0.05 %/%
Normal Mode I
Low Power Mode I
DD
DD
-150200mA
-716mA
Analog Outputs
Full Scale Output Current COMP_VID/Y/C (Notes 2, 3) IO 32.9 34.7 36.5 mA
Full Scale Output Current COMP_VID/Y/C (Notes 2, 4) IO 8.22 8.68 9.13 mA
LSB Current COMP_VID/Y/C (Notes 2, 3) IB 32.2 33.9 35.7 mA
LSB Current COMP_VID/Y/C (Notes 2, 4) IB 8.04 8.48 8.92 mA
DAC-to DAC Matching MAT - 2 - %
Output Compliance VOC 0 - + 1.4 V
Output Impedance ROUT - 15 - k
Output Capacitance COUT - - 30 pF
DAC Output Delay ODEL - 4 12 nsec
DAC Rise/Fall Time (Note 5) TRF - 2.5 5 nsec
Ω
Notes: 1. Low-Z - 3 dacs on
2. Output current levels with ISET = 4 KΩ , VREF = 1.232 V.
3. DACs are set to low impedance mode
4. DACs are set to high impedance mode
5. Times for black-to-white-level and white-to-black-level transitions.
5
CS7654
POWER CONSUMPTION (Continued)
Parameter Symbol Min Typ Max Units
Voltage Reference
Reference Voltage Output VOV 1.170 1.232 1.294 V
Rreference Input Current UVC - - 10 uA
Static Performance
DAC Resolution - - 10 Bits
Differential Non-Linearity DNL -1 +
Integral Non-Linearity INL - 2 +
Dynamic Performance
Differential Gain DG - 2 5 %
Differential Phase DP - +
Hue Accuracy HA - - 2 deg
Signal to Noise Ratio SNR 70 - - dB
Saturation Accuracy SAT - 1 2 %
0.5 + 1 LSB
1+ 2LSB
0. 5 + 2deg
CONTROL PORT CHARACTERISTICS (T
1 = V
DD
.)
= 25 °C; VDD = 5 V; Input Levels: logic 0 = 0 V, logic
A
Parameter Symbol Min Max Unit
SCL Clock Frequency f
Bus Free Time Between Transmissions t
Start Condition Hold Time t
Clock Pulse Width High
Low
Setup Time for Repeat Start Condition t
SDAIN Hold Time from SCL Falling t
SDAIN Setup Time from SCL Rising t
SDAIN and SCL Rise Time t
SDAIN and SCL Fall Time t
Setup Time for Stop Condition t
Stop Start
SDA
t
buf
CL
S
t
hdst
t
high
SCL
buf
hdst
t
high
t
low
sust
hdd
sud
r
f
susp
Repeated
Start
-400kHz
1.3 - µs
0.6 - µs
0.6
1.3
-
-
µs
µs
0.6 - µs
0-µs
0.1 - µs
-1.0µs
-0.3µs
0.6 - µs
Stop
t
hdst
t
f
t
susp
t
low
t
hdd
t
sud
t
sust
t
r
I2C Timing Diagram
6
CS7654
RECOMMENDED OPERATING CHARACTERISTICS
Parameter Symbol Min Typ Max Unit
Power Supply Voltage V
DD
Ground to Ground Voltage Differential - - 10 mV
Digital Input Rise/Fall Time - - 10 ns
CLKIN Level Setup to CLKIN2X Rising (non-interpolated) t
CLKIN Level Hold after CLKIN2X Rising (non-interpolated) t
S2
H2
Digital Input Voltage Range 0 - V
Operating Temperature Range T
A
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Unit
Power Supply Voltage V
Digital Input Voltage Range GND - 0.3 V
Forced Digital Output Current - 50 mA
Sustained Digital Output Voltage GND - 0.3 V
Output Short Circuit Current - - mA
Operating Temperature Range T
Lead Solder Temperature (10 s duration) - +260 °C
Storage Temperature Range -65 +160 °C
DD
A
4.5 5.0 5.5 V
8--ns
8--ns
DD
0-70°C
-0.3 6.0 V
+ 0.3 V
DD
+ 0.3 V
DD
070°C
V
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7
CS7654
GENERAL DESCRIPTION
Overview
The CS7654 is a complete color space converter
and multi-standard digital video encoder implemented in current CMOS technology. It provides
all necessary digital image processing for standard
four-color interline transfer CCD imagers. The
CS7654 processes the magenta, yellow, cyan, and
green (MYCG) CCD imager data into YCrCb formatted component and into NTSC-M, NTSC-J,
PAL-B, PAL-D, PAL-G, PAL-H, PAL-I, PAL-M,
PAL-N, or PAL-N Argentina-compatible analog
video.
Two 10-bit DAC outputs provide high quality SVideo analog output while another 10-bit DAC simultaneously generates composite analog video.
In order to lower overall system costs, the CS7654
provides an internal voltage reference that eliminates the requirement for an external, discrete,
three-pin voltage reference.
The CS7654 forms the heart of a four chip digital
CCD Camera. The four chips include the CCD imager, the CS7615 CCD digitizer, the CS7654 color
space processor, and a vertical drive interface-chip
for the CCD imager. Most four-phase CCD imagers (and their associated vertical drives) can be
used with the CS7615 digitizer and the CS7654
processor to form a simple and cost-effective Analog output format digital camera. The CS7615 and
CS7654 together support imager formats ranging
from 175×175 pixels up to 1000x1000 pixels. Timing control is located in the CS7615 analog processor, while the CS7654 synchronizes itself by
decoding the timing cues embedded in the CS7615
data stream. Alternately, the CS7654 accepts horizontal and vertical timing signals on HREFIN and
VREFIN pins. The block diagram in Figure 1 illustrates a typical system interconnect.
The CS7654 provides color separation of standard
MYCG chroma block data from industry standard
CS7615
CCD
6
512x480
Vertical
Drive
+18V to +12V
Figure 1. Typical 4-Chip Digital CCD Camera
CDS/ADC
Timing
6
I2C I2C
CCD
Bias
CS7654
Image
Processor
2
+5V
four-color CCD imagers. Gamma correction and
white balance adjustment functions are also included in the CS7654. The YCrCb (luminance and
chrominance) data is output at twice the scaled
pixel rate in 10-bit format. The digital YCrCb output data from the CS7654 conforms to the ITU-656
parallel component digital video recommendation
with embedded synchronization (see Embedded
EAV and SAV discussion).
The CS7654 incorporates an internal horizontal
scaler which may be turned on to increase the horizontal pixel count of the popular 360 (CIF) and
512 horizontal pixel per line imagers. The most
common target resolutions for the scaler are 640
and 720 pixels per line (square and rectangular pixel formats), but it is possible to provide generic
scaling of M/N where M and N are values from 1 to
31.
The CS7615 and CS7654 chip set supports a wide
range of imager formats while providing an output
format that follows the ITU-601 Component Digital Video recommendation. The ITU-601 document primarily specifies horizontal resolutions of
720 active horizontal pixels (which is required for
broadcast television compatibility). However,
many of today’s digital video receivers are capable
of operating with a wide range of video image formats. Even though these digital video receivers allow image formats not specified in the ITU601/656 recommendation, all of these receivers expect the basic ITU-601/656 protocol to be followed
in terms of data sequence and timing cues. This is
the case with the CS7654, where all output formats
8
CS7654
follow the ITU-601/656 recommendation even if
the image formats differ in horizontal a nd vertical
pixel dimensions.
EAV
H=1
Lines 1 to 19 V=1
Lines 20 to 26 3
V=0
Lines 264 to 282 V=1
Blanking
Horizontal
SAV
H=0
.
Vertical Blanking
Active Video
Field 1
Vertical Blanking
F=0
Lines
4 to 265
Lines 283 to 525
V=0
Active Video
Field 2
Blanking
Horizontal
640
0
779
Figure 2. Horizontal and Vertical Timing States
(640×480 resolution)
F=1
Lines
266 to 3
639
9
CS7654
Word Data Content Pixel Notes
1280 1111 1111 640 EAV
1281 0000 0000 EAV
1282 0000 0000 EAV
1283 1FV1 P3P2P1P0 641 EAV
1284 1000 0000 642 For pixels 642 to 777
1285 0001 0000
1286 1000 0000
1287 0001 0000 643
1552 1000 0000 776
1553 0001 0000
1554 1000 0000
1555 0001 0000 777
1556 1111 1111 778 SAV
1557 0000 0000 SAV
1558 0000 0000 SAV
1559 1FV0 P3P2P1P0 779 SAV
0 Cb0 0 Start of Digital Video
1 Y0 For VBLANK line 1 to 19
2Cr0
3Y1 1
4Cb2 2
5Y2
6Cr2
7Y3 3
2n Cbn n For active pixels 20
2n + 1 Yn
2n + 3 Crn
Yn+1 n+1
1272 Cb636 636
1273 Y636
1274 Cr636
1275 Y637 637
1276 Cb638 638
1277 Y638
1278 Cr638
1279 Y639 End of Digital VIdeo
Table 1. Detail of Scan Line for 640x480 Image
Cr = Cb = 80h
Y = 10h
and 264 to 283
Cr = Cb = 80h
Y = 10h
through 263 and 283 to
525 for n=even from pix-
els 0 to 638
10
CS7654
Digital Output Formats
The CS7654 can output data in a 10-bit format at
a 2x output pixel clock rate. Figure 3 details the
clock and data relationships. The output data transitions on the falling edge of the clock such that the
rising edge of the clock can be used to latch the data
into subsequent circuitry.
The CS7654 delivers 4:2:2 component digital video output data in YCrCb format. The data conforms
to the ITU-R BT.656 specification. The Y component range is 16-235 (8-bit data) and the Cr and Cb
component ranges are 16-240 (8-bit data). However, by setting CLIP_OFF (register 07h bit 6 at
SA34h) to a value of 1, the output data can be extended to a range of 1-254 (8-bit data). Only 00 and
FF are restricted to allow digital timing codes. The
CLIP_OFF register will set the digital section on
the data path to the extended range of value. If you
want to have the analog output set to extended
range, you will also have to set Register 06h at Station Address (SA ) 0x00.
The digital outputs are configured for 10-bit interleaved Y and CrCb data
The CS7654 supports both 8-bit and 10-bit operation as per the ITU-656 recommendation. The ITU656 recommendation defines the primary data path
as 8-bits wide with two additional fractional bits
that can be used to form a 10-bit data path. If only
8-bits of output data are used, the two LSBs,
DOUT1 and DOUT0 are not used. However,
DOUT[9:2] is connected exactly the same as in a
10-bit system. This is essential to properly pass the
image data and synchronization signals to the next
component.
Internal Horizontal Scaler
The internal horizontal scaler is used to bridge between common CCD imager formats and computer
or television formats.
Several pre-defined scaler modes may be selected
by writing a 3-bit value to bits 0-2 of register 04h at
SA 0x34h. These default scaling modes are described in Table 2. If the CUSTOM bit (bit 3 of register 04h at SA 0x34h) is set to a 1, then the scaling
ratio is determined by the M and N values contained in the Scaler Control registers (2Dh - 2Fh at
SA 0x34h.)
24.5454MHz
CLKOUT
SAV
DO [9-0]
A
Line 3 Pixel 776
to Line 4 P i xel 3
DO [9-0]
A
Line 263 Pixel 638
to Line 264 Pixel 645
DO [9-0]
A
Line 525 Pixel 638
to Line 1 Pixel 645
NOTE: EAV, SAV, and Blanking data values are based on the 8 MSB’s of the output data, the two LSBs are considered fractional.
Cb638 Y638 Cr638 Y639 FFh 00h 00h 9Dh 80h 10h 80h 10h 80h 10h
Figure 3. 2x Pixel Clock, 10-Bit interleaved Output Format for 640x480 Image Format.
FFh 00h 00h ABh 80h 10h 80h 10h 80h 10h80h 10h 80h 10h
EAV
FFh 00h 00h F1h 80h 10h 80h 10h 80h 10h80h 10h 80h 10h
EAV
11
CS7654
CLKIN2X Input Timing
The CLKIN2X, pin 59, will always require a primary pixel rate clock source. CCD manufacturers
generally specify a pixel clock frequency that is
compatible with one of the analog encoders that
can be used with a given imager. If the analog out-
Specific pixel-rate clock frequencies for analog encoders include 14.31818 MHz for 768H imagers,
the primary ITU-601 13.5 MHz for 720H imagers,
and down to 12.272727 MHz clock rates for 640H
VGA format imagers.
CLKOUT_GRG
put is used, the clock frequency input must be
matched precisely. However, digital display systems, such as those based on VGA graphics adapter
cards and Zoom Video systems, are generally not
sensitive to pixel clock frequency, and will tolerate
CLKOUT_GRG follows the output data rate The
clock output is at 2x the output luma sample rate,
there is no non-interlaced digital output on the
CS7654.
a wide range of pixel and frame rates.
Mode CCD Format CCD Clock (MHz) Output Format Input Clock (MHz) Scaling Ratio
000 CCD ½ input clock same as CCD (30 MHz max.) 1:1
001 512x480 9.818 640x480 24.5454 4:5
010 512x480 9.346 720x480 27.000 9:13
011 512x576 9.281 720x480 27.000 11:16
100 362x480 6.75 640x480 24.5454 11:20
101 362x480 6.75 720x480 27.000 1:2
362x576 6.75 720x576 27.000
110 512x576 9.563 720x576 27.000 17:24
11 1 512x480 9.000 720x480 27.000 2:3
512x576 9.000 720x576 27.000
Table 2. Default S caling Modes (Reg i ster 04h at SA34h)
12
CS7654
INTERNAL PROCESSING
The internal operation of the CS7654 can be separated into several distinct blocks. The following
section provides an overview of how these blocks
operate and interact.
Input Data Format and Chroma Separator
The CS7654 accepts up to 10-bit MYCG image
data from a CCD digitizer such as the CS7615.
The CS7654 internally converts the four-color
CCD MYCG interlaced image data into the various
color space for mats. Thes e include R GB and YU V,
as well as YCrCb. The individual image adjustments are performed in the most appropriate color
space representation. Ultimately the image is converted to YCrCb format for outputting digital data.
The same digital output data is also encoded in the
digital video encoder post processor section and
converted to analog NTSC or PAL.
White Balance and Gamma Correction
The red and blue color balances can be adjusted
through the I2C control port. During the AWB (automatic white balance) sequence the red level is adjusted to minimize the (Y-R) difference
component; similarly the blue level is adjusted to
minimize the (Y-B) color difference component.
An automatic white balance is initiated by writing
a 1 to register 05h bit 1 at SA 0x34h. For manual
control, the red balance is accessed through register
08h, and the blue balance is accessed through register 09h ( both at SA 0x34h).
Gamma correction is provided to offset the non-linear illumination profile of the display device. Separate 256 entry tables are supplied for red, green,
and blue. Each entry is 8-bits. The gamma table is
programmed through register 0Ch at SA 0x34h.
The write format is similar to the write format described in the normal I2C operation section later in
this document. The first byte contains the CS7654
device address and write bit, the second byte con-
tains the CS7654 gamma table register address
(0Ch), the third byte determines which gamma
RAM to update (red, green, and blue), the next 256
bytes contain the gamma table entries.
The blue gamma RAM is selected by setting register 0Ch bit 0 to a one; the green gamma RAM is selected by setting register 0Ch bit 1 to a one; and the
red gamma RAM is selected by setting register 0Ch
bit 2 to a one. Any, or all of the gamma RAMs may
be selected . The most common implementation is
to write the same gamma table to all 3 RAMs by
setting bits 0-2 high. The gamma table itself is
loaded from low to high. The first byte after the
RAM selection byte will correspond to the value
used when the input data is 00h, the 256th byte after
the RAM selection byte will correspond to the value used when the input data is FFh.
The gamma table is read in a similar manner. However, certain restrictions ar e made to reads. First,
the gamma RAMs may only be read one at a time
(RAM selection byte = 01,02,04 only) and, second,
the gamma table may only be read when gamma
correction is disabled (register 05 bit2 = 0).
Chroma Kill
As the brightness of an image increases, the green,
yellow, cyan, and magenta pixels within the CCD
array will saturate at different intens ity levels. As a
result, a highly illuminated object or light source
may start to look cyan. To overcome this effect, an
internal Chroma kill circuit compares the luma and
chroma values of each pixel to a set of programma-
ble thresholds. If the pixel’s luma value is greater
than the Y_THR value (register 27h at SA 0x34h )
and its Cr and Cb values are between the
CR_THR_H , CR_THR_L , CB_THR_H, and
CB_THR_L threshold values respectively, then
that pixel will lose its chroma value (become
white.) These thresholds are stored in registers 27h
- 2Ch at SA 0x34h.
13
CS7654
Internal Filters
The CS7654 has an internal low-pass chroma filter
to reduce the effects of color aliasing. This filter is
enabled by writing a value of 0 to bit 4 of register
01h at SA 0x00h. The CS7654 also contains a luma
peaking filter to enhance the edges of blurred images. This filter is enabled by setting register 05h bit
3 to a value of 0 at SA 0x34h. By default the lowpass chrome filter is off and the peaking filter is on.
Analog Video Timing Generator
All timing generation is accomplished via a
27 MHz input applied to the CLKIN2X pin.
The Video Timing Generator is responsible for orchestrating most of the other modules in the device.
It automatically disables color burst on appropriate
scan lines and automatically generates serration
and equalization pulses on appropriate scan lines.
Color Subcarrier Synthesizer
The subcarrier synthesizer is a digital frequency
synthesizer that produces the appropriate subcarrier frequency for NTSC or PAL. The CS7654 generates the color burst frequency based on the CLK
input (27 MHz). Color burst accuracy and stability
are limited by the accuracy of the 27 MHz input. If
the frequency varies, then the color burst frequency
will also vary accordingly.
Controls are provided for phase adjustment of the
burst to permit color adjustment and phase compensation. Chroma hue control is provided by the
CS7654 via a 10-bit Hue Control Register
(HUE_LSB and H_MSB). Burst amplitude control
is also made available to the host via the 8-bit burst
amplitude register (SC_AMP). Horizontal sync to
color burst phase adjust is possible by programming the SCH register (register 17h, SA 00h).
Chroma Path
The Video Input Formatter delivers 4:2:2 YUV
outputs into separate chroma and luma data paths.
The chroma path will be discussed here.
The chroma output of the Video Input Formatter is
directed to a chroma low-pass 19-tap FIR filter.
The filter bandwidth is selected (or the filter can be
bypassed) via the CONTROL_1 Register. The
passband of the filter is either 650 KHz or 1.3 MHz
and the passband ripple is less than or equal to
0.05 dB. The stopband for the 1.3 MHz selection
begins at 3 MHz with an attenuation of greater than
35 dB. The stopband for the 650 KHz selection begins around 1.1 MHz with an attenuation of greater
than 20 dB.
The output of the chroma low-pass filter is connected to the chroma interpolation filter in which upsampling from 4:2:2 to 4:4:4 is accomplished.
Following the interpolation filter, the U and V
chroma signals pass through two independent variable gain amplifiers in which the chroma amplitude
can be varied via the U_AMP and V_AMP 8-bit
host addressable registers.
The U and V chroma signals are fed to a quadrature
modulator in which they are combined with the
output from the subcarrier synthesizer to produce
the proper modulated chrominance signal.
The chroma then is interpolated by a factor of two
in order to operate the output DACs at twice the
pixel rate. The interpolated filters enable running
the DACs at twice the pixel rate and this helps reduce the sinx/x roll-off for higher frequencies and
reduces the complexity of the external analog low
pass filters.
Luma Path
Along with the chroma output path, the CS7654
Video Input Formatter initiates a parallel luma data
path by directing the luma data to a digital delay
line. The delay line is built as a digital FIFO in
which the depth of the FIFO replicates the clock
period delay associated with the more complex
chroma path. Brightness adjustment is also provided via the 8-bit BRIGHTNESS_OFFSET Register.
14
CS7654
Following the luma delay, the data is passed
through an interpolation filter that has a programmable bandwidth, followed by a variable gain amplifier in which the luma dc values are modifiable
via the Y_AMP Register.
The output of the luma amplifier connects to the
sync insertion block. Sync insertion is accomplished by multiplexing, into the luma data path,
the different sync dc values at the appropriate
times. The digital sync generator takes horizontal
sync and vertical sync timing signals and generates
the appropriate composite sync timing (including
vertical equalization and serration pulses), blanking information, and burst flag. The sync edge rates
conform to RS-170A or ITU R.BT601 and ITU
R.BT470 specifications.
It is also possible to delay the luminance signal,
with respect to the chrominance signal, by up to
three pixel clocks. This variable delay is useful to
offset different propagation delays of the luma
baseband and modulated chroma signals. This adjustable luma delay is available only on the
COMP_VID output.
Digital to Analog Converters
The CS7654 provides three discrete 27 MHz DACs
for analog video. The default configuration is one
10-bit DAC for S-video chrominance, one 10-bit
DAC for S-Video luminance, one 10-bit DAC for
composite output. All three DACs are designed for
driving either low-impedance loads (double terminated 75 Ω) or high-impedance loads (double terminated 300 Ω).
The DACs can be put into tri-state mode via hostaddressable control register bits. Each of the six
DACs has its own associated DAC enable bit. In
the Disable Mode, the 10-bit DACs source (or sink)
zero current.
For lower power standby scenarios, the CS7654
also provides power shut-off control for the DACs.
Each DAC has an associated DAC shut-off bit.
Voltage Reference
The CS7654 is equipped with an on-board voltage
reference generator (1.232 V) that is used by the
DACs. The internal reference voltage is accurate
enough to guarantee a maximum of 3% overall gain
error on the analog outputs. However, it is possible
to override the internal reference voltage by applying an external voltage source to the VREF pin.
Current Reference
The DAC output current-per-bit is derived in the
current reference block. The current step is specified by the size of resistor placed between the
ISET_DAC current reference pin and electrical
ground.
A 4 kΩ resistor needs to be connected between
ISET_DAC pin and GND. The DAC output currents are optimized to either drive a doubly terminated load of 75 Ω (low impedence mode) or a
double terminated load of 300 Ω (high impedence
mode). The 2 output current modes are software selectable through a register bit. Note that there are
two ISET pins on the device, one for the DACS,
and one for the PLL.
Closed Caption Insertion
The CS7654 is capable of NTSC Closed Caption
insertion on lines 21 and 284 independently.
Closed captioning is enabled for either one or both
lines via the CC_EN [1:0] Register bits and the
data to be inserted is also written into the four
Closed Caption Data registers. The CS7654, when
enabled, automatically generates the seven cycles
of clock run-in (32 times the line rate), start bit insertion (001), and finally insertion of the two data
bytes per line. Data low at the video outputs corresponds to 0 IRE and data high corresponds to 50
IRE.
There are two independent 8-bit registers per line
(CC_21_1 & CC_21_2 for line 21 and CC_284_1
& CC_284_2 for line 284). Interrupts are also provided to simplify the handshake between the driver
15
CS7654
software and the device. Typically the host would
write all 4 bytes to be inserted into the registers and
then enable closed caption insertion and interrupts.
As the closed caption interrupts occur the host software would respond by writing the next two bytes
to be inserted to the correct control registers and
then clear the interrupt and wait for the next field.
Control Registers
The control and configuration of the CS7654 is accomplished primarily through the control register
block. All of the control registers are uniquely addressable via the internal address register. The control register bits are initialized during device
RESET.
See the Programming section of this data sheet for
the individual register bit allocations, bit operational descriptions, and initialization states.
The registers of the CS7654 are located in two separate Station Address ( SA ), the first one at 0x00h
and the second one at 0x34h. Be careful to select
the proper SA when accessing register because
some registers have the same address but are located in a different Station Address. Note that both
sections of this device cannot bear the same I2C address.
Testability
The digital circuits are completely scanned by an
internal scan chain, thus providing close to 100%
fault coverage.
OPERATIONAL DESCRIPTION
Reset Hierarchy
The CS7654 is equipped with an active low asynchronous reset input pin, RESET. RESET is used to
initialize the internal registers and the internal state
machines for subsequent default operation. See the
electrical and timing specification section of this
data sheet for specific CS7654 device RESET and
power-on signal timing requirements and restrictions.
While the RESET pin is held low, the host interface
in the CS7654 is disabled and will not respond to
host-initiated bus cycles. All outputs are valid after
a time period following RESET pin low.
A device RESET initializes the CS7654 internal
registers to their default values as described by Table 13 and 14, Control Registers. In the default
state, the CS7654 video DACs are disabled and the
device is internally configured to provide blue field
video data to the DACs (any input data present on
the V [7:0] pins is ignored at this time). Otherwise,
the CS7654 registers are configured for NTSC-M
ITU R.BT601 output operation. At a minimum, the
DAC Registers 0x04 and 0x05 at Station Address
0x00 must be written (to enable the DACs) and the
IN_MODE bit of the CONTROL_0 SA 0x00, Register (0x00) must be set (to enable ITU R.BT601
data input on V [7:0]) for the CS7654 to become
operational after RESET.
Vertical Timing
The CS7654 encoder section can be configured to
operate in any of four different analog timing
modes: PAL, which is 625 vertical lines, 25 frames
per second interlaced; NTSC, which is 525 vertical
lines, 30 frames per second interlaced; and either
PAL or NTSC in Progressive Scan, in which the
display is non-interlaced. These modes are selected
in the CONTROL_0 Register (0x00) at SA
0x00h.Note that there are several digital mode
(scaler settings ) which will not have an equivalent
analog timing mode.
The CS7654 conforms to standard digital decompression dimensions and does not process digital
input data for the active analog video half lines as
they are typically in the over/underscan region of
televisions. 240 active lines total per field are processed for NTSC, and 288 active lines total per
field are processed for PAL. Frame vertical dimensions are 480 lines for NTSC and 576 lines for
PAL. Table 3 specifies active line numbers for both
NTSC and PAL.
16
Mode Field Active Lines
NTSC 1, 3; 2, 4 22-261; 285-524
PAL 1, 3, 5, 7; 2, 4, 6, 8 23-310; 336-623
NTSC Progressive-Scan NA 22-261
PAL Progressive-Scan NA 23-310
Table 3. Vertical Timing
NTSC Vertical Timing (odd field)
CS7654
Line
HSYNC
VSYNC
FIELD
Line
HSYNC
VSYNC
FIELD
Line
HSYNC
VSYNC
FIELD
3
NTSC Vertical Timing (even field)
264 265
PAL Vertical Timing (odd field)
265 1 2
4
5 6
266 267 268 269 270
7 8 9
3 4 5 6
10
271
7
PAL Vertical Timing (even field)
Line
HSYNC
VSYNC
FIELD
311 312
313 314 315 316 317
Figure 4. Vertical Timing
NTSC Interlaced
The CS7654 supports analog NTSC-M, NTSC-J
and PAL-M modes where there are 525 total lines
per frame and two fixed 262.5-line fields per frame
and 30 total frames occurring per second. NTSC in-
318
terlaced vertical timing is illustrated in Figure 5.
Each field consists of one line for closed caption,
240 active lines of video, plus 21.5 lines of blanking.
17
CS7654
Analog
Field 1
523 524 525 1 2 3 4 5 6 7 8 9
Analog
Field 2
261 262 263
Analog
Field 3
523 524 525
261 262 263
Burst begins with positive half-cycle Burst begins with negative half-cycle
1 23456 789
Analog
Field 4
VSYNC Drops
VSYNC Drops
10 22
285284272271270269268267266265264
10 22
285284272271270269268267266265264
Figure 5. NTSC Video Interlaced Timing
PAL Interlaced
The CS7654 supports analog PAL modes B, D, G,
H, I, N, and Combination N, in which there are 625
total lines per frame, two fixed 312.5 line fields per
frame, and 25 total frames per second. Figure 7 illustrates PAL interlaced vertical timing. Each field
consists of 287 active lines of video plus 25.5 lines.
Progressive Scan
The CS7654 supports an analog progessive scan
mode in which the video output is non-interlaced.
This is accomplished by displaying only the odd
video field for NTSC or PAL. To preserve precise
MPEG-2 frame rates of 30 and 25 per second, the
CS7654 displays the same odd field repetitively but
alternately varies the field times. This mode is in
contrast to other digital video encoders, which
commonly support progressive scan by repetitively
displaying a 262 line field (524/525 lines for
NTSC). The common method is flawed: over time,
the output display rate will overrun a system-clo cklocked MPEG-2 decompressor and display a field
twice every 8.75 seconds. NTSC non-interlaced
timing is illustrated in Figure 7. PAL non-interlaced timing is illustrated in Figure 8.
Digital Video Input Modes
The CS7654 provides two different digital video
input modes that are selectable through the
IN_MODE bit in the CONTROL_0 Register at SA
0x00.
In Mode 0 and upon RESET, the CS7654 defaults
to output a solid color (one of a possible of 256 colors). The background color is selected by writing
the BKG_COLOR Register (0x08) at SA 0x00.
The colorspace of the register is RGB 3:3:2 and is
unaffected by gamma correction. The default color
following RESET is blue.
18
VSY NC Drops
Analog
Field 1
CS7654
620 624 625 1 2 3 4 5 6 7 23 24
620 624 625 1 2 3 4 5 6 7 23 24
620 624 625 1 2 3 4 5 6 7 23 24
621 622 623
Analog
Field 2
308 311 312 313 314 315 316 317 318 319 320 336 337
308 311 312 313 314 315 316 317 318 319 320 336 337
309 310
Analog
Field 3
621 622 623
Analog
Field 4
309 310
Analog
Field 5
621 622 623
Analog
Field 6
308 311 312 313 314 315 316 317 318 319 320 336 337
620 624 625 1 2 3 4 5 6 7 23 24
308 311 312 313 314 315 316 317 318 319 320 336 337
309 310
Analog
Field 7
621 622 623
Analog
Field 8
309 310
Burst Phase = 135 degrees relative to U Burst Phase = 225 degrees relative to U
Figure 6. PAL Interlaced Timing
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