Cirrus Logic CS7622-IQ Datasheet

CCD Imager Analog Processor

CS7622

Features

l 13-Bit A/D Conversion Using DRX™

Technology

l Backlight Compensation
l Supports Full Scale Analog Input Voltage

Ranges from 300 mV to 1 V in 100 mV
Increments

l High Resolution Output Mode
l Low Resolution (Preview) Output Mode for

LCD Driver

l Integrated Correlated Double Sampler
l Digital Black Level Clamp
l Digital Outputs Selectable for 13, 12, or 10 Bits
l Low Power Consumption
l Power Down Mode
l High Speed Serial Interface
l Supports a Large Variety of Cloc k Input

Frequencies

l Low power mode option

Description

The CS7622 is a low-powe r analog front-en d proces sor
for interline or frame transfer CCD imagers. Main appli­cations include digital still image cameras and video
cameras.

The architecture in cludes a correlated doub le sampler,
black level clamp and a 13-bit A/D conversion mod ule
using patented DRX technology.

Chip parameters can be programmed using a high
speed 4-wire asynchronous digi tal in terfac e.

The chip outputs digitized CCD data in either 13-bit, 12­bit or 10-bit format. 10-bit outputs are generated from the
13-bit A/D output by a programmable companding curve.

ORDERING INFORMATION

CS7622-IQ -40 to +85 °C 32-pin TQFP 7x7x1.4m

CCD OUTPUT

CK_FT

CK_DATA

CDS/DRX

GAIN

CLOCK

GENERATOR

Preliminary Product Information

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

A/D

CONVERTER

BLACK

LEVEL

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 1999

(All Rights Reserved)

OUTPUT

COMPANDER

CLOCK

REGISTER

BLOCK

SERIAL

INTERFACE

SERIAL BUS

DATA OUT

CLOCK OUT

DS322PP1

JUL ‘99

1

TABLE OF CONTENTS

1.0 CHARACTERISTICS/SPECIFICATIONS ........................................................... 4

1.1 DIGITAL CHARACTERISTICS.................................................................... 4

1.2 POWER CONSUMPTION........................................................................... 4

1.3 RECOMMENDED OPERATING CHARACTERISTICS............................... 4

1.4 ABSOLUTE MAXIMUM RATINGS ..............................................................4

1.5 ADC (ANALOG-TO-DIGITAL CONVERTER).............................................. 5

1.6 CDS/VGA PARAMETERS...........................................................................5

1.7 SERIAL INTERFACE TIMING SPECIFICATIONS......................................5

2.0 GENERAL DESCRIPTION .................................................................................. 7

3.0 OPERATION ........................................................................................................ 8

3.1 CDS/VGA (correlated double sampling/variable gain amplification) ........... 8

3.2 Black Level Adjustment ............................................................................ 10

3.3 Gain Adjust Block ..................................................................................... 11

3.4 13-to-10 Bit Compander ........................................................................... 12

3.5 Stand By and Preview Mode ................................................................... 14

3.6 Serial Interface .......................................................................................... 14

3.7 Input Timing for Sampling Clocks ............................................................. 15

4.0 REGISTER DESCRIPTIONS ............................................................................. 17

Reset ........................................................................................................ 18

Power down Control 1 .............................................................................. 18

Operation Control 1 ..................................................................................19

Operation Control 2 ..................................................................................20

Black Level Control (8 LSBs) .................................................................... 20

Black Level Control (MSB) ........................................................................21

Black Level Control - General ................................................................... 21

Black Level Control - Loop Gain, Clamp Length .......................................22

Gain Calibration Offset 1 ..........................................................................23

Gain Calibration Offset 2 ..........................................................................23

Gain Calibration Offset 3 ..........................................................................23

Fixed Gain ................................................................... ...... ....... ................25

Compander - Black slope, Slopes (MSBs) ............................................... 27

Compander Slope 1 (LSBs) ...................................................................... 27

Compander Slope 2 (LSBs) ...................................................................... 27

Compander Slope 3 (LSBs) ...................................................................... 28

Compander Slope 4 (LSBs) ...................................................................... 28

Compander Offset 1 ................................................................................. 28

Compander Offset 2 (MSBs) .................................................................... 29

Compander Offset 2 (LSBs) .....................................................................29

Compander Offset 3 (LSBs) .....................................................................29

Compander Offset 4 (LSBs) .....................................................................29

CS7622

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/

Preliminary product info rmation describes products which are i n p roduction, but for which full characterization data is not yet available. Advance product i nfor ­mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of

any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
otherwise) without the pri or wri tt en consen t of Ci rrus Logic, Inc. Items from any Cirrus Logic websi te or disk may be printed for use by the user. However, no
part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical,
photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture
or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade­marks and service marks can be found at http://www.cirrus.com.

2 DS322PP1

Compander X1 (MSBs) ............................................................................ 30

Compander X1 (LSBs) ............................................................................. 30

Compander X2 (MSBs) ............................................................................ 30

Compander X2 (LSBs) ............................................................................. 30

Compander X3 (MSBs) ............................................................................ 31

Compander X3 (LSBs) ............................................................................. 31

Device ID .................................................................................................. 31

Revision Code .......................................................................................... 31

5.0 PIN DESCRIPTIONS ......................................................................................... 32

Supply ...................................................................................................... 32

Ground ..................................................................................................... 32

CMOS Input ............................................................................................. 32

CMOS Analog Input ................................................................................. 33

CMOS 4 mA Output ................................................................................. 33

6.0 PACKAGE DIMENSIONS ................................................................................. 34

LIST OF FIGURES

Figure 1. SEN Timing.........................................................................................................................6

Figure 2. Serial Write Timing..............................................................................................................6

Figure 3. Read Data Timing...............................................................................................................6

Figure 4. Digital Camera Block Diagram............................................................................................7

Figure 5. CS7622 Block Diagram.......................................................................................................7

Figure 6. Idealized CCD output waveform.........................................................................................8

Figure 7. Transfer function of VGA circuit (assuming full scale level of 1.0 V) ..................................9

Figure 8. Block diagram of CDS/VGA circuit......................................................................................9

Figure 9. Idealized timing diagram of VGA/CDS circuit ...................................................................10

Figure 10.Black level adjustment loop ..............................................................................................11

Figure 11.Transfer function of Vin to Gain Adjust output Block (assuming full scale level of 1.0 V).12

Figure 12.Gain Adjust output Block...................................................................................................12

Figure 13.13-to-10 bit compander.....................................................................................................13

Figure 14.CS7622 output data and clocks........................................................................................14

Figure 15.Input Timing ......................................................................................................................14

Figure 16.Typical Connection Diagram.............................................................................................16

Figure 17.Transfer Function of Analog Input to Digital Output (assuming full scale level of 1.0 V) ..24
Figure 18.Transfer Function of ADC with Fixed Gain Settings (assuming full scale level of 1.0 V)..26

CS7622

DS322PP1 3

1.0 CHARACTERISTICS/SPECIFICATIONS

CS7622

DIGITAL CHARACTERISTICS (T

= 25 °C; V

A

DDD

Parameter Symbol Min Typ Max Units

Logic Inputs

High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I

Logic Outputs

High-Level Output Source Current @ IOH = 4 mA V
Low-Level Output Sink Current @ I

= 4 mA V

OL

3-State Leakage Current I

POWER CONSUMPTION (T

= 25 °C; V

A

DDA

= V

DDD

Parameter Symbol Min Typ Max Units

Power Dissipation Peak Mode

Preview Mode

Stand By Down

Analog Power Supply Current Peak Mode

Preview Mode

Stand By Down

Digital Power Supply Current Peak/Preview Mode

Preview Mode

= 3.3 V)

IH

IL

IN

OH
OL

OZ

VDD-0.8 - - V

--0.8V

--10mA

VDD-0.4 - mV

--0.4mV

--10

µ

= 3.3 V; Output Load = 30 pF; Input Clock = 15MHz)

P
P

I
I

I

I

P

D
DLR
DPD

I

AN

ALR
APD

DN

DPD

-

-

-

-

-

-

-

-

214
162

0.0825
53

37

0.025
12

0

-

-

-

-

-

-

-

-

mW
mW
mW

mA
mA
mA

mA
mA

A

RECOMMENDED OPERATING CHARACTERISTICS

Parameter Symbol Min Typ Max Units

Power Supply Voltage V

V

DDA
DDD

3.0

2.5

3.3 3.6

3.6

V

V
GNDA to GNDD Voltage Differential 10 mV
Analog Full Scale Input Voltage Range A

IN

300 mV - 1 V V

p-p

Input Clock Rate - 20 MHz - MHz

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

Power Supply Voltage V
Digital Input Voltage GNDD-0.3 V
Analog Input Voltage A
Input Current (except supply pins) 10 mA
Ambient Temperature Range -0 +70 °C
Lead Solder Temperature (10sec durat ion) +260 °C
Storage Temperature Range -65 +150 °C

WARNING: Operation at or beyond these limits may result in permanent damage to the device.

Normal operation is not guaranteed at these extremes.

DDA

, V

IN

DDD

-0.3 6.0 V
+0.3 V

DDD

GNDA-0.3 V

+0.3 V

DDA

4 DS322PP1

CS7622

ADC (ANALOG-TO-DIGITAL CONVERTER)

Parameter Symbol Min Typ Max Unit

Full Scale Input Voltage Range 300 mV 1 V V
Full Scale Input Voltage Range Resolution 100 mV
ADC resolution - 10 - bits
Total Differential Non-Linearity - ±1 - LSB

Total Integral Non-Linearity - ±1 - LSB

CDS/VGA PARAMETERS

Parameter Symbol Min Typ Max Unit

Input Voltage Range 300 mV 1 V V
Total Gain Range A
Input Referred Noise (rms) Maximum Gain Setting Vn

VGA

VGA

SERIAL INTERFACE TIMING SPECIFICATIONS

Description Symbol Minimum Maximum Unit

Enable Setup t1 10 - ns
SDAT Setup t2 10 - ns
SDAT Hold t3 10 - ns
Serial Clock Period (Note 1) t4 143 - ns
Write Data Invalid t5 0 10 ns
Read Data Valid t6 0 10 ns
Clock to Disable t7 143 - ns

Rise to SEN Fall t8 200 - ns

SEN

- 18 - dB

--0.2 mV

0-p

0-p

Notes: 1. the minimum serial clock period must be longer than two pixel clock periods.

DS322PP1 5

SEN

SCLK

CS7622

t1

t7 t8

SDATI

SEN

SCLK

SDATI

R/W

, ADDR <6.0> DATA <7.0>

Figure 1. SEN Timing

R/W A6 A5 A6 A3

t2 t3

Figure 2. Serial Write Timing

t4

SCLK

t5 t6

SDATI

SDATO

A0 XX (DON’T CARE)

D7 D6 D5

Figure 3. Read Data Timing

6 DS322PP1

CS7622

2.0 GENERAL DESCRIPTION

The CS7622 forms the heart of a four chip digital
CCD Camera. The four chips include the CCD im­ager, the CS7622 CCD digitizer, a vertical drive in­terface chip and a backend DSP chip to further
process the digital data (see Figure 4.)

The patented DRX technology allows the CS7622
to output data with 13-bit dynamic range, and at the
same time reducing the power consumption to a 10­bit equivalent A/D converter.

CS7622

CDS/ADC

CCD

Control

The digitized output is either available in 13-bits,
12-bits or 10-bits. The 10-bit output is created by
companding the 13-bit A/D output to 10-bits. The
companding curve consists of 4 linear segments,
where each slope and each start point is user pro­grammable.

A block diagram of the CS7622 chip is shown in
Figure 5.

Backend

DSP

Video Output

AIN

CK_FT

CK_DATA

Σ

Generator

Vertical Drive

+5 V to -5 V

Timing Signals

DC-DC converter

+5 V

Figure 4. Digital Camera Block Diagram

CDS/VGA A/D

Clock

Black

Level

Serial Interface

SEN

SDATI SDATO SCLK

Gain

Adjust

13 to 10-bit

Compander

Reference

M

U
X

LCD Panel

VDD[2]
GND[2]

DOUT[12:0]
(up to 3 may be unused)

CLKO
CLAMP

TEST
RST

REF_CAPP

REF_CAPN

10 k

1 µF

BG_RES

Ω

Figure 5. CS7622 Block Diagram

DS322PP1 7

RESET LEVEL

FEED THROUGH

LEVEL

PIXEL PERIOD

VIDEO

SIGNAL

CS7622

RANGE

DARK

VIDEO LEVEL

Figure 6. Idealized CCD output waveform

3.0 OPERATION

3.1 CDS/VGA (correlated double sampling/variable gain amplification)

An idealized waveform of the CCD output is
shown in Figure 6.

The CCD output contains reset noise, thermal
noise, and 1/f noise generated in the CCD output
circuit. This degrades the S/N ratio and must be
cancelled. Since the noise during the active video
portion of the CCD signal is assumed to be corre­lated with the noise during the feed through portion
of the signal, this noise can be cancelled by sub­tracting the feed through level from the video level.
This operation is called correlated double sam­pling. The active video signal is the difference be­tween the feed through and video levels. The active
video signal varies according to light conditions. In
order to insure that the full dynamic range of the
ADC is utilized even under low light conditions,
the CCD output is amplified using a VGA. The
gain control is provided by a 2 bit control word
generated by an ADC after stage 1, which has a
gain of 1. Based on the input voltage, a gain of 1x,
2x, 4x, or 8x is subsequently applied to the signal.
The amount of gain is later adjusted in the digital
section. After the VGA, the signal gets digitized by
a 10 bit ADC. The 2 bit ADC output is used in

MAX. BRIGHTNESS

combination with the 10 bit ADC output to produce
a 13 bit output.

Adding more gain before the ADC does not offer
performance improvement because the noise of the
CCD (after gain is applied to it) begins to dominate
over the quantization noise. Any additional gain
should be done in digital since the performance is
the same as when the ADC output has the addition­al gain applied.

In order to add more flexibility, the full scale input
range is programmable through register 05h. This
setting will determine what input level maps to the
highest ADC output code. Thus depending on the
saturation level of the particular CCD used in the
system, an appropriate full scale input level can be
chosen in the CS7622. The choices of full scale in­put level are 300 mV to 1 V in 100 mV increments.
In the remainder of this document, all the figures
and discussions assume a full scale level of 1 V is
used.

The transfer function of the VGA portion of the cir­cuit is shown in Figure 7 with full scale level = 1 V.
It is assumed that the CDS has already been per­formed. If desired, the gain switching functionality
can be disabled and forced to a fixed gain of 8x, 4x,
2x, or 1x. This way any dynamic range enhance­ment is lost and the digital output is only 10 bits. If

8 DS322PP1

VOUT (V)

1.07

0.5

CS7622

1X2X4X8X

0.250.125

00 01 10 11

Figure 7. Transfer function of VGA circuit (assuming full scale level of 1.0 V)

Φ1

C1

VIN

100 KΩ

100 KΩ

VREF

C1

Cb

-A1

STAGE 1

Figure 8. Block diagram of CDS/VGA circuit

C2

Vo1

STAGE 2 STAGE 3

2

ADC

a fixed gain of 1x is selected, DOUT[12:3] is used
as the output, a fixed gain of 2x will use
DOUT[11:2], etc. In order to use this mode, the
fixed gain register (14h) should be set and the cali­bration offset registers (OEh - 10h) should be set to

0.
The CDS/VGA circuit is composed of three stages.

The first stage has a fixed gain of 1, and the second
and third stages have variable gain with a combined
gain range of 1 to 8 (0-18 dB). Figure 8 shows a
block diagram of the CDS/VGA circuit. The total
gain is A = (C2/C3)(C4/C5) which is adjusted by
varying C3 and C5. The capacitor Cb on the front

Φ2

-A2

C3

1.00.5

Φ1

C5

C4

Vo2

CONTROLS C3, C5
CONTROLS GAIN ADJUST BLOCK IN DIGITAL

-A3

VOUT

VIN (V)

ADC OUTPUT

of stage 1 is for black level adjustment and will be
discussed in detail later.

This circuit utilizes a two phase non-overlapping
clock to perform the desired CDS function. The
two phase clock also allows the video signal to be
passed to the output while retaining a positive po­larity signal. Figure 9 shows a timing diagram of
the two phase clock along with the CCD signal and
output signals of stages one, two and three.

There is an internal mid-scale DC bias level circuit
at the input pin. This allows AC coupling into the
CS7622 with a capacitor and having the input auto-

DS322PP1 9

CS7622

matically biased to mid-supply without worrying
about external circuitry to perform this task.

3.2 Black Level Adjustment

In order to maintain a constant reference level for
black pixels, a feedback loop is implemented that
sets the black level value at the output of the ADC
to 64 in the 13 bit digital code. This loop is active
during the optically black pixels which are output
at the beginning and end of a frame as well as dur­ing a portion of the horizontal blanking period. The
presence of black pixels in the CCD output is indi­cated by the CLAMP pulse, which is supplied ex­ternally through the CLAMP pin. The black level
can also be written to through the serial port.

In order to acquire a starting value for the black lev­el, the loop will run over the several lines of black
pixels at the beginning of the frame. The block di­agram of the loop is shown in Figure 10. The up­date rate is once per line during active pixel lines as
long as the Clamp pulse is < n+10 cycles. Where n
is the number of pixels accumulated before the
black loop is updated and is programmable through
register 0Dh bits 5:0. If the Clamp pulse is longer

than n+10 cycles the black loop is updated every
n+10 cycles. For example, during optical back lines
the loop is updated several times at a rate of once
every n+10 cycles.

The open-loop transfer function of the black level
adjustment loop is

Hz()

Kn×

=

------------ ­z1–

1

-------- -

K

blk_gain=

256

blk_gain = 1, 2, 4, or 8
where blk_gain is programmable through a register

and n = # of black pixels during clamp time, which
is also programmable. The value of Kxn will deter­mine the open-loop gain of the system. The settling
time for the loop can be calculated using the fol­lowing formula:

For offset range=1 (reg 06h, bit 0)



τ

–

=

------------------ ---------





---- -



fu

1nK–()ln

1

1

For offset range =0




τ

–

=

------------------- -------- -






1

ln





1

1



---- -



fu

nK

-------–
2

CCD
INPUT

SIGNAL

ck_ft

ck_data

OUT OF
STAGE 1

OUT OF
STAGE 2

OUT OF
STAGE 3

V(1)

V(1) V(2) V(3)

V(2) V(3)

V(1) V(2) V(3)

V(1) V(2)

Figure 9. Idealized timing diagram of VGA/CDS circuit

10 DS322PP1

CS7622

During fixed gain mode the time constant is a little
different.



For a fixed gain of 1:

For a fixed gain of 2:

For a fixed gain of 4:

For a fixed gain of 8:



τ

–

=

------------------- -------- -






1

ln








–

τ

=

------------------- -------- -






1

ln








τ

–

=

------------------- -------- -






1

ln







=

τ

–

-------------------- -------



1nK–()ln

1

1



---- -



fu

nK

-------–
8

1

1



---- -



fu

nK

-------–
4

1

1



---- -



fu

nK

-------–
2

1

1



---- -



fu

In order to achieve no ringing in the settling use,

n

--- -

for offset range = 1, and for offset range

1≤

K

------­2K

n

1≤

= 0.
The 9 MSBs of the black level accumulator can be

read or written through a register. If written, the

LSBs are set to zero. The black level is set to “8 ” in
a 10-bit digital output representation. In a 13-bit
representation, it is set to “64.” The power-up de­fault value in the accumulator is at mid level.

Also note that the black level adjust loop can be
disabled. In addition, the black level can be pro­grammed through the serial port.

3.3 Gain Adjust Block

In order to increase the dynamic range of the ADC,
a variable gain, whose value is determined by the
signal level, is applied to each pixel. This allows
for 13 bits of dynamic range and 10 bits of resolu­tion after accounting for the significance of the
ADC output bits. The gain applied in the analog is
illustrated in the transfer curve in Figure 7. Once
the signal is digitized, the gain adjust block uses the
gain information for a given pixel word and shifts
its bits accordingly. For example, using a full scale
level of 1.0 V, if Vin = 0.3 V, the VGA would
choose a gain of 2X so the ADC input is 0.6 V. The
10-bit output of the ADC (with no black level) is
(0.6/1.0) × 1024 = 614, or “1001100110.” in bina­ry. The gain adjust block will take this value plus
the bits representing the 2x gain and divide the out­put by two (shift right by 1). The output of the gain
adjust block is then “0100110011.000.” Note that
the decimal point is virtual, having no existence in
silicon. It is representing the fact that we keep 3 ex­tra bits of lower significance in the output. In the
same manner, if Vin = 0.75 V, a gain of 1X would
be chosen and the output of the gain adjust block

‘64’

BLK LVL LOOP

FROM SERIAL INTERFACE

GAIN REG

VIN

CDS/VGA

Σ

FU = UPDATE FREQUENCY

= PIXEL FREQUENCY

F

P

ADC

DAC

10

+

-

CLIP

7

K

F

U

BINARY

-1

Z

TO

+

+

MUX

-1

Z

F

P

9

THERM

Figure 10. Black level adjustment loop

DS322PP1 11