Cirrus Logic CS7620-IQ Datasheet
CCD Imager Analog Processor
CS7620
Features
l13-Bit A/D Conversion Using DRX™
Technology
lBacklight Compensation
lSupports three Input Ranges of 0.53V,
1.07V, and 1.60V
lMulti-Sync CCD Timing Generator
lHigh Resolution Output Mode
lLow Resolution (Preview) Output Mode for
LCD Driver
lIntegrated Correlated Double Sampler
lDigital Black Level Clamp
lDigital Outputs Selectable for 13, 12, or 10 Bits
lTwo Integrated General Purpose DACs
lLow Power Consumption
lPower Down Mode
lHigh Speed Serial Inte rface
lSupports a Large Variety of Clock Input
Frequencies
lLow power mode option
Description
The CS7620 is a low-power analog front-end processor
for interline or frame transfer CCD imager s. Main appl ications include digital still image cameras with up to
8k×8k pixels.
The architecture inc ludes a correlated double sampler,
black level clamp and a 13-bi t A/D conversion module
using patented DRX technology. In addition, the chip
contains a timing generator, which supports common
CCDs from IBM, and Polaroid. For CCDs using different
timing signals, the internal timing generator can be
bypassed.
There are 2 general purpose DACs availabl e which can
be used to drive motors for iris and shutter control.
Chip parameters can be programmed using a high
speed 4-wire asynchronous digital interface.
The chip outputs digitized CCD data in either 13-bit, 12bit or 10-bit format. 10-bit outputs are generated from the
13-bit A/D output by a programmable companding curve.
ORDERING INFORMATION
CS7620-IQ -40 to +85 °C 64-pin TQFP
10x10x1.4mm
CCD OUTPUT
DAC
OUTPUTS
MASTER
CLOCK
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
CDS/DRX
GAIN
2 DACS
PLL
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
A/D
CONVERTER
BLACK
LEVEL
TIMING
GENERATOR
CCD TIMING SIGNALS
Copyright Cirrus Logic, Inc. 1999
(All Rights Reserved)
OUTPUT
COMPANDER
CLOCK
REGISTER
BLOCK
SERIAL
INTERFACE
SERIAL BUS
DATA OUT
CLOCK OUT
JUL ‘99
DS301PP2
1
TABLE OF CONTENTS
1 CHARACTERISTICS/SPECIFICATIONS .................................................................................. 5
DIGITAL CHARACTERISTICS.................................................................................................5
POWER CONSUMPTION .. ...... ............................................. .............................................. ..... 5
RECOMMENDED OPERATING CHARACTERISTICS............................................................ 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 6
ADC (ANALOG-TO-DIGITAL CONVERTER)........................................................................... 6
CDS/VGA PARAMETERS........................................................................................................6
FREQUENCY SYNTHESIZER PARAMETERS .......................................................................6
SERIAL INTERFACE TIMING SPECIFICATIONS................................................................... 7
2 GENERAL DESCRIPTION ........................................................................................................8
3 OPERATION .............................................................................................................................. 9
3.1 Black Level Adjustment .................................................................................................... 10
3.2 Gain Adjust Block ............................................................................................................. 12
3.3 13-to-10 Bit Compander ...................................................................................................13
3.4 Timing Generator .............................................................................................................15
3.4.1 Vertical and Horizontal Timing Mode ..................................................................15
3.4.2 Horizontal Only Timing Mode ..............................................................................16
3.4.3 Slave mode .........................................................................................................17
3.4.4 Horizontal Timing Generator ...............................................................................17
3.4.5 Vertical Timing Generator ...................................................................................19
3.4.6 Frame Timing ......................................................................................................19
3.5 Frequency Synthesizer ....................................................................................................19
3.6 8-Bit General Purpose DACs ...........................................................................................20
3.7 Stand By Mode ................................................................................................................ 20
3.8 Preview Mode ..................................................................................................................21
3.9 Serial Interface .................................................................................................................21
3.10 Recommended Register Settings ..................................................................................21
4 REGISTER DESCRIPTIONS ................................................................................................... 25
4.1 Reset ................................................................................................................................28
4.2 Power Down Control 1......................................................................................................28
4.3 Power Down Control 2......................................................................................................29
4.4 Operation Control 1........................................................................................................... 29
4.5 Operation Control 2........................................................................................................... 31
4.6 Black Level Control - Accumulator (LSB).......................................................................... 32
4.7 Black Level Control - Accumulator (MSB)......................................................................... 32
4.8 General Black Level.......................................................................................................... 33
4.9 Black Level Control - Loop Gain, Clamp Length............................................................... 33
4.10 Gain Calibration - Offset 1 .............................................................................................. 34
4.11 Gain Calibration - Offset 2 .............................................................................................. 34
4.12 Gain Calibration - Offset 3 .............................................................................................. 35
CS7620
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/
Preliminary product info rmation describes products which are i n production, but for whi ch f ull characterization data is not yet available. Advance produ ct i nfor mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reli able. However , the i nformati on is sub ject to change with out no tice and i s provi ded “AS IS” withou t warranty of
any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rig ht s
of third parties. This document i s the propert y of Cirru s Logic, Inc. and implie s no licen se under patent s, copyri ghts, trademarks, or tr ade secrets. No part of
this publication may be copied, reproduced , stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or
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or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing
in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2 DS301PP2
CS7620
4.13 Timing Control - Number of Lines (MSBs)...................................................................... 36
4.14 Timing Control - Number of Lines (LSBs)....................................................................... 38
4.15 Timing Control - Number of Columns (MSBs)................................................................ 38
4.16 Timing Control - Number of Columns (LSBs)................................................................. 39
4.17 Timing Control - Number of Dark Rows.......................................................................... 39
4.18 Timing Control - Start of Black Pixels............................................................................. 40
4.19 Timing Control - End of Black Pixels .............................................................................. 40
4.20 Timing Control - Number of Rows until Active................................................................ 41
4.21 Timing Control - Start of Active Pixels............................................................................ 42
4.22 Timing Control - Vertical Time Division .......................................................................... 42
4.23 Timing Control - Lines in Storage Buffer (MSBs) ........................................................... 43
4.24 Timing Control - Lines in Storage Buffer (LSBs) ............................................................ 43
4.25 Timing Control - Extra Lines of Exposure in Low Resolution Mode (MSBs) .................. 43
4.26 Timing Control - Extra Lines of Exposure in Low Resolution Mode (LSBs) ................... 44
4.27 Timing Control - Vsync Mode, Lines of Exposure in Low Resolution Mode (MSBs)...... 44
4.28 Timing Control - Lines of Exposure in Low Resolution Mode (MSBs)............................ 47
4.29 Timing Control - Polarity of Vertical Shift Outputs .......................................................... 47
4.30 Horizontal Timing Control - H1 ....................................................................................... 48
4.31 Horizontal Timing Control - H2 ....................................................................................... 49
4.32 Horizontal Timing Control - H3 ....................................................................................... 50
4.33 Horizontal Timing Control - H4 ....................................................................................... 51
4.34 Horizontal Timing Control - Analog Delays..................................................................... 52
4.35 Compander - Black Slope, Slopes (MSBs)..................................................................... 53
4.36 Compander - Slope 1 (LSBs) ......................................................................................... 53
4.37 Compander - Slope 2 (LSBs) ......................................................................................... 54
4.38 Compander - Slope 3 (LSBs) ......................................................................................... 54
4.39 Compander - Slope 4 (LSBs) ......................................................................................... 55
4.40 Compander - Offset 1..................................................................................................... 55
4.41 Compander - Offsets (MSBs) ......................................................................................... 56
4.42 Compander - Offset 2 (LSBs)......................................................................................... 56
4.43 Compander - Offset 3 (LSBs)......................................................................................... 57
4.44 Compander - Offset 4 (LSBs)......................................................................................... 57
4.45 Compander - X1 (MSBs)................................................................................................ 58
4.46 Compander - X1 (LSBs)................................................................................................. 58
4.47 Compander - X2 (MSBs)................................................................................................ 59
4.48 Compander - X2 (LSBs)................................................................................................. 59
4.49 Compander - X3 (MSBs)................................................................................................ 60
4.50 Compander - X3 (LSBs)................................................................................................. 60
4.51 Power_up Counter.......................................................................................................... 61
4.52 Valid_data/Dout Edge/Clock_in Divider.......................................................................... 61
4.53 DAC #1 Control .............................................................................................................. 62
4.54 DAC #2 Control .............................................................................................................. 62
4.55 Device ID........................................................................................................................ 63
4.56 Rev Code........................................................................................................................ 63
5 PIN DESCRIPTIONS ............................................................................................................... 64
5.1 Supply .............................................................................................................................. 65
5.2 Ground ............................................................................................................................. 65
5.3 CMOS Input ..................................................................................................................... 65
5.4 CMOS Analog Input ......................................................................................................... 66
5.5 CMOS Analog Output ...................................................................................................... 66
5.6 CMOS 4 mA Output ......................................................................................................... 66
5.7 CMOS 28 mA Output ....................................................................................................... 67
5.8 Misc ................................................................................................................................. 67
6 PACKAGE DIMENSIONS ....................................................................................................... 68
DS301PP2 3
LIST OF FIGURES
Figure 1. SEN Timing......................................................................................................................... 7
Figure 2. Serial Write Timing........... ....... ...... ....... ...... ....... ...... ............................................. ............. .. 7
Figure 3. Read Data Timing ............................................................................................................... 7
Figure 4. Digital Camera Block Diagram............................................................................................ 8
Figure 5. CS7620 Block Diagram....................................................................................................... 8
Figure 6. Idealized CCD output waveform .........................................................................................9
Figure 7. Transfer function of VGA circuit (assuming full scale level of 1.07V)................................ 10
Figure 8. Block diagram of CDS/VGA circuit.................................................................................... 10
Figure 9. Idealized timing diagram of VGA/CDS circuit.................................................................... 11
Figure 10. Black level adjustment loop............................................................................................. 11
Figure 11. Transfer function of Vin to Gain Adjust output Block (assuming full scale level of 1.07V)13
Figure 12. Gain Adjust output Block................................................................................................. 13
Figure 13. 13-to-10 bit compander................................................................................................... 15
Figure 14. CS7620 output data and clocks ...................................................................................... 15
Figure 15. CS7620 output data and clocks ...................................................................................... 16
Figure 16. Picture Signal Timing...................................................................................................... 16
Figure 17. Signal Timing for Horizontal Only Mode.......................................................................... 17
Figure 18. Signal Timing for Slave Mode .........................................................................................17
Figure 19. Detailed Signal Timing Showing Internal Clock Phases ................................................. 18
Figure 20. Default Timing of Horizontal Signals to the CCD ............................................................ 18
Figure 21. High Resolution Mode..................................................................................................... 20
Figure 22. Low Resolution Mode...................................................................................................... 20
Figure 23. Typical Connection Diagram Using Vertical and Horizontal Timing Mode...................... 22
Figure 24. Typical Connection Diagram Using Horizontal Only Timing Mode ................................. 23
Figure 25. Typical Connection Diagram Using Slave Mode............................................................. 24
Figure 26. Transfer Function of Analog Input to Digital Output (assuming full scale level of 1.07V)36
Figure 27. Transfer Function of ADC with Fixed Gain Settings (assuming full scale level of 1.07V)37
Figure 28. Typical CCD Pixel Arrangement ..................................................................................... 41
Figure 29. 2 million pixel IBM CCD (5:1 reduction) .......................................................................... 46
Figure 30. 2 million pixel IBM CCD (5:1 reduction) RGB pattern ..................................................... 46
Figure 31. 1.3 million pixel IBM CCD (8:2 reduction) ....................................................................... 46
Figure 32. 1.3 million pixel IBM CCD (4:1 reduction) RGB pattern.................................................. 46
Figure 33. Vertical Timing Division for Low Resolution Mode.......................................................... 46
CS7620
LIST OF TABLES
Table 1. Companding Operational Control....................................................................................... 14
Table 2. Default Phases for Horizontal Signal Edges ...................................................................... 18
Table 3. Different Resolution Operating Modes ............................................................................... 19
Table 4. General Purpose DAC specifications................................................................................. 20
Table 5. IBM35CCD2PIX1 ............................................................................................................... 25
Table 6. IBM35CCD13PIX ............................................................................................................... 25
Table 7. Register Description........................................................................................................... 25
Table 8. Different Resolution Operating Modes ............................................................................... 30
Table 9. Full Scale Level Choices.................................................................................................... 32
Table 10. Offset Range .................................................................................................................... 32
Table 11. Black Loop Time Constant............................................................................................... 33
4 DS301PP2
1 CHARACTERISTICS/SPECIFICATIONS
CS7620
DIGITAL CHARACTERISTICS (T
= 25 °C; VDD_Ring = 5 V)
A
Parameter Symbol Min Typ Max Units
Logic Inputs
High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I
Logic Outputs
High-Level Output Source Current @ IOH = 4mA V
Low-Level Output Sink Current @ I
(H1-H4) Output Source Current @ I
(H1-H4) Output Sink Current @ I
= 4mA V
OL
OH = 24mA
OL = 24 mA
V
OH_HCLK
V
OL_HCLK
3-State Leakage Current I
POWER CONSUMPTION (T
= 25 °C; VAA = VDD = 5 V; Output Load = 30 pF)
A
Parameter Symbol Min Typ Max Units
Power Dissipation Peak Mode
Preview Mode
Stand By Down
Analog Power Supply Current Peak Mode
Preview Mode
Stand By Down
Digital Power Supply Current Peak/Preview Mode
Stand By Mode
IN
OH
OL
OZ
IH
IL
P
P
P
DLR
DPD
I
AN
I
ALR
I
APD
I
DN
I
DPD
VDD_Ring-0.8 - - V
--0.8V
--10
VDD-0.4 - V
--0.4V
VDD-0.4 V
--10
D
-
-
-
-
-
-
-
-
375
275
0.125
60
40
0.025
15
0
µ
0.4 V
µ
-
-
-
-
-
-
-
-
mW
mW
mW
mA
mA
mA
mA
mA
A
A
RECOMMENDED OPERATING CHARACTERISTICS
Parameter Symbol Min Typ Max Units
Power Supply Voltage V
Power Supply Voltage for Digital Pads V
Power Supply Voltage for Horizontal CCD Signal Outputs V
GNDA to GNDD Voltage Differential 10 mV
Clock Frequency Range 8 160 MHz
Analog Full Scale Input Voltage Range (w/ fs_lvl = 10)
(w/ fs_lvl = 01)
(w/ fs_lvl = 00)
DS301PP2 5
, V
AA1
V
DDD
DD_Ring
AA3
A
IN
AA2
,
4.5 5.0 5.5 V
3.0 3.3/5.0 5.5 V
3.0 3.3/5.0 5.5 V
-1.60
1.07
0.53
-V
p-p
CS7620
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
Power Supply Voltage V
Digital Input Voltage GNDD-0.3 V
Analog Input Voltage A
Input Current (except supply pins) 10 mA
Ambient Temperature Range 70 +70 °C
Lead Solder Temperature (10sec duration) +260 °C
Storage Temperature Range -65 +150 °C
WARNING: WARNING:Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
ADC (ANALOG-TO-DIGITAL CONVERTER)
Parameter Symbol Min Typ Max Unit
Input Voltage Range (w/ fs_lvl = 10)
(w/ fs_lvl = 01)
(w/ fs_lvl = 00)
ADC resolution - 10 - bits
Conversion Rate Maximum 16 - - MHz
Total Differential Non-Linearity - ±1 - LSB
Total Integral Non-Linearity - ±1 - LSB
, V
AA1
V
AA3
V
DD_Ring
V
DDD
IN
AA2
,
,
-0.3 7.0 V
,
GNDA-0.3 V
-1.60
1.07
.53
+0.3 V
DDD
+0.3 V
AAI
-V
0-p
CDS/VGA PARAMETERS
Parameter Symbol Min Typ Max Unit
Input Voltage Range (w/ fs_lvl = 10)
(w/ fs_lvl = 01)
(w/ fs_lvl = 00)
Total Gain Range A
Input Referred Noise (rms) Maximum Gain Setting Vn
VGA
VGA
-1.60
-V
0-p
1.07
.53
- 18 - dB
--0.2 mV
FREQUENCY SYNTHESIZER PARAMETERS
Parameter Symbol Min Typ Max Unit
CLKIN Frequency F
PLL Output Frequency F
CLKIN Duty Cycle D
clock_in
PLL_OUT
clock_in
Output Jitter - 200 - ps
Duty Cycle - 50 - %
PLL Acquisition Time - 200 - µs
6 DS301PP2
8 - 160 MHz
8 - 16 MHz
20 - 80 %
CS7620
SERIAL INTERFACE TIMING SPECIFICATIONS
Description Symbol Minimum Maximum Unit
Enable Setup t1 10 - ns
SDAT Setup t2 10 - ns
SDAT Hold t3 10 - ns
Serial Clock Period (Note 1) t4 143 - ns
Write Data Invalid t5 0 10 ns
Read Data Valid t6 0 10 ns
Clock to Disable t7 143 - ns
Rise to SEN Fall t8 200 - ns
SEN
Notes: 1. the minimum serial clock period must be longer than two pixel clock periods.
SEN
t1
SCLK
t7 t8
SDATI
SEN
SCLK
SDATI
SCLK
SDATI
R/W, ADDR <6.0> DATA <7.0>
Figure 1. SEN Timing
t4
R/W A6 A5 A6 A3
t2 t3
Figure 2. Serial Write Timing
t5 t6
A0 XX (DON’T CARE)
SDATO
D7 D6 D5
Figure 3. Read Data Timing
DS301PP2 7
CS7620
2 GENERAL DESCRIPTION
The CS7620 forms the heart of a four chip digital
CCD Camera. The four chips include the CCD imager, the CS7620 CCD digitizer, a vertical drive interface chip and a backend DSP chip to further
process the digital data (see Figure 4.) The CS7620
has a built-in timing generator which works with
imagers from IBM and Polaroid. If other CCDs are
used, the internal timing generator can be bypassed
and replaced by an external device, which outputs
the appropriate timing signals.
The patented DRX technology allows the CS7620
to output data with 13-bit dynamic range, and at the
CS7620
CDS/ADC
CCD
Timing Control
Vertical Drive
same time reducing the power consu mption to a 10bit equivalent A/D converter.
The digitized output is either available in 13-bits,
12-bits or 10-bits. The 10-bit output is created by
companding the 13-bit A/D output to 10-bits. The
companding curve consists of 4 linear segments,
where each slope and each start point is user programmable. Two output control signals and one
output clock provide synchronization with the output data.
A block diagram of the CS7620 chip is shown in
Figure 5.
Backend
DSP
Video Output
LCD Panel
AIN
RG
H1
H2
H3
H4
CLOCK_IN
BYPASS_PLL
DIAG[1:0]
+5 V to -5 V
DC-DC converter
Figure 4. Digital Camera Block Diagram
Σ
Analog
Clock
Generator
PLL
DAC1 DAC2 Serial Interface
DAC_OUT1
CDS/VGA A/D
DAC_OUT2
Black
Level
SEN
SDATI SDATO SCLK
Gain
Adjust
+5 V
13 to 10-bit
Compander
V1 V2 V3V4S1 S2 S3 S4
Reference
Timing
Generator
VDD[5]
GND[5]
M
U
X
DOUT[12:0]
(up to 3 may be unused)
CLKO
CLAMP
SCAN_MODE
PWR_DN
RST
TEST
REF_CAPP
1 µF
REF_CAPN
BG_RES
10 k
Ω
LINE_ENA
EXPOSE
HSYNC
RD_OUT
Figure 5. CS7620 Block Diagram
8 DS301PP2
CS7620
3OPERATION
CDS/VGA (correlated double sampling/variable gain amplification)
An idealized waveform of the CCD output is
shown in Figure 6.
The CCD output contains reset noise, thermal
noise, and 1/f noise generated in the CCD output
circuit. This degrades the S/N ratio and must be
cancelled. Since the noise during the active video
portion of the CCD signal is assumed to be correlated with the noise during the feed through portion
of the signal, this noise can be cancelled by subtracting the feed through level from the video level.
This operation is called correlated double sampling. The active video signal is the difference between the feed through and video levels. The active
video signal varies according to light conditions. In
order to insure that the full dynamic range of the
ADC is utilized even under low light conditions,
the CCD output is amplified using a VGA. The
gain control is provided by a 2 bit control word
generated by an ADC after stage 1, which has a
gain of 1. Based on the input voltage, a gain of 1x,
2x, 4x, or 8x is subsequently applied to the signal.
The amount of gain is later adjusted in the digital
section. After the VGA, the signal gets digitized by
a 10 bit ADC. The 2 bit ADC output is used in
combination with the 10 bit ADC output to produce
a 13 bit output.
Adding more gain before the ADC does not offer
performance improvement because the noise of the
CCD (after gain is applied to it) begins to dominate
over the quantization noise. Any additional gain
should be done in digital since the performance is
the same as when the ADC output has the additional gain applied.
In order to add more flexibility, the full scale input
range is programmable through register 07h. This
setting will determine what input level maps to the
highest ADC output code. Thus depending on the
saturation level of the particular CCD used in the
system, an appropriate full scale input level can be
chosen in the CS7620. The choices of full scale input level are 1.6V, 1.07V, 0.53V with 1.07V the
default. In the remainder of this document, all the
figures and discussions assume a full scale level of
1.07 is used. If a different full scale level is used,
all the voltages scale up or down by x1.5 or x0.5 for
1.6V and 0.53V full scale levels respectively.
The transfer function of the VGA portion of the cir-
cuit is shown in Figure 7 with full scale level =
1.07. It is assumed that the CDS has already been
performed. If desired, the gain switching functionality can be disabled and forced to a fixed gain of
8x, 4x, 2x, or 1x. This way any dynamic range enhancement is lost and the digital output is only 10
bits. If a fixed gain of 1x is selected, DOUT[12:3]
is used as the output, a fixed gain of 2x will use
DOUT[11:2], etc. In order to use this mode, the
PIXEL PERIOD
RESET LEVEL
VIDEO
RANGE
FEED THROUGH
LEVEL
VIDEO LEVEL
Figure 6. Idealized CCD output waveform
DS301PP2 9
SIGNAL
DARK
MAX. BRIGHTNESS
CS7620
fixed gain register (16h) should be set and the calibration offset registers (10h - 12h) should be set to
0.
The CDS/VGA circuit is composed of three stages.
The first stage has a fixed gain of 1, and the second
and third stages have variable gain with a combined
gain range of 1 to 8 (0-18 dB). Figure 8 shows a
block diagram of the CDS/VGA circuit. The total
gain is A = (C2/C3)(C4/C5) which is adjusted by
varying C3 and C5. The capacitor Cb on the front
of stage 1 is for black level adjustment and will be
discussed in detail later.
This circuit utilizes a two phase non-overlapping
clock to perform the desired CDS function. The
VOUT (V)
1.07
two phase clock also allows the video signal to be
passed to the output while retaining a positive polarity signal. Figure 9 shows a timing diagram of
the two phase clock along with the CCD signal and
output signals of stages one, two and three.
There is an internal mid-scale DC bias level circuit
at the input pin. This allows AC coupling into the
CS7620 with a capacitor and having the input automatically biased to mid-supply without worrying
about external circuitry to perform this task.
3.1 Black Level Adjustment
In order to maintain a constant reference level for
black pixels, a feedback loop is implemented that
VIN
0.5
100 KΩ
100 KΩ
VREF
1X2X4X8X
0.530.270.13
00 01 10 11
Figure 7. Transfer function of VGA circuit (assuming full scale level of 1.07V)
Φ2
C3
C4
-A2
Vo2
STAGE 2 STAGE 3
2
CONTROLS C3, C5
CONTROLS GAIN ADJUST BLOCK IN DIGITAL
Φ1
-A3
C1
Cb
Φ1
C1
-A1
STAGE 1
C2
Vo1
ADC
1.07
ADC OUTPUT
C5
VOUT
VIN (V)
TO AOUT CIRCUITRY
Figure 8. Block diagram of CDS/VGA circuit
10 DS301PP2
CS7620
sets the black level value at the output of the ADC
to 64 in the 13 bit digital code. This loop is active
during the optically black pixels which are output
at the beginning and end of a frame as well as during a portion of the horizontal blanking period. The
presence of black pixels in the CCD output is indicated by the CLAMP pulse, which can either be
supplied externally or generated internally if the
timing for the CCD is generated by the CS7620.
CCD
INPUT
SIGNAL
Φ1
V(1)
The black level can also be written to through the
serial port.
In order to acquire a starting value for the black level, the loop will run over the several lines of black
pixels at the beginning of the frame. The block diagram of the loop is shown in Figure 10. The update rate is once per line during active pixel lines,
and once every (n + 10) pixels during the optical
black lines.
V(2) V(3)
VIN
CDS/VGA
Σ
FU = UPDATE FREQUENCY
= PIXEL FREQUENCY
F
P
Φ2
OUT OF
STAGE 1
OUT OF
STAGE 2
OUT OF
STAGE 3
V(1) V(2) V(3)
V(1) V(2) V(3)
V(1) V(2)
Figure 9. Idealized timing diagram of VGA/CDS circuit
DAC
ADC
10
‘64’
+
-
CLIP
7
F
U
-1
Z
BLK LVL LOOP
GAIN REG
K
BINARY
TO
THERM
+
+
Figure 10. Black level adjustment loop
FROM SERIAL INTERFACE
MUX
-1
Z
F
P
9
DS301PP2 11
The open-loop transfer function of the black level
K
1
256
-------- -
blk_gain=
τ
1
1nK–()ln
-------------------------- -–
1
fu
-----
=
τ
1
1
nK
2
-------–
ln
--------------------------- -–
1
fu
-----
=
τ
1
1
nK
8
-------–
ln
--------------------------- -–
1
fu
-----
=
τ
1
1
nK
4
-------–
ln
--------------------------- -–
1
fu
-----
=
adjustment loop is
Hz()
Kn×
-------------=
z1–
blk_gain = 1, 2, 4, or 8
For a fixed gain of 4:
CS7620
1
τ
--------------------------- -–
=
1
ln
nK
-------–
2
-----
fu
1
where blk_gain is programmable through a register
and n = # of black pixels during clamp time, which
is also programmable. The value of Kxn will determine the open-loop gain of the system. The settling
time for the loop can be calculated using the following formula:
For offset range=1 (reg 06h, bit 0)
For offset range =0
During fixed gain mode the time constant is a little
different.
For a fixed gain of 1:
For a fixed gain of 2:
12 DS301PP2
For a fixed gain of 8:
1
τ
-------------------------- -–
=
1nK–()ln
1
-----
fu
In order to achieve no ringing in the settling use,
n
----
for offset range = 1, and for offset
1≤
K
n
------2K
1≤
range = 0.
The 9 MSBs of the black level accumulator can be
read or written through a register. If written, the
LSBs are set to zero. The black level is set to “8 ” in
a 10-bit digital output representation. In a 13-bit
representation, it is set to “64.” The power-up default value in the accumulator is at mid level.
Also note that the black level adjust loop can be
disabled. In addition, the black level can be programmed through the serial port.
3.2 Gain Adjust Block
In order to increase the dynamic range of the ADC,
a variable gain, whose value is determined by the
signal level, is applied to each pixel. This allows
for 13 bits of dynamic range and 10 bits of resolution after accounting for the significance of the
ADC output bits. The gain applied in the analog is
illustrated in the transfer curve in Figure 7. Once
the signal is digitized, the gain adjust block uses the
gain information for a given pixel word and shifts
its bits accordingly. For example, using the default
full scale level of 1.07V, if Vin = 0.3 V, the VGA
would choose a gain of 2X so the ADC input is 0.6
V. The 10-bit output of the ADC (with no black
level) is (0.6/1.07) × 1024 = 574, or “1000111110.”
in binary. The gain adjust block will take this value
CS7620
plus the bits representing the 2x gain and divide the
output by two (shift right by 1). The output of the
gain adjust block is then “0100011111.000.” Note
that the decimal point is virtual, having no existence in silicon. It is representing the fact that we
keep 3 extra bits of lower significance in the output.
In the same manner, if Vin = 0.75 V, a gain of 1X
would be chosen and the output of the gain adjust
block would be “1011001101000.” The transfer
function of the Vin/gain adjust out is shown in
Figure 11.
A block diagram of the gain adjust block is shown
in Figure 12.
DIG ADJUST OUT (13 BITS)
8192
Since the analog gain changes do not match the
digital shifts exactly, there is a potential to have
non-monotonic digital output. In order to remove
this problem, calibration is performed. During calibration, offset values are found that will be used to
counteract the errors caused by the analog gain
mismatch. Using these offset values, the final output is a monotonic continuous 13-bit value.
3.3 13-to-10 Bit Compander
While a 13 bit output may be useful in some applications, others may require the standard 10 bit output. To accommodate this and yet still retain the
advantages of the increased dynamic range, a 13to-10 (or 13-to-12) bit compander is included. By
4096
2048
1024
0
0.13
00 01 10 11
Figure 11. Transfer function of Vin to Gain Adjust output Block (assuming full scale level of 1.07V)
VGA_ADC OUTPUT
2
Figure 12. Gain Adjust output Block
0.530.27
ADC OUTPUT
10
GAIN ADJUST
SHIFT BY 0,1,2, OR 3
1X2X4X8X
13
1.07
TO DIGITAL GAIN
VIN (V)
ADC OUTPUT
DS301PP2 13
CS7620
using the picture content as a guide, the user can select which curve will lead to the best overall dynamic range in the picture. The Companding
module takes 13-bit data as input, and outputs either 10-bit companded data, 12-bit MSB-clipped
data or it lets the original 13-bit data pass through.
By programming the compander in the way that is
shown in Figure 13, it is possible to compensate for
backlighting conditions. Details in dark areas stay
visible, even in very complex lighting conditions.
These three modes can be selected through 2 register bits in operational control.
Bits_out register bits Output mode
0x 10 bits companded
10 13 bits
11 12 bits (clipped)
Table 1. Companding Operational Control
In the 12-bit clipped mode, any input above 4095
gets clipped to 4095. In the 10-bit companded
mode, the input gets companded through a four
segment, three knees, fully programmable curve.
The second option clips all pixel values less than
black (code 64 in the 13 bit data) to a programmable offset value, offset1. This may be set to 0 if desired. This option will lose the “blacker-thanblack” pixel information, but allow for slightly
more dynamic range. Note: If using the linear mode
(option 1), offset1 must be set to 8.
Registers x1 through x3 should be programmed
with the x coordinates of each one of the three
knees.
Registers slope1 through slope4 should be programmed with 256 multiplied by the calculated
slopes.
Finally, the offsets can be programmed following
the formulas below:
y1 = slope1/256 × (x1-64) + offset1
y2 = slope2/256 × (x2-x1) + y1
y3 = slope3/256 × (x3-x2) + y2
offset2 = y1 - (x1 × slope2 / 256)
offset3 = y2 - (x2 × slope3 / 256)
To program the curve, the placement of the t hree
knees in the companding curve must be determined. The next step is to determine the slope of
the four segments created by the three knees (slope
for each segment is defined as delta y / delta x). Finally, offsets must be calculated to keep the companding curve continuous.
A fourth knee exists in the curve, which represents
the black level value. There are two options for the
10-bit black value. In case one, a linear mapping is
employed such that “blacker-than-black” pixel information is kept, with black (code 64 in the 13 bit
data) being defined as code 8 in the 10 bit domain.
offset4 = y3 - (x3 × slope4 / 256)
(use integer division and discard the remainder)
When using the 10 bit companded output, be aware
of the non-linearity of the output data. If linear output is needed to perform AWB or AGC, a linear
curve can be implemented to gather statistics. This
can be achieved by writing 8191 to x1 (set register
38h to 1fh and set register 39h to ffh) and setting
slope1 to 32 (set register 2eh to 00010xxxb and set
register 2fh to 20h). Once the statistics have been
gathered, all four registers should be returned to
their previous values before taking the actual picture.
14 DS301PP2
CS7620
The output of the compander is available at the pins
DOUT<9:0> and it makes transitions either at the
falling or rising edges of the pixel rate clock CLKO, controlled by a register bit. The Falling edge
option is shown in Figure 14.
Two options exist for outputting data. The first option will output the pixel rate clock on the CLKO
pin. The polarity of the pixel clock out of the pin is
programmable so that the user may choose the appropriate clock edge to latch in the data. Based on
the RD_OUT and HSYNC signals, the user will be
able to determine when he is over active pixels. The
second option will output a data_valid signal on the
CLKO pin that is synchronous with the input clock
(Figure 15). The data_valid signal will only toggle
over active pixels. The user may then latch the data
during this valid time. Note: DATA_VALID mode
cannot be used if the system clock runs at the pixel
rate.
3.4 Timing Generator
There are three timing options available with the
CS7620. The chip may produce all the vertical and
horizontal timing for the imager, only the horizontal timing, or the chip may be used in a complete
slave mode and not produce any of the CCD timing
at all. Each will be discussed in detail in this section.
3.4.1 Vertical and Horizontal Timing Mode
To select this option, the user must tie the
BYPASS_PLL pin low and select the proper internal timing mode in the timing mode register. The
CS7620 is the master of the clocking. It will provide vertical outputs and horizontal outputs. In this
mode, the user must control two signals. The first is
the master PWR_DN signal. When this signal is
high, all of the CS7620 powers down except for the
OFFSET4
OFFSET3
OFFSET2
CLKO
CODE_OUT
1023
OFFSET1
(x2,y2)
SLOPE3
(x1,y1)
64
SLOPE2
SLOPE1
X1 X2 X3
Figure 13. 13-to-10 bit compander
(x3,y3)
SLOPE4
8191
CODE_IN
DOUT<9:0>
Figure 14. CS7620 output data and clocks
DS301PP2 15
CS7620
DAC outputs (these may be powered down through
register control if they are not being used). The second signal is the EXPOSE signal. This signal
should go high at the beginning of exposure and
low at the beginning of readout. The suggested timing of these signals is shown in Figure 16. Note that
the chip must power up at least 500 µs before readout begins. The LINE_ENA and CLAMP pins are
not used in this mode.
3.4.2 Horizontal Only Timing Mode
To select this mode, the user must set the
BYPASS_PLL pin low and select external timing
mode in the timing mode register. The CS7620 is
the master of the pixel rate timing, but the line and
frame timing is controlled externall y. In this mode,
the user must control four signals- PWR_DN, EX-
POSE, LINE_ENA, and CLAMP. The master
PWR_DN signal may be used to conserve power
during non-readout time. The EXPOSE pin is redefined as the non-readout signal. When high, the
H1-H4 and RG signals are set in their idle state
(low for H1-H4, high for RG). The LINE-ENA pin
should be high during the vertical shift and load periods. This will hold the H1-H4 signals in their
user-programmable default states. The CLAMP
pin should be high when over dark reference
(black) pixels. The suggested timing for these signals is shown in Figure 17. Note that the chip
should power up at least 500 µ s before the beginning of readout. The CLAMP signal may also be
high during the dark pixel lines at the beginning of
the frame.
SYSTEM_CLK
CLKO (DATA_VALID)
DOUT<9:0>
T
EXP
>500 µs
Figure 15. CS7620 output data and clocks
POWERDOWN SIGNAL
EXPOSE SIGNAL
T
READOUT
T
FRAME
Figure 16. Picture Signal Timing
WARNING: NOTE: It is reco mmended to keep the par t in power down mode while not in use to reduce power
16 DS301PP2
CS7620
3.4.3 Slave mode
To select this mode, the user must set the
BYPASS_PLL pin high and select external timing
mode in the timing register. The CS7620 timing is
now slaved off of an external source and supplied
with sampling clocks for feedthrough and data. In
this mode, the user must control five signalsPWR_DN, EXPOSE, CLAMP, CK_FT
(CLOCK_IN), and CK_DT (LINE_ENA). The
master PWR_DN signal may be used to conserve
power during non-readout time. The EXPOSE pin
is redefined as the non-readout signal. Using the
falling edge of this signal, the chip will delay its
RD_OUT pin output by the appropriate amount as
determined by the chip latency so that it will go active at the correct point in the data stream. CLAMP
should be high when over the dark reference pixels.
The CLOCK_IN and LINE_ENA pins are rede-
fined as the CK_FT and CK_DT signals, which
sample the feedthrough and data levels, respectively. The suggested timing for PWR_DN, EXPOSE,
and CLAMP is the same as shown previously in
Figures 16 and 17. The timing for CK_FT
(CLOCK-IN) and CK_DT (LINE-ENA) is shown
in Figure 18.
3.4.4 Horizontal Timing Generator
During every horizontal line period the data from
the horizontal shift register is shifted out on the
CCD output pin one pixel at a t ime. The analog timing generator creates the required driving signals to
control the CCD horizontal timing as well as the
analog sampling signals. The timing signals involved in this operation are H1, H2, H3, H4 and
RG. The exact timing of these signals can be con-
V SHIFT
& LOAD
CCD
INPUT
SIGNAL
CK_FT
CK_DT
CLAMP
LINE_ENA SIGNAL
EXTENDED
PIXELS
Figure 17. Signal Timing for Horizontal Only Mode
DARK
PIXELS
T
LINE
SIGNAL
ACTIVE
PIXELS
ACTIVE
PIXELS
V SHIFT
& LOAD
T
LINE+1
Figure 18. Signal Timing for Slave Mode
DS301PP2 17
Ideal
CCD Signal
CS7620
internal
sampling
clocks
Figure 19. Detailed Signal Timing Showing Internal Clock Phases
CK_FT
CK_DT
Ideal
CCD Signal
H1
H2
default
settings
H3
H4
RG
t0t4 t5 t6 t7 t0t3 t4 t5 t6 t7t1 t2 t3t1 t2
Figure 20. Default Timing of Horizontal Signals to the CCD
trolled through the serial interface as described below.
The pixel period is broken down into 8 equal time
periods. By delaying the clock a given number of
these time periods, different phases are created.
This is shown in Figure 19. These clock phases are
labeled t0-t7 and are shown relative to an idealized
CCD signal and the internal sampling signals.
Using these eight clock phases, the user may set the
rising and falling edges of each horizontal pixel
clock at 1/8 of a pixel clock period. In addition, t he
18 DS301PP2
user may set each horizontal signal to a default
state when the output lines are to be held constant
during blanking. The default timing for the horizontal signals is shown in Figure 20 and Table 2.
See the register listing for more details.
Signal Rising edge Falling edge Hold level
H1 t0 t5 high (‘1’)
H2 t2 t7 high (‘1’)
H3 t4 t1 high (‘1’)
H4 t6 t3 low (‘0’)
Table 2. Default Phases for Horizontal Signal Edges
CS7620
3.4.5 Vertical Timing Generator
The signals involved in the vertical timing generator are the vertical shift clocks V1 through V4 and
the storage clocks S1 through S4. The vertical timing generator generates the signals needed by the
CCD to shift charge vertically down into the horizontal shift register. The chip is the timing master,
and it generates the signals needed by the horizontal timing generator and other modules to operate.
The timing generator is controlled externally by
various signals; the falling edge of the input signal
EXPOSE sets the part into readout mode, and after
this edge, it generates the timing signals to output a
full frame, provided that RST and PWR_DN are
not active.
The mode register selects the CCD timing, and the
resolution mode to be generated. Please refer to
IBM-CCD datasheet for more info.
Mode value Mode
000 IBM35CCD2PIX1 and IBM35CCDPIX13
CCD high resolution mode
001 IBM35CCD2PIX1 CCD low resolution
(viewfinder) mode
010-100 reserved
101 IBM35CCD13PIX CCD (2x2) low resolu-
tion (viewfinder) mode
110 IBM35CCD13PIX CCD (3x4) low resolu-
tion (viewfinder) mode
111 external timing used
Table 3. Different Resolution Operating Modes
The timing module’s functionality can be configured through the use of registers. Note that before
entering a preview mode, all of the programmable
parameters must be set prior to this.
Shiftl_num is the number of lines in the shift buffer.
Tdv is the length of the minimum vertical timing
interval measured in pixel clocks.
Num_pixels is the number of pixels per line
V_polarity allows to switch the polarity of all the
vertical timing signals going to the CCD.
Blk_begin is the first black pixel in a line
Blk_end is the last black pixel in a line
Drk_rws_fst is the number of black lines to be
readout at the beginning of the frame
Drk_rws_lst is the number of black lines to be
readout at the end of the frame
3.4.6 Frame Timing
Figures 21 and 22 illustrates the frame timing for
the low and high resolution modes.
HSYNC is high during the active pixel area, and it
is low during vertical shift (horizontal and vertical
blanking periods).
RD_OUT is triggered by the falling edge of expose, it is delayed by the chip latency, and it
switches back high once the last pixel has been read
out of the CS7620. RD_OUT is low during the active pixel areas and during the horizontal blanking
periods (vertical line shifts) and it goes high during
the vertical blanking period, between frames.
The dotted lines in Figures 21 and 22 correspond to
the vsync option which can be enabled by writing a
one to register vsync_md (register 25h bit 5). This
causes the RD_OUT signal to behave like a verti cal
sync signal. It makes the signals HSYNC and
RD_OUT the same length at the beginning of a
new frame (see Figures 21 and 22).
3.5 Frequency Synthesizer
Since multiple clock phases and timing are required for the pixel rate clocks controlling the CCD
imager, the clock generator contains a PLL circuit
to generate the proper timing. “Frequency Synthesizer Parameters” on page 6 shows the requirements for this PLL. The frequency of the input
clock may be set from 1 to 20X the pixel clk frequency, in integer mult iples. The freq uency us ed is
Num_lines is the number of lines per frame.
DS301PP2 19
CS7620
register programmable in terms of multiples of the
pixel clock rate.
3.6 8-Bit General Purpose DACs
Two 8-bit current-output DACs are available for
external use. Table 4 shows the output specifications of these DACs.
3.7 Stand By Mode
Stand-by mode can be entered using the PWR_DN
pin. All circuitry on chip including the DACs can
Expose
vsync_md = 1vsync_md = 0
RD_OUT
HSYNC
Parameter High impedance
mode
Iout 2.155 mA 8.7 mA
loading 464
Table 4. General Purpose DAC specifications
Ω
Low impedance
mode
Ω
115
be powered down. Various functional blocks can
be powered down individually, and are controlled
through registers. Note that the DACs can be powered down in that way if not in use. During Stand
By mode, the register contents are maintained and
V1 ... V4
S1 ... S4
H1 ... H4
Expose
RD_OUT
HSYNC
V1 ... V4
S1 ... S4
H1 ... H4
262 lines
don’t care
first read-out line last read-out line
Figure 21. High Resolution Mode
vsync_md = 0
vsync_md = 1
262 lines
262 lines
first read-out line last read-out line
first read-out line
picture n picture n picture (n+1)
Figure 22. Low Resolution Mode
20 DS301PP2
CS7620
do not have to be reprogrammed at the next power
up.
3.8 Preview Mode
It is strongly recommend that the chip should be
kept in Stand By mode when not in use in order to
save power. When in preview mode, a user may
wish to cut down the resolution of the ADC output
to 6 bits in order to reduce the power consumption
of the CS7620. In this mode, the current is reduced
by 20 mA. With the DRX (Dynamic Range eXtension) circuitry, 3 bits of dynamic range are added to
the 6-bit ADC output producing a 9-bit output. The
pins DOUT[12:4] are used to output the digitized
data in preview or Stand By mode.
3.9 Serial Interface
The serial interface is designed to allow high speed
input to control the chip’s registers. The specifications on this interface are as follows:
Asserting the enable pin, SEN, enables the serial
interface to perform data transfers. Data present on
the SDATI pin is latched into the CS7620 on each
rising edge of the serial clock, SCLK. Data output
on SDATO from the CS7620 is clocked out on the
rising edge of SCLK.
The CS7620 receives only the first 16 rising edges
of the SC LK while SEN is low and then ignores
any remaining SCLK and SDATI information. If
SEN goes high before 16 SCLK pulses have been
received, the CS7620 aborts the serial transfer.
The first bit is the R/W bit. R/W = 1 identifies the
transfer as a read. If (0), the transfer is a write. The
next seven bits define the address. For write transfers, the second byte of the 16-bit packet contains
the data byte. For read transfers, the CS7620 outputs the read data on SDATO after accepting the
address. Address and data are transferred MSB
first. When not reading out data, the SDATO pin is
not driven by the chip (Hi-Z state).
The timing diagrams and specifications are shown
in “Serial Interface Timing Specifications” on
page 7 and Figures “SEN Timing”, “Read Data
Timing”, and “Serial Write Timing” on page 7.
3.10 Recommended Register Settings
These are the values that need to be written to the
registers to change the configuration of the CS7620
to work with each CCD in either low resolution or
high resolution mode. (2 × 2) refers to a RGRGRG
pattern and (3 × 4) refers to a RGBRGB pattern
CCD.
DS301PP2 21
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