Cirrus Logic CS7615-KQ Datasheet
CCD Imager Analog Processor
CS7615
Features
l
10-Bit A/D Converter
l
Multi-Sync CCD Timing Generator,
handles imagers up to 1000 pixels wide
l
Integrated Correlated Double Sampler
l
38 dB Automatic Analog Gain Control
l
Up to 90 dB Total Gain Adjust Range
l
Closed-Loop “Fuzzy” AGC/Exposure
l
Code 16 Black Level Clamp
l
I2C Control Bus
l
4-Phase Vertical CCD Timing Signals
l
No CCD Buffer Amplifier Required
l
Master Clock or Crystal Controlled
Description
The CS7615 is a low-power Analog front-end processor
for standard four-color interline transfer CCD imagers.
The architecture includes a correlated double sampler,
AGC amplifier, black-level clamp, 10-Bit A/D converter,
and a complete multi-sync CCD timing generator. The
analog CCD imager output can be directly connected to
the CS7615 input, which does not require an external
buffer amplifier . The pi xel data i s double sampl ed for i mproved noise performance, and gain adjusted prior to
being digitized by t he A/D conv erter. Feedbac k from t he
A/D converter holds the image black level at code-16
(assumes 8-bit data path), addressing ITU-601 compliance issues. The multi-sync CCD timing generator is
programmed via the I
wide range of interline transfer CCD imagers up to 1000
pixels wide. The CS7615 supports full ITU-601 compliance for images up to 720 pixels wide , and is compatible
with both NTSC and PAL timing. The CS7615 is designed to be used along with either the CS7665 or
CS7666 Digital Color-Space Processor for CCD Cameras, which generates a 4:2:2 component digital video
output.
2
C bus, and can be used with a
CCD Output
Master Clock
CDS/AGC Data Out
AGC
Controller
PLL
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
ORDERING INFORMATION
CS7615-KQ 0° to +70° C 44-pin TQFP
(10 mm × 10 mm × 1.6 mm)
A/D
Converter
Black
Level
Timing
Generator
CCD Timing Signals
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1998
(All Rights Reserved)
Output
Formatter
Register
Block
I2C
Clocks Out
I2C Bus
DS231PP6
JUL ‘98
1
TABLE OF CONTENTS
ANALOG C H A RA C T E RISTICS: ........ ... .................... .............................. ..............3
DIGITAL CHARACTERISTICS: ............................................................................ 3
POWER CONSUMPTION:....................................................................................3
CONTROL PORT CHARACTERISTICS:..............................................................4
SWITCHING CHARACTERISTICS:...................................................................... 5
RECOMMENDED OPERATING CHARACTERISTICS: ....................................... 5
ABSOLUTE MAXIMUM RATINGS:...................................................... ...... ...........5
GENERAL D E SC R IPTION .... .. ..................... ....................................... ................ 6
Overview ......... ......... ....... ......... ......... .......... ...... .......... ......... ....... ......... ....... 6
Interfacing the CS7615 with CS7665 or CS7666 ..................... ..................6
Operatio n .......... .............. .............. ........... .............. .............. .............. ......... 6
CCD Timing Generator ......................................... .... ........................ .. .... .. ..8
Vertical Timing Specifications ..................................................................... 8
Horizontal Timing Specifications .................................................................8
Description of Opera tion . .. ... ....................................... ............................. ... 9
Automatic Gain Control ............................................................................... 9
Correlated Double Sampling (CDS) .......................................................... 11
Analog to Digital Converter ....................................................................... 15
Black Level Adjust to Code 16 (10-bit Code 64) .......................................15
Formatter .................................................................................................. 15
SERIAL CO N T RO L B U S ................ .. ..................... ....................................... ..... 16
Station Address ........................................................................................ 16
Write Operations ................................................................................ 16
Address S e t O p e ra ti o n .. ............................. ....................................... . 16
Read Opera tions ............. .. .............................. .............................. .....16
REGISTER DESCRIPTIONS ............................................................................. 17
PIN DESCR I P T IO N S ............................. .............................. ..............................30
PACKAGE DIMENSIONS ..................................................................................34
CS7615
2 DS231PP6
CS7615
ANALOG CHARACTERISTICS: (T
=25°C; VAA=VDD=5V; Output Load=30pF )
A
Parameter Symbol Min Typ Max Units
Dynamic Performance
Integral Non-Linearity INL - 1 - LSB
Differential Non-Linearity DNL - 0.75 - LSB
Analog Input
Analog Input Capacitance C
IN
-10-pF
Automa tic G a in C o n tr o l
Maximum Gain G
Minimum Gain G
Gain Increment
DIGITAL CHARACTERISTICS: (T
=25°C; VAA=VDD=5V; Output Load=30pF )
A
MAX
MIN
∆
G - 78.4 117.6 mdB
-20-dB
-0-dB
Parameter Symbol Min Typ Max Units
Logic Inputs
High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I
IH
IL
IN
VDD-0.8 - - V
--0.8V
--10mA
Logic Outputs
High-Level Output Source Current @ VOH = VDD-0.4V I
Low-Level Output Sink Current @ V
= 0.4V I
OL
3-State Leakage Current I
OH
OL
OZ
--1mA
--1mA
--10µA
POWER CONSUMPTION: (T
=25°C; VAA=VDD=5V; Output Load=30pF )
A
Parameter Symbol Min Typ Max Units
Power Dissipation P
Analog Power Supply Current Normal Mode
Low-Power Mode
DIgital Power Supply Current Normal Mode
Low-Power Mode
I
AN
I
ALP
I
DN
I
DLP
D
-650-mW
-
-
-
-
99
63
55
22
-
-
-
-
mA
mA
mA
mA
DS231PP6 3
CS7615
CONTROL PORT CHARACTERISTICS: (T
Parameter Symbol Min Typ Max Units
SCL Clock Frequency f
Bus Free Time Between Transmissions t
St art Condition Hold Time t
Clock Pulse Width High
Setup TIme for Repeat Start Condition t
SDAIN Hold Time from SCL Falling t
SDAIN Setup Time from SCL Rising t
SDAIN and SCL Rise Time t
SDAIN and SCL Fall Time t
Setup Time for Stop Condition t
=25°C; VAA=VDD=5V; Output Load=30pF )
A
Low
Stop Start
SDA
t
buf
t
hdst
t
high
SCL
buf
hdst
t
high
t
low
sust
hdd
sud
r
f
susp
Repeated
Start
t
- - 100 kHz
4.7 - -
4.0 - -
4.0
4.7
4.7 - 0--µs
0.25 - -
--1.0µs
--0.3µs
4.0 - -
--µs
Stop
t
hdst
f
t
susp
µ
s
µ
s
µ
s
µ
s
µ
s
µ
s
CL
S
t
low
t
hdd
Figure 1. I2C Timing Diagram
t
sud
t
sust
t
r
4 DS231PP6
CS7615
SWITCHING CHARACTERISTICS: (T
=25°C; VSS=VDD=5V; Output Load=30pF )
A
Parameter Symbol Min Typ Max Units
Crystal Frequency Range f
CRY
6.75 27 MHz
Crystal Oscill ator Duty Cycle 4 0 60 %
CLKO Frequency f
CLK2XO Frequency f
pix
dat
6.75 13.5 MHz
13.5 27 MHz
CLKO duty cycle 50 %
CLK2XO duty cycle 50 %
CLK2XO falling edge to CLKO falling edge 4 8 ns
FR Clock (CCD reset gate clock) Duty Cycle 25 %
H1 Clock
H2 Clock
Duty Cycle 50 %
Duty Cycle 50 %
RECOMMENDED OPERATING CHARACTERISTICS:
V
AC
V
AIN
V
DC
Feedthrough
Level
GND
Figure 2. Analog Input
Parameter Symbol Min Typ Max Units
Power Supply Voltage V
AA
, V
DD
4.5 5.0 5.5 V
GNDA to GNDD Voltage Dif ferential 10 mV
Crystal Frequency Range 6.75 27 MHz
Analog Input AC Range (Figure 2) V
Analog Input DC Offset (Figure 2) V
Analog Input Voltage (Figu re 2) A
AC
DC
IN
01.65V
12 V
018V
ABSOLUTE MAXIMUM RATINGS:
Parameter Symbol Min Max Units
Power Supply Voltage V
AA
, V
DD
Digital Input Voltage GNDD-0.3 (V
Analog Input Voltage - AIN only A
IN
Input Current (except supply pins) 10 mA
Ambient Temperature Range -0 +70 °C
Lead Solder Temperature (10sec duration) +260 °C
Storage Temperature Range -65 +150 °C
-0.3 7.0 V
)+0.3 V
DD
GNDA-(0.3) 20 V
Specifications are su bject to change without notice.
DS231PP6 5
CS7615
GENERAL DESCRIPTION
Overview
The CS7615 performs the analog functions in a
four chip digital CCD Camera. The four main chips
include the CCD imager, the CS7615 CCD digitizer, the CS7665 or CS7666 color space processor,
and a vertical drive interface-chip for the CCD imager. Several CCD imagers (and their associated
vertical drivers) can be used with the CS7615 digitizer and the CS7665 or CS7666 proc essor to form
a simple and cost-effective YCrCb output format
digital camera. The block diagram in Figure 3 illustrates the s ys tem interco nnect.
4:2:2, H.656 VIDEO
IMAGE
PROCESSO R
2
I C
+5 V
CS4952 or
CS4954
2
2
I C BUS
CCD CDS/ADC
7
512x480
VERTICAL
DRIVE
+8 V TO +12 V
CS7615
TIMING
9
DC-DC
CONVERTER
I C
2
CS7665 or CS7666
Figure 3. Typical 4-Chip Digital CCD Camera
Interfacing the CS7615 with CS7665 or CS7666
The CS7666 is a direct replacement for the
CS7665. No board or softwa re cha nges are needed
for existing designs. However, slight changes to
existing hardware and software are necessary to
take advan tage of th e CS766 6. See Figu re 4 and 5
and the CS7666 data she et for m ore det ails.
Operation
The CS7615 digitizer is designed to provide all
necessary an al og functions and conversion to digital data of a standard CCD image r output signal as
well as prov ide all the timin g and control sig nals
for the CCD imager. The architecture includes a
correlated dou ble sampler, va riable gain am plifier
with an integrated AGC loop, black level clamp,
10-bit A/D converter, output formatter, and a complete multi-sync CCD timing generator. The output
of the A/D converter ranges from code 004h to
code 3FBh a nd the form atter adds spec ial end-of active-video (EAV) and start-of-active-video
(SAV) codes to each line, making the output of the
CS7615 simila r to the descrip tion in the ITU-65 6
recommenda tion.
56
55
CS7665CLK2x0 CLOCK
XTAL
32
33
CS7615
39
CLK0
4
10-BIT DATA
Figure 4. CS7615/CS7665 Interface
NC
CS7615
33
32 XTALIN
39
CLK0
4
10-BIT DATA
CS7666NC
55 CLKIN
CCLOKG
56
XTAL
52
Figure 5. CS7615/CS7666 Interface
6 DS231PP6
CS7615
The EAV/SAV code definitions are consistent with
an 8-bit data path. As per the ITU-656 recommen-
dation, the LSB’s of the CS7615 ar e fractional bit s
which are not used when delivering 8-bit output data. In 10-bit mode, all ten digital outputs can be
connected directly to the CS 7665.
The output da ta format from the CS7615 formatte r
is shown in Figure 6. The CS7615 also outputs two
clocks, one at the pi xe l rate and t he other at 2× the
HREF
Blanking period
EAV code (10 bits)
Smpl. Word
0 3FFh
1 000h
2 000h
3
Smpl. Word
4 040h
Binary
1
fv1P3P2P1P
Blank code (10 bits)
repeat above word
4T
00
0
N
T
b
output pixel data rate (see pin description for
CLK2XO). The ou tput of the formatter i s available at the pins D
and it transitions at the fall-
O[0..9]
ing edge of the pixel rate clock CLKO. Figure 7
shows the basic output timing diagram. The falling
edges of CLKO lag t he fall ing ed ges of CLK2XO
by 4 to 8 ns and both clocks hav e approximately
50% duty cycles.
Active video
4T
AV*T
T = output pixel period
During active video,
samples of mosai c d ata;
during vertical blanking,
040h.
At reset or power down, 040h.
SAV code (10 bits)
Smpl. Word
0 3FFh
1 000h
2 000h
3
Binary
fv0P3P2P1P
1
00
0
f
= field bit; 0 (odd field), 1 (even field)
v
= vertical blanking bit; 0 (active video lines), 1(verti cal blanking)
P3P2P1P
DS231PP6 7
= error protection bits (as per ITU-656).
0
Figure 6. CS7615 Output Data Format
CLK2XO
CLKO
D
O[0..9]
CS7615
Figure 7. CS7615 Output Data and Clocks
CCD Timing Generator
The CCD timing and control signal outputs are dictated by the programmable register settings. This
allows for compatibility with a variety of CCDs.
The HSYNC signal is also output for use in a genlock confi guration. The op en-drain HCLK can be
used to clock dc -dc voltage converters whi ch are
typically used to generate the CCD imager bias
voltages. The following description explains the
various output signals provided to the vertical driver and CCD a s well as t he progra mmabl e parame ters that may be set to control these signals.
HREF* - horizontal reference signal. It stays
high during the active video portion of the line.
HENB* - Horizontal shift register clock enable
signal. Enables H1 a nd H2 out of analog timing.
CLAMP* - Black clamp signal provided to the
ADC.
V1X, V2X, V3X, V4X - Vertical register shift
clock. Used both during vertical transfer and
charge read out.
VH1X, VH3X - CCD charge read out pulse.
HCLK - Signal used by the dc - dc converter. In
the norma l mode, it is th e same as HREF; In
fast mode, i t ope rate s at about 16× of the h orizontal line fre quency and is rese t at the beg in-
ning of HREF.
HSYNC - Horizontal sync signal.
OFDX - Overflow drain control clock. This
signal sets the ele c tronic shutter speed .
VRST - Vertica l fi eld reset signa l.
VREF* - Vertical reference signal. It is high
during the active video lines.
*Internal sign a l on the CS7615 - not a chip output.
Vertical Timing Specifications
The CCD array i s read out alternate ly as odd and
even fields with interlaced horizontal lines. Thus
each field has half the total nu mber of horizontal
rows. Table 1 specifi es the progr ammable ve rtical
timings which are defined in Figure 8. The timings
vary based on odd o r even field, 525 or 625 line
CCD, and the manufa c turer.
Horizontal Timing Specifications
Each horizontal row of the CCD is divided into
several regions co rrespon din g to the type of pixel s
present. Different CCDs have different numbers of
pixels in e ach region and the timing si gnals must
take this into account. The d ifferent pixe l types include optic al bla ck pi xe ls (fro nt an d rea r), d um my
pixels, active video pixels, and blank video. The
horizontal t iming for t he CCD is based on maintaining a fi xed 63.5 µs horizont al line time.
8 DS231PP6
Symbol Description Register
VLO # of lines in odd field 33h, 39h
VLE # of lin e s in even field 34h, 39h
VBO End of VREF line # 36h, 39h
XSO Charge transfer line # 38h, 39h
VBE End of VREF line # 35h, 39h
XSE Charge transfer line # 37h, 39h
Table 1. CCD vertical timing specifications
Table 2 speci fies all of the program mable timing
parameters related to horizontal timing signals.
These parame ters are defined in Figure 9.
Figure 9 shows the timings for HREF, HSYNC,
CLAMP, and HENB. Their relationship to different kinds of pixels on each horizontal row output
from the CCD is also shown . The waveforms for
these signals are repeated on every line. The horizontal shi ft regi ster clock s, H1 and H 2, operat e at
the CLKO frequency and are active throughout the
horizontal line period except when HENB is high.
CS7615
Figure 10 shows the t imings for the V1 X through
V4X signals. The specified waveforms repeat on
every horizontal line except during the charge
transfer line. During this line the CCD charge is
read out an d the timing is differen t as shown in Figure 11. In addition signals VH1X and VH3X are
also required during charge read out a s shown in
Figure 1 2.
The overflo w drai n cont rol si gnal is shown in Fig ure 13. The OFDX signal is used to control the
electronic sh utter timin g of the CCD. Sh utter timing for vario us set ti ngs of the shutter control is described in the register section of this document.
Description of Operation
The interna l o perat io n of the CS76 15 ca n b e sepa rated into several distinct blocks. The following
section provides an overvi ew of how these blocks
operate and interact.
Automatic Gain Control
The pixel dat a ente ri ng the CS 7615 from th e CC D
is scaled as det ermined by the au t o m atic gain control loop. By pro perly applyin g gain to the signal,
the full range of the A/D converter is used. The in-
VLO
VREF*
HREF
FLD
DS231PP6 9
1
VBO: end of VREF
XSO: charge transfer line
Not to scale
Figure 8. Vertical Timing Signals -Internal to CS7615
VBE: end of VREF
XSE: charge transfer line
VLE
Hlen
CS7615
HREF
HSYNC
CLAMP
HENB
0
BC
Hsnyr
Hstart
HBPD
Hsynf
Hend
Active Video
CCD
OUTPUT
Optical
black pixels
Figure 9. Timing Diagram for Href, HSYNC, Clamp, and Henb
Inactive
video
ternal analog gain range is 38 dB in steps of
0.078 dB ideal. Adjustments made in these small
steps sh oul d c ause n o not ice able bri gh tne ss chan ge
in the image from frame to frame. In addition to the
internal an alog gain , the con trol loo p will var y the
shutter speed through the OFDX output from 0 to 54 dB as it deems necessary.
The AGC algorithm uses a luma or mosaic histogramming technique in which the brightness of
each pixel is binned into one of seven bins. The
Active video
number of pixels in a bin will produce an error signal that is then used to update the gain. The following paramete rs control the loop d ynamics and are
programma ble to meet th e needs of the us er.
PAL bit: Selects a PAL or NTSC camera system.
AGC Window: Adjusts what portion of the
frame is used for the AGC algorithm.
Luma/Mosaic: Selects whether luma or mosai c
data are used in the histogramming.
10 DS231PP6
HREF
V1X
V2X
V3X
CS7615
V1f
V1r
V2f
V2r
V3f
V3r
V4X
V4f
V4r
Figure 10. Vertical Shift Register Signal Timings
Flickerless Mode: Restricts the shutter speed to
only flickerless values for the given system and
environment. If the scene is too bright, the
AGC loop will select exposure settings shorter
than the flickerless modes.
PAL Environment: Selects PAL or NTSC environment.
Target Value: Adjusts the brightness threshold.
A lower target re sults in the loop settli ng to a
lower gain.
Max Gain: Sets a maximum gain value that will
not be exceeded even if the target brightness
has not been me t.
Slew: Contro ls the rate of decay of the gai n as
the AGC loop slews because of light intensity
variation.
Speed: Cont rols the overall lo op gai n and th us
speed of gain correc t ion.
Min Gain: Sets the m inimum on-chip gain al lowed. Thi s va lue s ho uld be us ed if the sat ura tion voltag e is less than 1. 6V .
Correlated Double Sampling (CDS)
Correlated Do uble Sampling, as applied to CCDbased imaging systems, is a method used to remove
low-frequency noise from the output of a CCD imager leaving only the signal of interest. The CDS is
applied prior to amplification by the VGA.
DS231PP6 11
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