Cirrus Logic CS7410-CQ, CS7410-CM Datasheet

CD/MP3/WMA Audio Controller

CS7410

Features

l Super on-chip Integration for low cost and low count bill of

materials

l 32-Bit RISC Processor performs audio decode and system

management functions

l 16-bit DSP for audio special effects
l 80 Kbytes internal SRAM, and 256 Kbytes internal ROM
l Interfaces to external SDRAM or EDO DRAM (for shock

protection), and to external ROM/FLASH (for custom
program storage)

l CD serial interface with advanced pattern matching and

software error handling

l Integrated DAC functionality
l Simultaneous 4 channels PCM audio output and IEC-958

output.

l Large number of GPIO pins for servo control, key scan, LCD

control, etc.

l Three serial control/status ports
l Sophisticated clock management and low power

consumption

l Supports ISO9660 and multi-session write methods
l Low power 0.18 micron technology
l 100-pin MQFP package
l 100-pin LQFP package

Description

The CS7410 is a true system-on-a-chip for the CD­based digital audio market. With a powerful RISC pro­cessor, one DSP, integrated audio ∆Σ modulator, large
internal SRAM and program ROM, and glueless inter­face to popular CD chip sets, the CS7410 is a complete
single chip low-power programmable audio decoder.
This powerful architecture is easily capable of MP3,
WMA, and other future audio formats. The CS7410’s
flexible architecture and low power consumption make it
an ideal low-cost solution for a wide range of player ap­plications. For portable audio systems, the memory
interface can be used to add DRAM or SRAM for Elec­tronic Shock Protection (ESP). A flexible set of interfaces
are available for end-user I/O such as a keypad and LCD
control for use in mass market CD players, boom boxes,
and shelf-top systems.

ORDERING INFORMATION

CS7410-CM 0° to 70° C 100-pin MQFP
CS7410-CQ 0° to 70° C 100-pin LQFP

RISC-32

Instruction

Cache

CPU

CD

Interface

Control

FIFO

External Interface

2-Wire Debug Interface

3/4 Wire Serial

Programmable I/O

PWM Out

Preliminary Product Information

Cirrus Logic, Inc.

P.O. Box 17847, Austin, Texas 78760
[phone] FAX: [phone]
http://www.cirrus.com

Data

Cache

MAC

DSP-16

Instruction

Cache

CPU / MAC

X,Y Data

memory

Audio

Interface

∆Σ Modulator

PCM Out

IEC-958

System Miscellaneous

PLL

Clock

Control

Timers Get Bits

Register

Bank

80 KB

Internal

SRAM

Memory Controller

ROM/SRAM

Control

Flash

Control

This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.

Copyright  Cirrus Logic, Inc. 2002

Mini

DMA

DRAM

Control

(All Rights Reserved)

256 KB
Internal

ROM

JUL ‘02

DS553PP1

1

TABLE OF CONTENTS

1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5

1.1 AC and DC Parametric Specifications ...............................................................................5

1.1.1 Absolute Maximum Rating .................................................................................... 5

1.1.2 Recommended Operating Conditions ...................................................................5

1.1.3 Electrical Specifications ........................................................................................5

1.1.4 DC Characteristics ................................................................................................ 7

1.1.4.1 SDRAM Interface .................................................................................. 7

1.1.4.2 Serial Interface .................................................................................... 11

1.1.4.3 EDO DRAM interface ..........................................................................12

1.1.4.4 FLASH / ROM Interface ...................................................................... 15

1.1.4.5 Audio Output Interface ........................................................................ 17

1.1.4.6 CD Interface ........................................................................................18

1.1.4.7 Miscellaneous Timings ........................................................................20

2. CS7410 SUMMARY ................................................................................................................ 21

2.1 CS7410 Typical Application ............................................................................................. 21

2.2 CS7410 Block Summaries ..............................................................................................21

2.2.1 RISC-32 ..............................................................................................................21

2.2.2 DSP-16 ................................................................................................................21

2.2.3 System Controls ..................................................................................................21

2.2.4 Memory System ..................................................................................................22

2.2.5 CD Interface ........................................................................................................ 22

2.2.6 Audio Interface ....................................................................................................22

2.2.7 External Interface ................................................................................................ 22

2.2.8 System Functions ................................................................................................22

3. FUNCTIONAL DESCRIPTION ...............................................................................................23

3.1 RISC-32 Processor .......................................................................................................... 23

3.2 DSP-16 Processor ...........................................................................................................23

3.3 Memory Control ...............................................................................................................23

3.4 CD Interface ..................................................................................................................... 23

3.5 System Control Functions ................................................................................................ 23

3.6 Audio Output ....................................................................................................................24

4. PIN DESCRIPTION .................................................................................................................25

CS7410

Contacting Cirrus Logic Support

For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:

http://www.cirrus.com/corporate/contacts/sales.cfm

IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product infor-

mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the infor­mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus
and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only
for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying
for general distribution, advertising or promotional purposes, or for creating any work for resale.

An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma­terial and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT­ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade­marks or service marks of their respective owners.

2 DS553PP1

4.1 Pin Identification .............................................................................................................. 25

4.2 Miscellaneous Pins .......................................................................................................... 30

4.3 Serial Interface Pins ........................................................................................................ 30

4.4 SDRAM / DRAM Interface ............................................................................................... 31

4.5 ROM/NVRAM Interface ................................................................................................... 32

4.6 Digital Audio Output Interface .......................................................................................... 33

4.7 ∆Σ Modulator Interface .................................................................................................... 33

4.8 CD Interface .................................................................................................................... 34

4.9 General Purpose Input/Output (GPIO) ............................................................................ 35

4.10 Power and Ground ........................................................................................................ 36

5. 100-PIN MQFP PACKAGE SPECIFICATIONS (20X14X2.85MM) ....................................... 38

6. 100-PIN LQFP PACKAGE SPECIFICATIONS (14X14X1.4MM) ........................................... 39

LIST OF FIGURES

Figure 1. SDRAM Timing................................................................................................................ 7

Figure 2. SDRAM Load Mode......................................................................................................... 8

Figure 3. SDRAM Burst Write......................................................................................................... 9

Figure 4. SDRAM Burst Read......................................................................................................... 9

Figure 5. SDRAM Refresh ............................................................................................................ 10

Figure 6. Serial Interface Timing Diagram .................................................................................... 11

Figure 7. EDO Page Write Timing Diagram.................................................................................. 13

Figure 8. EDO Page Read Timing Diagram.................................................................................. 13

Figure 9. EDO Refresh Timing Diagram....................................................................................... 14

Figure 10. FLASH/ROM Read ...................................................................................................... 15

Figure 11. FLASH/ROM Write....................................................................................................... 16

Figure 12. Audio Output Timing.................................................................................................... 17

Figure 13. CD Interface Timing..................................................................................................... 18

Figure 14. CD Interface Timing Diagrams..................................................................................... 19

Figure 15. Miscellaneous Timings................................................................................................. 20

Figure 16. CS7410 Application ..................................................................................................... 21

Figure 17. CS7410 Pin Identification............................................................................................. 25

Figure 18. 100-Pin MQFP Package (20x14x2.85mm).................................................................. 38

Figure 19. 100-Pin LQFP Package (14X14X1.4mm).................................................................... 39

CS7410

LIST OF TABLES

Table 1. SDRAM Characterization Data ......................................................................................... 7

Table 2. Serial Interface Characterization Data............................................................................ 11

Table 3. EDO DRAM Characterization Data................................................................................. 12

Table 4. FLASH/ROM Read Characterization Data...................................................................... 15

Table 5. Audio Output Interface Symbols and Characterization Data........................................... 17

Table 6. Pin Type and Direction Legend....................................................................................... 25

Table 7. Pin Assignments ............................................................................................................. 26

Table 8. Miscellaneous Interface Pins .......................................................................................... 30

Table 9. Serial Interface Pins........................................................................................................ 30

Table 10. SDRAM Interface.......................................................................................................... 31

Table 11. EDO DRAM Interface.................................................................................................... 31

Table 12. ROM/NVRAM Interface ................................................................................................. 32

Table 13. Audio Output Interface.................................................................................................. 33

Table 14. ∆Σ Output Interface....................................................................................................... 33

Table 15. CD Interface.................................................................................................................. 34

DS553PP1 3

CS7410

Table 16. Dedicated General Purpose I/O Pins............................................................................35

Table 17. Redefined General Purpose Pins..................................................................................35

Table 18. Power and Ground........................................................................................................36

4 DS553PP1

1. CHARACTERISTICS AND SPECIFICATIONS

1.1 AC AND DC PARAMETRIC SPECIFICATIONS

(AGND, DGND=0V, all voltages with respect to 0V)

1.1.1 Absolute Maximum Rating

Symbol Description Min. Max. Unit

CS7410

VDD
VDD
V

I

I

I

I

O

T

SOL

T

VSOL

T

STOR

T

AMB

P

TOT

IO

CORE

Power Supply Voltage on I/O ring -0.5 4.6 Volts
Power Supply Voltage on core logic and PLL -0.5 2.5 Volts
Digital Input Applied Voltage (power applied) -0.5 5.5 Volts
Digital Input Forced Current -10 10 mA
Digital Output Forced Current -50 50 mA
Lead Soldering Temperature 260
Vapor Phase Soldering Temperature 235
Storage Temperature (no power applied) -40 125
Ambient Temperature (power applied) 0 70

o

C

o

C

o

C

o

C

Power consumption 1 W

CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to
the device. Cirrus Logic recommends that CS7410 devices operate at the settings described in the next ta­ble.

1.1.2 RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

Supply Voltage, IO V
Supply Voltage, core and PLL V
Ambient Temperature (power applied) T

DD
DD

AMB

3.0 3.3 3.6 Volts

1.62 1.8V 1.98 Volts
0 25 70

o

C

1.1.3 Electrical Specifications

(TA = 0 to 70 oC)

Parameter Symbol Conditions Min Typ Max Units

Power Supply

Supply Current, IO I
Supply Current, core and PLL I

DD

DD

DS553PP1 5

Normal Operating 13 mA
Normal Operating 70 mA

Digital Pins

CS7410

Parameter Symbol Conditions Min Typ Max Units

Input Voltage, High V
Input Voltage, Low V
Input Current I
Input Pull up/down resistor R
Output Voltage, High V
Output Voltage, Low V
High-Z-state Leakage I

IN

OZ

IH

IL

I

OH

OL

2.0 Volts

0.8 Volts

V

= V

IN

DD

or V

SS

-1 +1
75

µA

KΩ
@ buffer rating 2.4 Volts
@ buffer rating 0.4 Volts
V

= VSS or V

OUT

DD

-1 +1

µA

6 DS553PP1

1.1.4 DC CHARACTERISTICS

(TA= 25°C; VDD_PLL=VDD_CORE=1.8V±10%, VDD_IO=3.3V±10%)

1.1.4.1 SDRAM Interface

Symbol Description Min Typ Max Unit

t

mper

t

mco

t

mdow

t

mhw

t

msur

t

mhr

DR_CKO Period 22 ns
Output Delay from DR_CKO active edge 19 ns
M_D[15:0] delay from DR_CKO 19 ns
M_D[15:0] valid time after DR_CKO 5 ns
M_D[15:0] setup to DR_CKO 13 ns
M_D[15:0] hold time after DR_CKO 0 ns

Table 1. SDRAM Characterization Data

CS7410

DR_CKO

M_WE_L

M_A
DR_RAS_L
DR_CAS_L

M_D

(write)

M_D

(read)

t

msur

t

mper

t

mco

t

mdow

t

mhr

Figure 1. SDRAM Timing

t

mhw

DS553PP1 7

DR_CKO

DR_RAS_L

DR_CAS_L

M_A

M_D

M_WE_L

CS7410

Figure 2. SDRAM Load Mode

8 DS553PP1

DR_CKO

DR_RAS_L

DR_CAS_L

CS7410

M_A

M_D

M_WE_L

DR_CKO

DR_RAS_L

ADRAS

ADCAS

D0

Figure 3. SDRAM Burst Write

Dn...D1

DR_CAS_L

M_A

M_D

M_WE_L

ADRAS ADCAS

D1 Dn...D2

Figure 4. SDRAM Burst Read

DS553PP1 9

DR_CKO

DR_RAS_L

DR_CAS_L

M_A

M_D

M_WE_L

CS7410

Figure 5. SDRAM Refresh

10 DS553PP1

1.1.4.2 Serial Interface

Symbol Description Min Typ Max Unit

t

clk_per

t

DMs

t

DMh

t

DSs

t

CMs

t

DSh

SER2_CLK

(CPOL=0)

SER2_CLK

(CPOL=1)

Clock period 66 ns
Master-mode data setup 28 ns
Master-mode data hold 28 ns
Slave-mode data setup 15 ns
Master chip select to clock setup 28 ns
Slave mode data hold 0 ns

t

CMs

Table 2. Serial Interface Characterization Data

t

clk_per

CS7410

SER2_DO

(master)

SER2_DI

(slave)

SER2_CS

t

DMs

t

DSs

MSB LSB

t

t

DMh

DSh

Figure 6. Serial Interface Timing Diagram

LSBMSB

DS553PP1 11

1.1.4.3 EDO DRAM interface

Symbol Description Min Typ Max Unit

t

RAS

t

RP

t

RCL

t

CAS

t

CPN

t

CAH

t

ASR

t

RAH

t

ASC

t

AA

t

CAC

t

CSR

t

CHR

t

CRH

t

WDS

t

WDH

t

WS

t

WH

t

ROE

t

OER

t

DCH

RAS low time 72 ns
RAS high pulse time 40 ns
RAS fall to CAS fall 38 ns
CAS low time 30 ns
CAS high time 15 ns
CAS fall to address row 29 ns
Address row to RAS fall 10 ns
RAS fall to address column 18 ns
second address column (burst) to CAS fall 10 ns
Column address to data setup 35 ns
CAS fall to data setup 17 ns
CAS fall to RAS fall 19 ns
RAS fall to CAS rise 18 ns
CAS rise to RAS rise 6 ns
Write data setup to CAS fall 12 ns
Write data hold to CAS fall 29 ns
Write enable setup to CAS fall 13 ns
Write enable hold to CAS fall 20 ns
RAS fall to OE fall -5 5 ns
RAS rise to OE rise -5 5 ns
Read data hold to CAS rise 0 ns

CS7410

Table 3. EDO DRAM Characterization Data

Note:Values shown are for minimum internal clock period (11ns) and all programmed wait states enabled.

12 DS553PP1