Cirrus Logic CS6422-IS, CS6422-CS Datasheet
CS6422
Enhanced Full-Duplex Speakerphone IC
Features
l Single-chip full-duplex hands-free operation
l Optional Tx Noise Guard
l Programmable attenuation during double-talk
l Optional 34 dB microphone preamplifier
l Dual channel AGC’ed volume controls with
mute
l Dual integrated 80 dB IDR codecs
l Speech-trained Network and Acoustic Echo
Cancellers
l Rx and Tx supplementary echo suppression
l Configurable half-duplex training mode
l Powerdown mode
l Microcontroller Interface
DVDDNC1 NC2 NC3 NC4
General Description
Most modern speakerphones use half-duplex operation,
which alternates transmission between the far-end talker
and the speakerphone user. This is done to ensure stability because the acoustic coupling between the
speaker and microphone is much higher in speakerphones than in handsets where the coupling is
mechanically suppressed.
The CS6422 enables full-duplex conversation using
echo cancellation and suppression in a single-chip solution. The CS6422 can easily replace existing half-duplex
speakerphone ICs with a huge increase in conversation
quality.
The CS6422 consists of telephone & audio interfaces,
two codecs and an echo-cancelling DSP.
ORDERING INFORMATION
CS6422-CS 0
CS6422-IS -40
CDB6422 Evaluation Board
AVDD
o
to 70oC 20-pin SOIC
o
to 85oC 20-pin SOIC
9101112
17
NI
(0, 6, 9.5, 12 dB)
Network
Sidetone
(none, -24,
-18, -12 dB)
4
NO
RGain RVol
ADC
NSdt
DAC
8
+
Σ
+
(Mute, -12 to +30 dB)
Network
Echo
Canceller
Pre-emphasis
Filter
Suppression
Microcontroller Interface
76
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
16 1
Rx
Suppression
Pre-emphasis
Filter
Acoustic
Echo
Canceller
Tx
5
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
TVol
(Mute, -12 to +30 dB)
-
Σ
15 2 19
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
DAC
Clock
Acoustic
ASdt
Sidetone
(none, -24,
-18, -12 dB)
+
+
ADC
TGain
(0, 6, 9.5, 12 dB)
Generation
Mic
1 k
Voltage
Refe rence
Ω
34 dB
3
AO
14
CLKI
13
CLKO
20
API
18
APO
JUL ‘01
DS295PP4
1
TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 5
ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5
RECOMMENDED OPERATING CONDITIONS ....................................................................... 5
POWER CONSUMPTION ........................................................................................................ 5
ANALOG CHARACTERISTICS ................................................................................................ 5
ANALOG TRANSMISSION CHARACTERISTICS.................................................................... 6
MICROPHONE AMPLIFIER ..................................................................................................... 6
DIGITAL CHARACTERISTICS ................................................................................................. 6
SWITCHING CHARACTERISTICS .......................................................................................... 7
2. OVERVIEW ............................................................................................................................... 9
3. FUNCTIONAL DESCRIPTION ................................................................................................. 9
3.1 Analog Interface ................................................................................................................. 9
3.1.1 Acoustic Interface ................................................................................................ 10
3.1.2 Network Interface ................................................................................................ 11
3.2 Microcontroller Interface ..................................................................................................11
3.2.1 Description .......................................................................................................... 11
3.2.2 Register Definitions ............................................................................................. 12
3.3 Register 0 ......................................................................................................................... 13
3.3.1 Mic - Microphone Preamplifier Enable .................................................................... 14
3.3.2 HDD - Half-Duplex Disable...................................................................................... 14
3.3.3 GB - Graded Beta.................................................................................................... 14
3.3.4 RVol - Receive Volume Control............................................................................... 14
3.3.5 TSD - Transmit Suppression Disable ...................................................................... 14
3.3.6 ACC - Acoustic Coefficient Control ......................................................................... 15
3.3.7 TSMde - Transmit Suppression Mode..................................................................... 15
3.4 Register 1 ......................................................................................................................... 16
3.4.1 THDet - Transmit Half-Duplex Detection Threshold ................................................ 17
3.4.2 Taps - AEC/NEC Tap Allocation ............................................................................. 17
3.4.3 TVol - Transmit Volume Control .............................................................................. 17
3.4.4 RSD - Receive Suppression Disable....................................................................... 17
3.4.5 NCC - Network Coefficient Control.......................................................................... 17
3.4.6 AuNECD - Auto re-engage NEC Disable ................................................................ 17
3.5 Register 2 ......................................................................................................................... 18
3.5.1 RHDet - Receive Half-Duplex Detection Threshold ................................................ 19
3.5.2 RSThd - Receive Suppression Threshold ............................................................... 19
3.5.3 NseRmp - Noise estimator Ramp rate .................................................................... 19
CS6422
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information
contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any
kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third
parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise)
without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the
printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or
sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in
this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
2
CS6422
3.5.4 HDly - Half-Duplex Holdover Delay......................................................................... 19
3.5.5 HHold - Hold in Half-Duplex on Howl ...................................................................... 19
3.5.6 TDSRmp - Tx Double-talk Suppression Ramp rate ................................................ 19
3.5.7 RDSRmp - Rx Double-talk Suppression Ramp rate ............................................... 20
3.5.8 IdlTx - half-duplex Idle return-to-Transmit ............................................................... 20
3.6 Register 3 ......................................................................................................................... 21
3.6.1 TSAtt - Transmit Suppression Attenuation.............................................................. 22
3.6.2 PCSen- Path Change Sensitivity ............................................................................ 22
3.6.3 TDbtS - Tx Double-talk Suppression attenuation .................................................... 22
3.6.4 RDbtS - Rx Double-talk Suppression attenuation ................................................... 22
3.6.5 TSThd - Transmit Suppression Threshold .............................................................. 22
3.6.6 TSBias - Transmit Suppression Bias ...................................................................... 22
3.7 Register 4 ......................................................................................................................... 23
3.7.1 AErle - AEC Erle threshold...................................................................................... 24
3.7.2 AFNse - AEC Full-duplex Noise threshold .............................................................. 24
3.7.3 NErle - NEC Erle threshold ..................................................................................... 24
3.7.4 NFNse - NEC Full-duplex Noise threshold.............................................................. 24
3.7.5 RGain - Receive Analog Gain ................................................................................. 24
3.7.6 TGain - Transmit Analog Gain ................................................................................ 24
3.8 Register 5 ......................................................................................................................... 25
3.8.1 HwlD - Howl detector Disable ................................................................................. 26
3.8.2 TD - Tone detector Disable ..................................................................................... 26
3.8.3 APCD - Acoustic Path Change detector Disable .................................................... 26
3.8.4 NPCD - Network Path Change detector Disable..................................................... 26
3.8.5 APFD/NPFD - Acoustic Pre-emphasis Filter Disable/Network
Pre-emphasis Filter Disable..................................................................................... 26
3.8.6 AECD - Acoustic Echo Canceller Disable ............................................................... 27
3.8.7 NECD - Network Echo Canceller Disable ............................................................... 27
3.8.8 ASdt - Acoustic Sidetone level ................................................................................ 27
3.8.9 NSdt - Network Sidetone level ................................................................................ 27
3.9 Reset ............................................................................................................................... 28
3.9.1 Cold Reset .......................................................................................................... 28
3.9.2 Warm Reset ........................................................................................................ 28
3.9.3 Reset Timer ........................................................................................................ 28
3.10 Clocking ......................................................................................................................... 28
3.11 Power Supply ................................................................................................................ 29
3.11.1 Power Down Mode ............................................................................................ 29
3.11.2 Noise and Grounding ........................................................................................ 29
4. DESIGN CONSIDERATIONS ................................................................................................. 31
4.1 Algorithmic Considerations .............................................................................................. 31
4.1.1 Full-Duplex Mode ................................................................................................ 31
4.1.1.1 Theory of Operation ........................................................................... 31
4.1.1.2 Adaptive Filter ..................................................................................... 32
4.1.1.2.1 Pre-Emphasis ............................................................................ 32
4.1.1.2.2 Graded Beta .............................................................................. 33
4.1.1.3 Update Control .................................................................................... 33
4.1.1.4 Speech Detection ................................................................................ 33
4.1.2 Half-Duplex Mode ............................................................................................... 34
4.1.2.1 Idle Return to Transmit ....................................................................... 34
4.1.3 AGC .................................................................................................................... 34
4.1.4 Suppression ........................................................................................................ 35
4.1.4.1 Transmit Suppression ......................................................................... 36
4.1.4.2 Receive Suppression .......................................................................... 36
3
4.2 Circuit Design ................................................................................................................... 37
4.2.1 Interface Considerations ..................................................................................... 37
4.2.2 Grounding Considerations .................................................................................. 38
4.2.3 Layout Considerations ........................................................................................ 38
4.3 System Design ................................................................................................................. 38
4.3.1 Gain Structure ..................................................................................................... 38
4.3.2 Testing Issues ..................................................................................................... 39
5. PIN DESCRIPTIONS .............................................................................................................. 41
6. GLOSSARY ............................................................................................................................ 44
7. PACKAGE DIMENSIONS ....................................................................................................... 46
LIST OF FIGURES
Figure 1. CLKI Timing ................................................................................................................... 7
Figure 2. Reset Timing .................................................................................................................. 7
Figure 3. Microcontroller Interface Timing ..................................................................................... 7
Figure 4. Typical Connection Diagram (Microphone Preamplifier Enabled) ................................. 8
Figure 5. Typical Connection Diagram (Microphone Preamplifier Disabled) ................................ 8
Figure 6. Analog Interface ........................................................................................................... 10
Figure 7. Microcontroller Interface .............................................................................................. 12
Figure 8. Suggested Layout ........................................................................................................ 29
Figure 9. Ground Planes ............................................................................................................. 30
Figure 10. Simplified Acoustic Echo Canceller Block Diagram ................................................... 31
Figure 11. How the AGC works (TVol = +30 dB) ........................................................................ 35
CS6422
4.1.4.3 Double-talk Attenuation ....................................................................... 36
4.1.4.4 Noise Guard ........................................................................................ 37
4.2.1.1 Analog Interface .................................................................................. 37
4.2.1.2 Microcontroller Interface ...................................................................... 37
4.3.2.1 ERLE ................................................................................................... 39
4.3.2.2 Convergence Time .............................................................................. 40
4.3.2.3 Half-Duplex Switching ......................................................................... 40
LIST OF TABLES
Table 1. Full scale voltages for each gain stage ........................................................................... 11
Table 2. MCR Control Register Mapping ...................................................................................... 12
Table 3. Register 0 Bit Definitions................................................................................................. 13
Table 4. Register 1 Bit Definitions................................................................................................. 16
Table 5. Register 2 Bit Definitions................................................................................................. 18
Table 6. Register 3 Bit Definitions................................................................................................. 21
Table 7. Register 4 Bit Definitions................................................................................................. 23
Table 8. Register 5 Bit Definitions................................................................................................. 25
4
CS6422
1. CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
DC Supply (AVDD, DVDD) -0.3 6.0 V
Input Current (Except supply pins) I
Input Voltage Analog
Digital
Ambient Operating Temperature T
Storage Temperature T
in
V
ina
V
ind
A
stg
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Units
DC Supply (AVDD, DVDD) 4.5 5.0 5.5 V
Ambient Operating Temperature Commercial
Industrial
T
AOp
-10 +10 mA
-0.3
-0.3
AVD D + 0 . 3
DVDD+0.3
-40 85 °C
-65 150 °C
0
-40
25
25
70
85
V
°C
POWER CONSUMPTION
(TA = 25°C, DVDD = AVDD = 5 V, f
= 20.480 MHz) (Note 1)
XTAL
Parameter Symbol Min Typ Max Units
Power Supply Current, Analog (RST
Power Supply Current, Analog (RST
Power Supply Current, Digital (RST
Power Supply Current, Digital (RST
=0)
=1)
=0)
=1)
P
P
P
P
DA0
DA
DD0
DD
10 20 mA
50 80 mA
1mA
1mA
Notes: 1. AO and NO outputs are not loaded.
ANALOG CHARACTERISTICS (T
= 25°C, DVDD = AVDD = 5 V, f
A
= 20.480 MHz)
XTAL
Parameter Symbol Min Typ Max Units
Input Offset Voltage (APO, NI) 2.12 V
Output Offset Voltage (AO, NO) 2.12 V
Transmit Group Delay (Note 2) 6 ms
Receive Group Delay (Note 2) 6 ms
Input Impedance (APO, NI) Z
Load Impedance (AO, NO) Z
in
load
10 kΩ
1.5 MΩ
Power Supply Rejection (1 kHz) 40 dB
Notes: 2. These parameters are guaranteed by design or by characterization.
5
CS6422
ANALOG TRANSMISSION CHARACTERISTICS (T
= 25°C, DVDD = AVDD = 5 V, f
A
XTAL
20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HDD=TSD=RSD=1, analog inputs and outputs loaded with
resistors and capacitors as shown in the typical connection diagram, Figure 4)
Parameter Symbol Min Typ Max Units
Idle Channel Noise C-Message weighted (0-4 kHz)
(Inputs grounded C-Message weighted (0-4 kHz)
through a capacitor) Psophometrically weighted (0-4 kHz)
Signal-to-Noise Ratio C-Message weighted (0-4 kHz)
(1.0 V
1 kHz sine wave input)
rms,
Total Harmonic Distortion C-Message weighted (0-4 kHz)
(1.0 V
1 kHz sine wave input)
rms,
Programmable Analog Gain RGain/TGain = 00
RGain/TGain = 01
RGain/TGain = 10
RGain/TGain = 11
SNR 73 80 dB
THD 0.030 0.1 %
-80
11
-78
0
6
9.5
12
-73 dBV
dBrnC0
dBm0p
dB
Volume Control Stepsize (TVol/RVol) 3 dB
ADC Full-scale Voltage Input 0.9 1.0 V
DAC Full-scale Voltage Output 1.0 1.2 V
rms
rms
ADC Noise Floor C-Message weighted (0-4 kHz) -83 dBV
DAC Noise Floor, DAC muted C-Message weighted (0-4 kHz) -83 dBV
=
MICROPHONE AMPLIFIER (T
= 25°C, DVDD = AVDD = 5 V, f
A
= 20.480 MHz)
XTAL
Parameter Symbol Min Typ Max Units
Gain (Z
= 50Ω)A
source
mic
34 dB
Signal-to-Noise Ratio C-Message weighted (0-4 kHz) SNRm 70 dB
Input Impedance Z
Input Offset Voltage V
DIGITAL CHARACTERISTICS (T
= 25°C, DVDD = AVDD = 5 V,f
A
inm
offm
XTAL
8kΩ
2.12 V
= 20.480 MHz)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I
Input Capacitance C
IH
IL
leak
IN
DVDD-1.0 V
1.0 V
10 µA
5pF
6
CS6422
ANALOG TRANSMISSION CHARACTERISTICS (T
f
=20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HDD=TSD=RSD=1, analog inputs and outputs loaded with
XTAL
= -40°C to 85oC, DVDD = AVDD = 5 V,
A
resistors and capacitors as shown in the typical connection diagram, Figure 4)
Parameter Symbol Min Typ Max Units
Idle Channel Noise C-Message weighted (0-4 kHz)
(Inputs grounded C-Message weighted (0-4 kHz)
through a capacitor) Psophometrically weighted (0-4 kHz)
Signal-to-Noise Ratio C-Message weighted (0-4 kHz)
(1.0 V
1 kHz sine wave input)
rms,
Total Harmonic Distortion C-Message weighted (0-4 kHz)
(1.0 V
1 kHz sine wave input)
rms,
Programmable Analog Gain RGain/TGain = 00
RGain/TGain = 01
RGain/TGain = 10
RGain/TGain = 11
SNR 72 80 dB
THD 0.030 0.1 %
-80
11
-78
0
6
9.5
12
-72 dBV
dBrnC0
dBm0p
dB
Volume Control Stepsize (TVol/RVol) 3 dB
ADC Full-scale Voltage Input 0.9 1.0 V
DAC Full-scale Voltage Output 1.0 1.2 V
rms
rms
ADC Noise Floor C-Message weighted (0-4 kHz) -83 dBV
DAC Noise Floor, DAC muted C-Message weighted (0-4 kHz) -83 dBV
MICROPHONE AMPLIFIER (T
= 25°C, DVDD = AVDD = 5 V, f
A
= 20.480 MHz)
XTAL
Parameter Symbol Min Typ Max Units
Gain (Z
= 50Ω)A
source
mic
34 dB
Signal-to-Noise Ratio C-Message weighted (0-4 kHz) SNRm 70 dB
Input Impedance Z
Input Offset Voltage V
DIGITAL CHARACTERISTICS (T
= 25°C, DVDD = AVDD = 5 V,f
A
inm
offm
XTAL
8kΩ
2.12 V
= 20.480 MHz)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage V
Low-Level Input Voltage V
Input Leakage Current I
Input Capacitance C
IH
IL
leak
IN
DVDD-1.0 V
1.0 V
10 µA
5pF
7
SWITCHING CHARACTERISTICS
Parameter Symbol Min Typ Max Units
Digital input rise time t
RST
low time
CLKI frequency f
CLKI duty cycle t
CLKI high or low time t
Min DRDY
STROBE high or low time t
DRDY
DATA valid to STROBE rising setup time t
STROBE rising to DATA valid hold time t
STROBE rising to DRDY
Min RST
Max RST
falling to DRDY falling (CLKI = 20.480 MHz)
HLSTROBE
falling to STROBE rising setup time
rising hold time
rising to 4th extra STROBE pulse (cold reset)
rising to 4th extra STROBE pulse(warm reset)
rise
t
RSTL
CLKI
LCLKI
HLCLKI
t
DRDY
t
sDRDY
sDATA
hDATA
t
hDRDY
t
cRST
t
wRST
CS6422
1.0 µs
1.0 µs
20.480 MHz
40 50 60 %
19.5 ns
125 µs
55 ns
30 ns
30 ns
30 ns
30 ns
110 ms
100 ms
RST
STROBE
DRDY
DRDY
STROBE
DATA
t
RSTL
t
sDATA
f
1
CLKI
t
HLCKI
Figure 1. CLKI Timing
Bit15
Bit14 Bit2 Bit1
Figure 2. Reset Timing
t
DRDY
t
sDRDY
t
hDAT A
Bit15
Bit14
t
t
wRST
Bit0
t
cRST
HLCKI
four extra strobe pulses
1234
Bit0DATA
t
hDRDY
t
HLSTROBE
Bit15
Bit14
Figure 3. Microcontroller Interface Timing
8
Network
Line Out
Network
Line In
3300 pF
0.47 µF
+
10 µF
12.1 k
6.04 k
3300 pF
From
Microcontroller
0.1 µF
Ω
Ω
16
15
17
8
7
6
5
DVDD
DGND
4
NO
NI
DATA
STROBE
DRDY
RST
ferrite bead
CS6422
NC1NC2NC3NC4
22pF
AGND
20.480 MHz
AVDD
MB
APO
API
AO
CLKOCLKI
13149101112
22pF
0.1 µF
1
2
19
0.1 µF
18
20
12.1 k
3
3300pF
0.022 µF
0.47 µF
Ω
+
10 µF
+
+5V Analog
F
10
µ
Speaker
Driver
CS6422
Mic Bias
Figure 4. Typical Connection Diagram (Microphone Preamplifier Enabled)
ferrite bead
AVDD
API
APO
MB
AO
CLKOCLKI
13149101112
22pF
0.1 µF
1
2
20
18
19
0.1 µF
12.1 k
3
3300pF
0.47 µF
6.04 k
3300 pF
Ω
+
10 µF
Ω
0.47 µF
10 µF
+
Network
Line Out
Network
Line In
3300 pF
0.47 µF
Microprocessor
10 µF
3300 pF
From
+
6.04 k
0.1 µF
12.1 k
Ω
Ω
16
15
17
8
7
6
5
DVDD
DGND
4
NO
NI
DATA
STROBE
DRDY
RST
AGND
CS6422
NC1NC2NC3NC4
20.480 MHz
22pF
+5V Analog
External Mic
Preamp
Speaker
Driver
Figure 5. Typical Connection Diagram (Microphone Preamplifier Disabled)
9
CS6422
2. OVERVIEW
The CS6422 is a full-duplex speakerphone chip for
use in hands-free communications with telephony
quality audio. Common applications include
speakerphones, inexpensive video-conferencing,
and hands-free cellular phone car kits. The CS6422
requires very few external components and allows
system control through a microcontroller interface.
Hands-free communication through a microphone
and speaker typically results in acoustic feedback
or howling because the loop gain of the system exceeds unity by the time audio amplitudes are adjusted to a reasonable level. The solution to the
howling problem has typically been half-duplex,
where either the transmit or the receive channel is
active, never both at the same time. This prevents
instability, but diminishes the overall communication quality by clipping words and forcing each
talker to speak in turn.
Full-duplex conversation, where both transmit and
receive channels are active simultaneously, is the
conversation quality we enjoy when using handsets. Full-duplex for hands-free communications is
achieved in the CS6422 using a digital signal processing technique called “Echo Cancellation.” The
end result is a more natural conversation than halfduplex, with no awkward breaks and pauses, allowing both parties to speak simultaneously.
Echo Cancellation reduces overall loop gain and
the acoustic coupling between speaker and microphone. This coupling reduction prevents the annoying effect of hearing one’s own delayed speech,
which is worsened when there is delay in the system, such as vocoder delay in digital cellular
phones.
The CS6422 is a complete system implementation
of a Digital Signal Processor with RAM and program ROM, running Echo Cancellation algorithms
developed at Crystal Semiconductor using customer input, integrated with two delta-sigma codecs.
The CS6422 is intended to provide a full-duplex
speakerphone solution with a minimum of design
effort while displacing existing half-duplex speakerphone chips.
3. FUNCTIONAL DESCRIPTION
The CS6422 is divided into four external interface
blocks. The analog interfaces connect the device to
the transmit and receive paths. Control functions
are accessible through the microcontroller interface. Two pins accommodate either a crystal or an
externally applied digital clock signal. Analog and
digital power and ground are provided through four
pins.
3.1 Analog Interface
In a speakerphone application, one input of the
CS6422 connects to the signal from the microphone, called the near-end or transmit input, and
one output connects to the speaker. The output that
leads to the speaker is called the near-end or receive output. Together, the input and output that
connect to the microphone and speaker form the
Acoustic Interface.
The signal received at the near-end input is passed
to the far-end or transmit output after acoustic echo
cancellation. This signal is sent to the telephone
line. The signal from the telephone line is received
at the far-end input, also called the receive input,
and this signal is passed to the receive output after
network echo cancellation. The far-end input and
output form the Network Interface.
The analog interfaces are physically implemented
using delta sigma converters running at an output
word rate of 8 kHz, resulting in a passband from
DC to 4 kHz. Because the inputs are analog to digital converters (ADCs), anti-aliasing and full-scale
input voltage must be kept in mind. The ADCs expect a single-pole RC filter with a corner at 8 kHz,
and they are post-compensated internally to prevent any resulting passband droop. The ADCs also
expect a maximum of 0.9 V
puts (which are biased around 2.12 VDC). A signal
(2.5 Vpp) at their in-
rms
10
Receive Path
CS6422
NI
FAR-END
(0,6,9.5,12 dB)
NO
17
4
RGain
ADC
D
S
P
DAC
DAC
ADC
CS6422
Transmit Path
Figure 6. Analog Interface
of higher amplitude will clip the ADC input and
will result in poor echo canceller performance. See
Section 4., “Design Considerations” for more details.
The outputs are delta-sigma digital to analog converters (DACs) and have similar requirements to
the ADCs. The DACs are pre-compensated to expect a single-pole RC filter with a corner frequency
at 4 kHz. The full scale voltage output from a DAC
is 1.1 V
(3.1 Vpp) maximum, 1 V
rms
typical, bi-
rms
ased around 2.12 VDC.
3.1.1 Acoustic Interface
The pins API (pin 20), APO (pin 18), AO (pin 3),
and MB (pin 19) form the Acoustic Interface. A
block diagram of the Acoustic Interface is shown in
Figure 6.
API and APO are, respectively, the input and output of the built-in microphone pre-amplifier. The
pre-amplifier is an inverting amplifier with a fixed
AO
3
NEAR-END
API
TGain
(0,6,9.5,12 dB)
Mic
Ω
1k
Voltage
Reference
34 dB
20
1918
MBAPO
gain of 34 dB biased around an input offset voltage
of 2.12 V. APO is the output of the pre-amplifier
after a 1 kΩ (typical) resistor. The circuitry connected to the amplifier input must present low
source impedance (<100 Ω) to the API pin or the
gain will be reduced. When using the internal mic
preamp, a 0.022 µF capacitor should be placed between APO and ground to provide the anti-aliasing
filter required by the ADC, as shown in Figure 4.
The pre-amplifier may be bypassed by clearing the
‘Mic’ bit (Register 0, bit 15) using the Microcontroller Interface (see Section 3.2, “Microcontroller Interface”). If the internal mic preamp is not used, a
0.022 µF capacitor should be tied between API and
ground, and APO should be driven directly. In this
case, the signal into APO must be low-pass filtered
by a single-pole RC filter with a corner frequency at
8 kHz (see Figure 5).
Following the pre-amplifier is a programmable analog gain stage, called TGain, which is controlled
11
CS6422
through the Microcontroller Interface. This gain
stage allows gains of 0 dB, 6 dB, 9.5 dB, and 12 dB
to be added prior to the ADC input. The default
gain stage setting is 0 dB.
The signal at APO should not exceed 2.5 Vpp at the
0 dB gain stage setting. If a different gain setting is
used, then the full-scale signal at APO must also
change. Table 1 shows full-scale voltages as measured at APO for the given programmable gain:
Gain Setting Full-scale Voltage
0 dB 2.5 V
6 dB 1.25 V
9.5 dB 0.84 V
12 dB 0.63 V
Table 1. Full scale voltages for each gain stage
pp
pp
pp
pp
MB serves to provide decoupling for the internal
voltage reference, and must have a 0.1 µF and a
10 µF capacitor to ground for bypass. Noise on MB
will strongly influence the overall analog performance of the CS6422.
The acoustic output, AO, should connect to a single-pole low-pass RC network with a corner frequency of 4 kHz, which will filter out-of-band
components. The full-scale voltage swing at AO is
3.1 V
maximum, 1 V
pp
typical. AO is capable of
rms
driving a load of 10 kΩ or more.
3.1.2 Network Interface
The pins NI (pin 17) and NO (pin 4) form the Network Interface. The details of the Network Interface are shown in Figure 6.
NI is the input from the telephone network into the
CS6422. The signal into NI must be low pass filtered by a single-pole RC filter with a corner frequency of 8 kHz.
RGain, a programmable analog gain stage accessible through the Microcontroller Interface, amplifies signals received at NI. This gain stage allows a
gain of 0 dB, 6 dB, 9.5 dB, or 12 dB to be added
prior to the ADC input. The default gain stage setting for the network side is 0 dB.
The signal at NI should not exceed 2.5 V
at the
pp
0 dB gain stage setting. If another gain setting is selected, then the full-scale signal at NI will change.
Table 1 shows full-scale voltages as measured at NI
for the given programmable gain.
The output to the telephone network side, NO,
should connect to a single pole RC network with a
corner frequency at 4 kHz, which will filter out-ofband components. The maximum swing NO is capable of producing is 3.1 V
maximum, 1 V
pp
rms
typical. NO is capable of driving a load of 10 kΩ or
more.
3.2 Microcontroller Interface
The registers and control functions of the CS6422
are accessible through the Microcontroller Interface, which consists of three pins: DATA (pin 8),
STROBE (pin 7), and DRDY (pin 6). These inputs
can connect to the outputs of a microcontroller to
allow write-only access to the 16-bit Microcontroller Control Register (MCR).
3.2.1 Description
The Microcontroller Interface is implemented by a
serial shift register that is clocked by STROBE and
gated by DRDY. The microcontroller begins the
transaction by setting DRDY low while STROBE
is low. The most significant bit (MSB), Bit 15, of
the 16-bit data word should be presented to the
DATA pin and then STROBE should be brought
high to shift the data bit into the CS6422. STROBE
should be brought low again so it is ready to shift
the next bit into the shift register. The next data bit
should then be presented to the DATA pin ready to
be latched by the rising edge of STROBE. This procedure repeats for all sixteen bits as shown in Figure 7. After the last bit (Bit 0) has been shifted in,
DRDY should be brought high to indicate the conclusion of the transfer, and four or more extra
12
CS6422
STROBE pulses must be applied to latch the data
into the CS6422.
Since the MCR is a shift register, the STROBE can
be run arbitrarily slowly with a duty cycle limited
only by the minimum high and low time specified
in “Switching Characteristics”. The Microcontrol-
ler Interface is polled at 125 µs intervals, so register writes must be spaced at least 125 µs apart or
the register contents may be overwritten.
STROBE
Bit15
Bit14 Bit13 Bit12
DRDY
Bit11 Bit10 Bit9 Bit8
Bit7 Bit6
3.2.2 Register Definitions
The six control registers accessible through the
MCR are described in detail in the following tables.
These registers are addressed by bits b3-0 of the
MCR. Bit ‘b0’ must always be ‘0’. Table 2 shows
the register map with the default settings. Tables 3
through 8 show the control registers in more detail.
The Register Map at the top of each register description shows the names of all the bits, with their
reset values below the bitfield name. The reset value can also be found in the Word column of the bitfield summary as indicated by an ‘*’.
four extra strobe pulses
Bit5 Bit4 Bit3
Bit2
Bit1
12
Bit0DATA
3
4
Figure 7. Microcontroller Interface
# b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3-0
0Mic1HDD
0
1 THDet
00
2 RHDet
00
3TSAtt00PCSen
4AErle00AFNse
5HwlD0TD0APCD0NPCD0APFD0NPFD0AECD0NECD
GB
10
Tap s
10
RSThd
00
0
00
RVol
0100
TVol
1010
NseRmp
00
TDbtS
000
NErle
00
Table 2. MCR Control Register Mapping
HDly
00
RDbtS
00
NFNse
00
TSD
0
RSD
0
HHold0TDSRmp0RDSRmp0IdlTx
TSThd
RGain
ASdt
0
00
00
00
ACC
00
NCC
00
TSMde00000
AuNECD00010
0
TSBias
00
TGain
00
NSdt
00
0100
0110
1000
1010
13
CS6422
3.3 Register 0
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
MicHDD GB RVol TSD ACC TSMde0000
1 0 10 0100 0 00 0
A4 00
Bits Name Function Word Operation
15 Mic Microphone preamplifier enable 0
1*
14 HDD Half-Duplex Disable 0*
1
13-12 GB Graded Beta 00
01
10*
11
11-8 RVol Rx Volume control 0000
0001
---
0100*
---
1010
1011
--1101
1110
1111
7 TSD Tx Suppression Disable 0*
1
6-5 ACC AEC Coefficient Control 00*
01
10
11
4 TSMde Tx Suppression Mode 0*
1
disable mic preamp
enable mic preamp
enable half-duplex
disable half-duplex
0.00 dB/ms
0.75 dB/ms
0.38 dB/ms
0.19 dB/ms
+30 dB
+27 dB
---
+18 dB
---
+0 dB
-3 dB
---
-9 dB
-12 dB
mute
enable Tx suppression
disable Tx suppression
Normal
Clear
Freeze
reserved
enable noise guard
disable noise guard
14
* Denotes reset value
Table 3. Register 0 Bit Definitions
3.3.1 MIC - MICROPHONE PREAMPLIFIER ENABLE
The microphone preamplifier described in Section 3.1.1, “Acoustic Interface” is enabled by default,
but may be disabled by setting Mic to ‘0’. Refer to Section 3.1.1, “Acoustic Interface” for more details
on using the Microphone Preamplifier.
3.3.2 HDD - HALF-DUPLEX DISABLE
In normal operation, the CS6422 will be in a half-duplex mode if the echo canceller is not providing
enough loop gain reduction to prevent howling. This half-duplex mode is active at power-up while the
adaptive filter begins to train. Half-duplex mode prevents howling and also masks the convergence
process.
In some cases, such as when measuring convergence speed (see Section 4.3.2, “Testing Issues”),
the half-duplex mode is undesirable. By default, the half-duplex mode is enabled.
3.3.3 GB - GRADED BETA
The room-size adjustment scheme called “graded beta,” provided for the acoustic echo canceller in
the CS6422, is controlled by GB. The network echo canceller does not support graded beta.
Graded beta is an architectural enhancement to the CS6422 which takes advantage of the fact that
acoustic echoes tend to decay exponentially with time. The CS6422 can increase the beta, or update
gain, for the coefficients of the adaptive filter which occur earlier in time and decrease it for those that
occur later in time, which increases convergence speed while maintaining stability. In order to make
this improvement, there is an implicit assumption that the decay rate of the echo is known. The graded
beta control allows the system designer to adjust this. For very acoustically live rooms, use either no
decay (00) or slight decay (11). Cars and acoustically dead rooms can benefit from the most rapid decay
(01).
CS6422
3.3.4 RVOL - RECEIVE VOLUME CONTROL
Volume in the receive path is set by RVol. The volume control in the receive direction is implemented
by a peak-limiting automatic gain control (AGC) and digital attenuation at the near-end output DAC.
The AGC is discussed in detail in Section 4., “Design Considerations”. See Section 4.1.3, “AGC”for a
full explanation of how it functions.
When the reference level is set to +0 dB, the AGC is disabled. Volume control is implemented by digital attenuation in 3 dB steps from this point on down. The maximum gain is +30 dB and the minimum
is -12 dB. The lowest gain setting (1111) mutes the receive path.
The default setting for RVol is +18 dB.
3.3.5 TSD - TRANSMIT SUPPRESSION DISABLE
The Transmit Supplementary Echo Suppression function is a non-linear echo control mechanism.
Transmit Suppression introduces TSAtt (see Register 3) of attenuation into the transmit path when it
is engaged. When TSMde = ‘1’, the transmit suppressor engages when there is speech detected in
the receive path and no near-end speech is present. When TSMde = ‘0’, the default case, the transmit
suppressor engages when there is no near-end speech present. When near-end speech is present,
the suppression attenuation is removed. By default, the transmit suppression function is enabled.
15
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