l Single-chip f ull-duplex hands-free operation
l Optional Tx Noise Guard
l Programmable att enuation during do uble-talk
l Optional 34 dB microphone preamplifier
l Dual channel AGC’ed volume controls wi th
mute
l Dual integrated 80 dB IDR codecs
l Speech-trained Network and Acoustic Echo
Cancellers
l Rx and Tx supplementary echo suppression
l Configurable half-duplex training mode
l Powerdown mode
l Microcontroller Interface
DVDDNC1NC2NC3NC4
161
Rx
Suppression
TVol
(Mute, -12 to +30 dB)
17
NI
(0, 6, 9.5, 12 dB)
Network
Sidetone
(none, -24,
-18, -12 dB)
4
NO
9101112
RGainRVol
ADC
NSdt
DAC
+
Σ
+
(Mute, -12 to +30 dB)
Network
Echo
Canceller
Pre-emphasis
Filter
Suppression
Microcontroller Interface
Tx
General Description
Most modern speakerphones use half-duplex operation,
which alternates transmission between the far-end talker
and the speakerphone use r. This is done to ens ure stability because the acoustic coupling between the
speaker and microphone is much higher in speakerphones than in handsets where the coupling is
mechanically suppressed.
The CS6422 enables full-duplex conversation using
echo cancellation and suppression in a single-chip solution. The CS6422 can easily replace existing half-duplex
speakerphone ICs with a huge increas e in co nv er sa tio n
quality.
The CS6422 consists of tel ephone & audio interfaces,
two codecs and an echo-cancelling DSP.
ORDERING INFORMATION
CS6422-CS20-pin SOIC
CDB6422Evaluation Board
AVDD
3
Pre-emphasis
Filter
Acoustic
Echo
Canceller
-
+
+
Σ
DAC
ASdt
ADC
Acoustic
Sidetone
(none, -24,
-18, -12 dB)
TGain
(0, 6, 9.5, 12 dB )
Voltage
Reference
Clock
Generation
Mic
34 dB
Ω
1 k
14
13
20
18
AO
CLKI
CLKO
API
APO
8
DATA STROBE
76
DRDY
Preliminary Product Information
Cirrus Logic, Inc.
Crystal Semiconductor Products Division
WARNING: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
ParameterSymbolMinTypMaxUnits
DC Supply (AVDD, DVDD)4.55.05.5V
Ambient Operating TemperatureT
AOp
-10+10mA
-0.3
-0.3
AVDD+0.3
DVDD+0.3
V
-4085°C
-65150°C
02570°C
POWER CONSUMPTION
(TA = 25°C, DVDD = AVDD = 5 V, f
= 20.480 MHz) (Note 1)
XTAL
ParameterSymbolMinTypMaxUnits
Power Supply Current, Analog (RST
Power Supply Current, Analog (RST
Power Supply Current, Digital (RST
Power Supply Current, Digital (RST
=0)
=1)
=0)
=1)
P
P
P
P
DA0
DA
DD0
DD
1020mA
5060mA
1mA
1mA
Notes: 1. AO and NO outputs are not loaded.
ANALOG CHARACTERISTICS (T
= 25°C, DVDD = AVDD = 5 V, f
A
= 20.480 MHz)
XTAL
ParameterSymbolMinTypMaxUnits
Input Offset Voltage (APO, NI)2.12V
Output Offset Voltage (AO, NO)2.12V
Transmit Group Delay(Note 2)6ms
Receive Group Delay(Note 2)6ms
Input Impedance (APO, NI)Z
Load Impedance (AO, NO)Z
in
load
10kΩ
1.5M
Power Supply Rejection (1 kHz)40dB
Notes: 2. These parameters are guaranteed by design or by characterization.
Ω
4DS295PP1
CS6422
ANALOG TRANSMISSION CHARACTERISTICS (T
= 25°C, DVDD = AVDD = 5 V, f
A
XTAL
20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HDD=TSD=RSD=1, analog inputs and outputs loaded with
resistors and capacitors as shown in the typical connection diagram, Figure 1)
ParameterSymbolMinTypMaxUnits
Idle Channel NoiseC-Message weighted (0-4 kHz)
(Inputs groundedC-Message weighted (0-4 kHz)
through a capacitor)Psophometrically weighted (0-4 kHz)
Signal-to-Noise RatioC-Message weighted (0-4 kHz)
(1.0 V
1 kHz sine wave input)
rms,
Total Harmonic DistortionC-Message weighted (0-4 kHz)
(1.0 V
1 kHz sine wave input)
rms,
Programmable Analog GainRGain/TGain = 00
RGain/TGain = 01
RGain/TGain = 10
RGain/TGain = 11
SNR7580dB
THD0.0300.1%
-80
11
-78
0
6
9.5
12
-75dBV
dBrnC0
dBm0p
dB
Volume Control Stepsize (TVol/RVol)3dB
ADC Full-scale Voltage Input0.91.0V
DAC Full-scale Voltage Output1.01.1V
The CS6422 is a full-duplex speakerphone chip for
use in hands-free communications with telephony
quality audio. Common applications include
speakerphones, inexpensive video-conferencing,
and hands-free cellular phone car kits. The CS6422
requires very few external components and allows
system control through a microcontroller interface.
Hands-free communication through a microphone
and speaker typically results in acoustic feedback
or howling because the loop gain of the system exceeds unity by the time audio amplitudes are adjusted to a reasonable level. The solution to the
howling problem has typically been half-duplex,
where either the transmit or the receive channel is
active, never both at the same time. This prevents
instability, but diminishes the overall communication quality by clipping words and forcing each
talker to speak in turn.
Full-duplex conversation, where both transmit and
receive channels are active simultaneously, is the
conversation quality we enjoy when using handsets. Full-duplex for hands-free communications is
achieved in the CS6422 using a digital signal pro-
cessing technique called “Echo Cancellation.” The
end result is a more natural conversation than halfduplex, with no awkward breaks and pauses, allowing both parties to speak simultaneously.
Echo Cancellation reduces overall loop gain and
the acoustic coupling between speaker and microphone. This coupling reduction prevents the annoying effect of hearing one’s own delayed speech,
which is worsened when there is delay in the system, such as vocoder delay in digital cellular
phones.
The CS6422 is a complete system implementation
of a Digital Signal Processor with RAM and program ROM, running Echo Cancellation algorithms
developed at Crystal Semiconductor using customer input, integrated with two delta-sigma codecs.
The CS6422 is intended to provide a full-duplex
speakerphone solution with a minimum of design
effort while displacing existing half-duplex speakerphone chips.
FUNCTIONAL DESCRIPTION
The CS6422 is divided into four external interface
blocks. The analog interfaces connect the device to
the transmit and receive paths. Control functions
are accessible through the microcontroller interface. Two pins accommodate either a crysta l or an
externally applied digital clock signal. Analog and
digital power and ground are provided through four
pins.
Analog Interface
In a speakerphone application, one input of the
CS6422 connects to the signal from the microphone, called the near-end or transmit input, and
one output connects to the speaker. The output that
leads to the speaker is called the near-end or receive output. Together, the input and output that
connect to the microphone and speaker form the
Acoustic Interface.
The signal received at the near-e nd input is pa ssed
to the far-end or transmit output after acoustic echo
cancellation. This signal is sent to the telephone
line. The signal from the telephone line is received
at the far-end input, also called the receive input,
and this signal is passed to the receive output after
network echo cancellation. The far-end input and
output form the Network Interface.
The analog interfaces are physically i mplemented
using delta sigma converters running at an output
word rate of 8 kHz, resulting in a passband from
DC to 4 kHz. Because the inputs are analog to digital converters (ADCs), anti-aliasing and full-scale
input voltage must be kept in mind. The ADCs expect a single-pole RC filter with a corner at 8 kHz,
and they are post-compensated internally to prevent any resulting passband droop. The ADCs also
expect a maximum of 0.9 V
puts (which are biased around 2.12 VDC). A signal
(2.5 Vpp) at their in-
rms
8DS295PP1
Receive Path
CS6422
NI
FAR-END
(0,6,9.5,12 dB)
NO
17
4
RGain
ADC
D
S
P
DAC
DAC
ADC
CS6422
Transmit Path
Figure 3. Analog Interface
of higher amplitude will clip the ADC input and
will result in poor echo canceller performance. See
the Design Considerati ons section for more details.
The outputs are delta-sigma digital to analog converters (DACs) and have similar requirements to
the ADCs. The DACs are pre-compensated to expect a single-pole RC filter with a corner frequency
at 4 kHz. The full scale voltage output from a DAC
is 1.1 V
(3.1 Vpp) maximum, 1 V
rms
typical, bi-
rms
ased around 2.12 VDC.
Acoustic Interface
The pins API (pin 20), APO (pin 18), AO (pin 3),
and MB (pin 19) form the Acoustic Interface. A
block diagram of the Acoustic Interface is shown in
Figure 3.
API and APO are, respectively, the input and output of the built-in microphone pre-amplifier. The
pre-amplifier is an inverting amplifier with a fixed
gain of 34 dB biased around an input offset voltage
of 2.12 V. APO is the output of the pre-amplifier
AO
3
NEAR-END
API
TGain
(0,6,9.5,12 dB)
Mic
1k
Ω
Voltage
Reference
34 dB
20
1918
MBAPO
after a 1 kΩ (typical) resistor. The circuitry connected to the amplifier input must present low
source impedance (<100Ω) to the API pin or the
gain will be reduced. When using the internal mic
preamp, a 0.022 µF capacitor should be placed between APO and ground to provide the anti-aliasing
filter required by the ADC, as shown in Figure 1.
The pre-amplifier may be bypassed by clearing the
‘Mic’ bit (Register 0, bit 15) using th e Microcontroller Interface (see Microcontroller Interface section).
If the intern al mic pream p is no t used, a 0.022 µF capacitor should be tied between API and ground, and
APO should be driven directly. In this case, the signal into APO must be low-pass filtered by a singlepole RC filter with a corner frequency at 8 kHz (see
Figure 2).
Following the pre-amplifier is a programmable analog gain stage, called TGain, which is controlled
through the Microcontroller Interface. This gain
stage allows gains of 0 dB, 6 dB, 9.5 dB, and 12 dB
DS295PP19
CS6422
to be added prior to the ADC input. The default
gain stage setting is 0 dB.
The signal at APO should not exceed 2.5 Vpp at the
0 dB gain stage setting. If a different gain setting is
used, then the full-scale signal at APO must al so
change. Table 1 shows full-scale voltages as measured at APO for the given programmable gain:
Gain SettingFull-scale Voltage
0 dB
6 dB
9.5 dB
12 dB
Table 1. Full scale voltages for each gain stage.
2.5 V
1.25 V
0.84 V
0.63 V
pp
pp
pp
pp
MB serves to provide decoupling for the internal
voltage reference, and must have a 0.1 µF and a 10
µF capacitor to ground for bypass. Noise on MB
will strongly influence the overall analog performance of the CS6422.
The acoustic output, AO, should connect to a single-pole low-pass RC network with a corner frequency of 4 kHz, which will filter out-of-band
components. The full-scale voltage swing at AO is
3.1 Vpp maximum, 1 V
typical. AO is capable of
rms
driving a load of 10 kΩ or more.
Network Interface
The pins NI (pin 17) and NO (pin 4) form the Network Interface. The details of the Network Interface are shown in Figure 3.
NI is the input from the telephone network into the
CS6422. The signal into NI must be low pass filtered by a single-pole RC filter with a corner frequency of 8 kHz.
RGain, a programmable analog gain stage accessible through the Microcontroller Interface, amplifies signals received at NI. This gain st age allows a
gain of 0 dB, 6 dB, 9.5 dB, or 12 dB to be added pri-
or to the ADC input. The default gain stage setting
for the network side is 0 dB.
The signal at NI should not exceed 2.5 Vpp at the
0 dB gain stage setting. If another gain setting is selected, then the full-scale signal at NI will change.
Table 1 shows full-scale voltages as measured at NI
for the given programmable gain.
The output to the telephone network side, NO,
should connect to a single pole RC network with a
corner frequency at 4 kHz, which will filter out-ofband components. The maximum swing NO is capable of producing is 3.1 Vpp maximum, 1 V
rms
typical. NO is capable of driving a load of 10 kΩ or
more.
Microcontroller Interface
The registers and control functions of the CS6422
are accessible through the Microcontroller Interface, which consists of three pins: DATA (pin 8),
STROBE (pin 7), and DRDY (pin 6). These inputs
can connect to the outputs of a microcontroller to
allow write-only access to the 16-bit Microcontroller Control Register (MCR).
Description
The Microcontroller Interface is implemented by a
serial shift register that is clocked by STROBE and
gated by DRDY. The microcontroller begins the
transaction by setting DRDY low while STROBE
is low. The most significant bit (MSB), Bit 15, of
the 16-bit data word should be presented to the
DATA pin and then STROBE should be brought
high to shift the data bit into the CS6422. STROBE
should be brought low again so it is ready to shift
the next bit into the shift register. The next data bit
should then be presented to the DATA pin ready to
be latched by the rising edge of STROBE. This procedure repeats for all sixteen bits as shown in Figure 4. After the last bit (Bit 0) has been shifted in,
DRDY should be brought high to indicate the conclusion of the transfer, and four or more extra
10DS295PP1
CS6422
STROBE pulses must be applied to latch the
data into the CS6422.
Since the MCR is a shift register, the STROBE can
be run arbitrarily slowly with a duty cycle limited
only by the minimum high and low time specified
in the Switching Characterstics table. The Micro-
controller Interface is polled at 125 µs intervals,
so register writes must be spaced at least 125 µs
apart or the register contents may be overwritten.
STROBE
Register Definitions
The six control registers accessible through the
MCR are described in detail in the following tables.
These registers are addressed by bits b3-0 of the
MCR. Bit ‘b0’ must always be ‘0’. Table 2 shows
the register map with the default settings. Tables 3
through 8 show the control registers in more detail.
The Register Map at the top of each register description shows the names of all th e bit s, with th eir
reset values below the bitfield name. The reset value can also be found in the Word column of the bit-
field summary as indicated by an ‘*’.
four extr a strobe pulses
12
3
4
Bit15
Bit14 Bit13 Bit12
DRDY
#b15b14b13b12b11b10b9b8b7b6b5b4b3-0
Mic1HDD
0
1
RHDet
2
3
4
HwlD0TD0APCD0NPCD0APFD0NPFD0AECD0NECD
5
0
THDet
00
00
TSAtt
00
AErle
00
GB
10
Taps
10
RSThd
00
PCSen
0
AFNse
00
Bit11 Bit10 Bit9 Bit8
Figure 4. Microcontroller Interface
NseRmp
00
TDbtS
000
NErle
00
Table 2. MCR Control Register Mapping
RVol
0100
TVol
1010
Bit7 Bit6
HDly
00
RDbtS
00
NFNse
00
Bit5 Bit4 Bit3
TSD
RSD
HHold0TDSRmp0RDSRmp0IdlTx
0
0
0
TSThd
RGain
00
00
ASdt
00
Bit2
Bit1
ACC
00
NCC
00
Bit0DATA
TSMde
AuNECD
TSBias
00
TGain
00
NSdt
00
0
0
0
0000
0010
0100
0110
1000
1010
DS295PP111
CS6422
Register 0
b15b14b13b12b11b10b9b8b7b6b5b4b3b2b1b0
MicHDDGBRVolTSDACCTSMde
101001000000
A4 0 0
BitsNameFunctionWordOperation
15MicMicrophone preamplifier enable
14HDDHalf-Duplex Disable
13-12GBGraded Beta
11-8RVolRx Volume control
7TSDTx Suppression Disable
6-5ACCAEC Coefficient Contro l
4TSMdeTx Suppression Mode
0
1*
0*
1
00
01
10*
11
0000
0001
---
0100*
---
1010
1011
--1101
1110
1111
0*
1
00*
01
10
11
0*
1
0000
disable mic preamp
enable mic preamp
enable half-duplex
disable half-duplex
0.00 dB/ms
0.75 dB/ms
0.38 dB/ms
0.19 dB/ms
+30 dB
+27 dB
---
+18 dB
---
+0 dB
-3 dB
---
-9 dB
-12 dB
mute
enable Tx suppression
disable Tx suppression
Normal
Clear
Freeze
reserved
enable noise guard
disable noise guard
* Denotes reset value
Table 3. Register 0 Bit Definitions
Mic - Microphone Preamplifier Enable
The microphone preamplifier described in the
Acoustic Interface section is enabled by default, but
may be disabled by setting Mic to ‘0’. Refer to the
Acoustic Interface section for more details on using
the Microphone Preamplifier.
enough loop gain reduction to prevent howling.
This half-duplex mode is active at power-up while
the adaptive filter begins to train. Half-duplex
mode prevents howling and also masks the convergence process.
In some cases, such as when measuring convergence speed (see Testing Issues), the half-duplex
HDD - Half-Duplex Disable
In normal operation, the CS6422 will be in a half-
mode is undesirable. By default, the half-duplex
mode is enabled.
duplex mode if the echo canceller is not providing
12DS295PP1
CS6422
GB - Graded Beta
The room-size adjustment scheme called “graded
beta,” provided for the acoustic echo canceller in the
CS6422, is controlled by GB. The network echo
canceller does not support graded beta.
Graded beta is an architectural enhancement to the
CS6422 which takes advantage of the fact that
acoustic echoes tend to decay exponentially with
time. The CS6422 can increase the beta, or update
gain, for the coefficients of the adaptive filter
which occur earlier in time and decrease it for thos e
that occur later in time, which increases convergence speed while maintaining stability. In order to
make this improvement, there is an implicit assumption that the decay rate of the echo is known. The
graded beta control allows the system designer to adjust this. For very acoustically live rooms, use either
no decay (00) or slight decay (11). Cars and acoustically dead rooms can benefit from the most rapid decay (01).
RVol - Receive Volume Control
Volume in the receive path is set by RVol. The volume control in the receive direction is implemented
by a peak-limiting automatic gain control (AGC)
and digital attenuation at the near-end output DAC.
The AGC is discussed in detail in the Design Con-siderations section. See the sub-section on AGC
for a full explanation of how it functions.
When the reference level is set to +0 dB, the AGC
is disabled. Volume control is implemented by digital attenuation in 3 dB steps from this point on
down. The maximum gain is +30 dB and the minimum is -12 dB. The lowest gain setting (1111)
mutes the receive path.
The default setting for RVol is +18 dB.
TSD - Transmit Suppression Disable
The Transmit Supplementary Echo Suppression
function is a non-linear echo control mechanism.
Transmit Suppression introduces TSAtt (see Regis-
ter 3) of attenuation into the transmit path when it
is engaged. When TSMde = ‘1’, the transmit suppressor engages when there is spee ch detected in
the receive path and no near-end speech is present.
When TSMde = ‘0’, the default case, the transmit
suppressor engages when there is no near-end
speech present. When near-end speech is present,
the suppression attenuation is removed. By default,
the transmit suppression function is enabled.
ACC - Acoustic Coefficient Control
The coefficients of the AEC adaptive filters in the
CS6422 are controlled by ACC. The default position (00) yields normal operation, which means the
coefficients are free to adjust themselves to the
echo path in order to cancel echo. When set to the
clear position (01), the adaptive f ilter coefficients
are all held at zero, so the echo canc eller is effectively disabled. Note that unless the half-duplex
mode is disabled, this will force the CS6422 into
half-duplex mode. The freeze position (10) causes
the coefficients to retain their current values and
not change.
TSMde - Transmit Suppression Mode
TSMde enables the Noise Guard feature of the
CS6422. Noise Guard is a noise squelch feature
that operates in the transmit path (from the nearend microphone to the far-end speaker). In traditional hands-free systems where the near-end talker
is located in a noisy environment, the near-end system will remain in transmit mode and send that
noise to the far-end listener. This creates a real
problem if the listener is using a traditional half-duplex speakerphone because the far-end phone will
stay in receive mode, thus preventing the far-end
talker from being heard. Noise Guard eliminates
this problem by squelching the transmit channel at
the near-end unless near-end speech is detected,
permitting the far-end speakerphone to switch normally during the conversation.
DS295PP113
Noise Guard is also useful in cellular hands-free car
applications because it prevents car noise from
reaching the far-end while the near-end talker is silent.
Noise Guard is usually disabled when “half-duplex
Idle return-to- Transmi t” is ena bled. See t he Register 2 description for more information. Noise
Guard is enabled by default.
CS6422
14DS295PP1
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