Cirrus Logic CS6420-CS, CS6420 Datasheet

Full-Duplex Speakerphone Chip

CS6420

Features

Single-chip full-duplex hands-free operation

Automatic gain control

Optional 34 dB microphone preamplifier

Integrated mute and volume control

Integrated 80 dB IDR dual codec

Speech-trained Network and Acoustic Echo Cancellers

Powerdown mode

Microcontroller Interface

DGND

NC4 NC3 NC2 NC1 AGND

General Description

Most modern speakerphones use half-duplex ope ration, which switches transmission between the far-end talker and the speakerphone user. This is done because the acoustic coupling between the speaker and microphone is much higher in speakerphones than in handsets where the coupling is mechanicall y suppressed.

The CS6420 enables full-d uplex conversat ion with a single-chip solution. The CS6420 can easily replace existing half-duplex speakerphone ICs with a huge increase in conversation quality.

The CS6420 consists of telephone & audio interfaces, two codecs and an echo-cancelling DSP.

ORDERING INFORMATION

CS6420-CS 20-pin SOIC CDB6420 Evaluation Board

AVDD

ADC

0,6,9.5,12dB

Pre-Emphasis Network

DAC

Mute/Volume

DVDD

Control

Filter

High Pass

Echo CancellerFilter

Half Duplex

Microcontroller Interface

DA TA STROBE DRDY

Preliminary Product Information

Cirrus Logic, Inc. Crystal Semiconductor Products Division

P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com

RxAGC

Acoustic Pre-Emphasis

TxAGC

Suppression

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Half Duplex

Suppression

Hgih Pass

RST

(All Rights Reserv ed)

Control

Mute/Volume

FilterEcho Canceller

ADC

Filter

0,6,9.5,12dB

AVDD

DAC

Generation

1 kΩ

2.12V BANDGAP

APO MB

Clock

34 dB

3.5V

CLKI CLKO

API

JUN ‘97

DS205PP2

TABLE OF CONTENTS

Absolute Maximum Ratings..............................................................................................4

Recommended Operating Conditions..............................................................................4

Power Consumption ................................................................... ......... ........ ......................4

Analog Charac te rist ics....... ... .... ... ... ... ... ................ ... ... ... ................ ... ... ... ... ................ ... ... ...4

Analog Transmission Characteristics..............................................................................5

Microphone Amplifier........................................................................................................5

Digital Characteristics .......................................................................................................5

Overview ............................................................................................................................8

Functional Description .....................................................................................................8

Analog Interface .......................................................................................................8

Acoustic Interface ..............................................................................................9

Network Interface ............................................................................................10

Microcontroller Interface .........................................................................................10

Description ......................................................................................................10

Mic - Microphone Preamplifier Enable...............................................12

TSD - Transmit Suppression Disable.................................................12

GB - Graded Beta..............................................................................12

ACC - Acoustic Coefficient Control....................................................13

RVol - Receive Volume Control.........................................................13

TGain - Transmit Analog Gain...........................................................13

HD - Half-Duplex Disable...................................................................14

RSD - Receive Suppression Disable.................................................14

Taps - AEC/NEC Tap Allocation........................................................15

NCC - Network Coefficient Control....................................................15

TVol - Transmit Volume Control.........................................................15

RGain - Receive Analog Gain............................................................15

NErle - Network ERLE Threshold......................................................16

NFNse - Network Full-Duplex Noise Threshold.................................16

RHDet - Receive Half-Duplex Detection Threshold...........................17

HDly - Half-Duplex Holdover Delay....................................................17

NseRmp - Background Noise Power Estimator Ramp Rate..............17

RSThd - Receive Suppression Threshold..........................................17

PCSen- Path Change Sensitivity.......................................................17

AErle - Acoustic ERLE Threshold......................................................18

AFNse - Acoustic Full-Duplex Noise Threshold.................................18

THDet - Transmit Half-Duplex Detection Threshold..........................18

TSAtt - Transmit Suppression Attenuation.........................................19

TSBias - Transmit Suppression Bias.................................................19

TSThd - Transmit Suppression Threshold.........................................19

HHold - Hold in Half-Duplex on Howl.................................................19

Reset ...............................................................................................................19

Clocking ..................................................................................................................19

Power Supply .........................................................................................................20

Power Down Mode ..........................................................................................20

Noise and Grounding ......................................................................................21

Design Considerations ...................................................................................................22

Algorithmic Considerations .....................................................................................22

Full-Duplex Mode ............................................................................................22

Theory of Operation..................................................................................22

Adaptive Filter...........................................................................................23

Pre-Emphasis....................................................................................23

Graded Beta.......................................................................................23

Update Control..........................................................................................24

CS6420

2 DS205PP2

Speech Detection .....................................................................................24

Half-Duplex Mode ...........................................................................................24

AGC ................................................................................................................ 25

Suppression .................................................................................................... 25

Transmit Suppression...............................................................................26

Receive Suppression................................................................................27

Circuit Design .........................................................................................................27

Interface Considerations .................................................................................27

Analog Interface........................................................................................27

Microcontroller Interface ...........................................................................27

Grounding Considerations ..............................................................................28

Layout Considerations ........................................................ ........ ....................28

System Design .......................................................................................................28

Gain Structure .................................................................................................28

Testing Issues .................................................................................................29

ERLE ........................................................................................................29

Convergence Time...................................................................................30

Half-Duplex Switching.......................................... ......... ........ ......... ...........30

Pin Descriptions ..............................................................................................................31

Analog Interface ..............................................................................................31

Microcontroller Interface .................................................................................32

Clock ............................................................................................................... 32

Power Supply ..................................................................................................32

Miscellaneous .................................................................................................33

Glossary ...........................................................................................................................34

Package Dimensions ......................................................................................................37

CS6420

DS205PP2 3

CS6420

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Min Max Units

DC Supply (AVDD, DVDD) -0.3 6.0 V Input Current (Except supply pins)

Input Voltage Analog

Digital

Ambient Operating Temperature

Storage Temperature

ina

ind

stg

WARNING: Operation beyond these limits may result in permanent damage to the device.

Normal operation is not guarant eed at these extremes.

RECOMMENDED OPERATING CONDITIONS

Parameter Symbol Min Typ Max Units

DC Supply (AVDD, DVDD) 4.5 5.0 5.5 V Ambient Operating Temperature

AOp

-10 +10 mA

-0.3

AVDD+0.3 DVDD+0.3

-40 85 °C

-65 150 °C

0 2570°C

POWER CONSUMPTION (T

= 25°C, DVDD = AVDD = 5V, f

= 20.480 MHz) (Note 1)

XTAL

Parameter Symbol Min Typ Max Units

Power Supply Current, Analog (RST Power Supply Current, Analog (RST Power Supply Current, Digital (RST Power Supply Current, Digital (RST

=0)

=1) =0) =1)

DA0

DD0

10 20 mA

50 60 mA

1mA

Notes: 1. AO and NO outputs are not loaded.

ANALOG CHARACTERISTICS (T

= 25°C, DVDD = AVDD = 5V, f

= 20.480 MHz)

XTAL

Parameter Symbol Min Typ Max Units

Input Offset Voltage (APO, NI) 2.12 V Output Offset Voltage (AO, NO) 2.12 V Transmit Group Delay (Note 2) 6 ms Receive Group Delay (Note 2) 6 ms Settling Time from RST

rising 104 ms MB Output Voltage 3.5 V MB Drive Capability 10

Input Impedance (APO, NI) (Note 2) Load Impedance (AO, NO) (Note 2)

load

10 kΩ

300 k

Power Supply Rejection (1 kHz) 40 dB

Ω

Notes: 2. These parameters are guaranteed by design or by characterization.

4 DS205PP2

CS6420

ANALOG TRANSMISSION CHARACTERISTICS (T

= 25°C, DVDD = AVDD = 5V, f

XTAL

20.480 MHz, RVol=TVol=RGain=TGain= 0 dB, HD=TSD=RSD=1, analog inputs and ouputs loaded with resistors and capacitors as shown in the typical connection diagram, Figure 2)

Parameter Symbol Min Typ Max Unit s

Idle Channel Noise A-weighted (0-20 kHz) (Inputs grounded C-Message weighted (0-4 kHz) through a capacitor) Psophometrically weighted (0-4 kHz)

Signal-to-Noise Ratio A-weighted (0-20 kHz) (Full Scale, 1kHz C-Message weighted (0-4 kHz) sine wave input) Psophometrically weighted (0-4 kHz)

-67

SNR 69

-67

-69 dBV dBrnC0

dBm0p

dBrnC0

dBm0p Total Harmonic Distortion C-Message Weighted (0-4 kHz) THD 0.1 % Programmable Gain RGain/TGain = 00

RGain/TGain = 01 RGain/TGain = 10 RGain/TGain = 11

0 6

9.5 12

Volume Control Stepsize (TVol/RVol) 3 dB ADC Full-scale Voltage Input 0.9 1.0 Vrms DAC Full-scale Voltage Output 1.0 1.1 Vrms ADC Noise Floor C-Message Weighted (0-4 kHz) -80 dBV DAC Noise Floor, DAC muted C-Message Weighted (0-4 kHz) -85 dBV

MICROPHONE AMPLIFIER (T

= 25°C, DVDD = AVDD = 5V,f

Parameter Symbol Min Typ Max Units

Gain (Zsource = 50Ω) Signal-to-Noise Ratio A-weighted (0-20 kHz) Input Impedance Input Offset Voltage

DIGITAL CHARACTERISTICS (T

= 25°C, DVDD = AVDD = 5V,f

Parameter Symbol Min Typ Max Units

High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance

mic

SNR

inm

offm

leak

= 20.480 MHz)

XTAL

34 dB

63 dB

Ω

2.12 V

= 20.480 MHz)

XTAL

DVDD-1.0 V

1.0 V 10

5pF

DS205PP2 5

SWITCHING CHARACTERISTICS

Parameter Symbol Min Typ Max Units

Input rise time

low time

RST CLKI frequency CLKI duty cycle

frequency

DRDY STROBE frequency

to STROBE setup time

DRDY DATA to STROBE setup time STROBE to DATA hold time STROBE to DRDY

hold time

rise

RSTL

XTAL

LCLKI

DRDY

STROBE

sDRDY

sDATA

hDATA

hDRDY

CS6420

1.0 µs

18.432 20.480 22.528 MHz 40 50 60 %

DC f DC 9.0 MHz

30 ns 30 ns 30 ns 30 ns

/ 2560 kHz

XTAL

DRDY

sDRDY

hDRDY

STROBE

DATA

sDATA

Bit15

hDATA

Bit14

Bit0

Figure 1. Microcontroller Interface Switching Characteristics

6 DS205PP2

Telephone

Line Out

Telephone Line In

3300 pF

0.47 µF

1 µF

6.04 k

3300 pF

0.1 µF

12.1 k

Ω

CS6420

ferrite bead

+5V Analog

0.1

DVDD

DGND

Ω

AVDD

AGND

APO

API

1 2

0.1 µF

0.022

0.47 µF

1 µF

10 µF

10 k

Ω

+5V Analog

1.5 k

Ω

Telephone

Line Out

Telephone Line In

From

Microprocessor

8 7

6 5

DATA

STROBE DRDY RST

NC1NC2NC3NC4

1112

20.480 MHz

22pF

12.1 k

Ω

3300pF

CLKOCLKI

22pF

Figure 2. Typical Connection Diagram (Microphone Preamplifier Enabled)

ferrite bead

+5V Analog

0.1

1 2

1 µF

0.47 µF

6.04 k

Ω

0.47

3300 pF

0.1 µF

10 µF

3300 pF

0.47 µF

6.04 k

3300 pF

0.1 µF

12.1 k

Ω

16 15

DVDD DGND

AVDD

AGND

API

Ω

APO

near-end

input

DATA

From

Microprocessor

6 5

STROBE DRDY RST

NC1NC2NC3NC4

20.480 MHz

22pF

12.1 k

Ω

3300pF

CLKOCLKI

13149101112

22pF

Figure 3. Typical Connection Diagram (Microphone Preamplifier Disabled)

DS205PP2 7

CS6420

OVERVIEW

The CS6420 is a full-duplex speakerphone chip for use in hands-free comm unications with teleph ony quality audio. Common applications include speakerphones, inexpensive video-conferencing, and cellular ph one car kits. The CS6420 require s very few external comp onents and allows system control through a microcontroller int erface.

Hands-free com munication thro ugh a microph one and speaker t ypically results i n acoustic feedba ck or howling because the loop gain of the system exceeds un ity by the time audi o amplitudes are ad justed to a reasonable level. The solution to the howling problem has typically been half-duplex, where either the transmit or the receive channel is active, neve r both at the same time. T his prevent s the howl ing, but di minishe s the ove rall com munication quality by clipping words and forcing the talker at each end to wait for the talker at the other end to stop speaking.

Full-duplex conv er sation , where bot h transm it and receive c hannels are active simult aneously, is t he conversation quality we enjoy when using handsets. Full-duplex for hands-free communications is achieved in the CS 6420 using a digita l signal pro-

cessing te chnique called “Echo Cancellation.” The end result is a more natural conversation than halfduplex, with no awkward breaks and pauses, as if both parties were spea king to each other directly.

Echo Cancellation reduces overall loop gain and the acousti c coupling between speaker and m icrophone. This coupling reduction prevents the annoying effect of hearing one’s own delayed speech, the effect being w orse when there is delay in the system, such as vocoder delay in digital cellular phones.

The CS6 420 i s a comp le te sys tem im pl eme ntat ion of a Digital Signal Processor with RAM and pro gram ROM, running Echo Cancellation algorithms developed at Crystal Semiconductor using customer input, integrated with two delta-sigma codecs.

The CS6420 is intended to provide a full-duplex speakerphone so lution with a mi nimum of design effort while displa cing exist ing ha lf-dupl ex spe akerphone chips.

FUNCTIONAL DESCRIPTION

The CS6420 is ro ughly divided into four external interface blocks. The analog inte rfaces connect the chip to the transmit and receive paths. Certain control functions are accessible through the microcontroller interface. Two pins accommodate either a crystal or an externally applied digital clock signal. Analog and digit al powe r and ground are provided through four pin s.

Analog Interface

In a speakerphone application, one input of the CS6420 connects to the signal from the microphone, sometimes called the near-end input or transmit input, and one output connects to the speaker. The output that leads to the speaker is sometimes called the near-end output or receive output. Together, the input and output that connect to the microphone and speaker are referred to as the Acoustic Interface.

The signal received at the near-end input is then passed to the far-end output or transmit output after acoustic echo cancellation. This signal is sent to the telephone l ine. The signal fr om the telephon e line is received at the f ar-end i nput, al so called the receive input , and t his s igna l is pa ssed to the rec eive output after network echo cancell ation. Together, the far-end in put an d output form the Network In terface.

The analog interfaces are physically implemented using delta sigma converters runnin g at an output word rate of 8 kHz, resulting in a passband from DC to 4 kHz. Because the inputs are analog to digital converters (ADCs), certain design considerations must be kept in mind: specifically, antialiasing and full-scale input voltage. The ADCs expect a single-pole RC filter with a corner at 8 kHz,

8 DS205PP2

CS6420

PGA

0,6,9.5,12 dB

ADC

DAC

FAR-END

DAC

ADC

Receive Path

Transmit Path

Figure 4. Analog Interface

and they are post-compensated internally to prevent any resultant passband droop. The ADCs also expect a max imum of 1 V

(2.8 Vpp) at their in -

rms

puts (which are biased around 2.12 VDC). A signal of higher amplitude will clip the ADC input and may result in poor echo canceller performance. See the Design Considerations section for more details.

The outputs a re delta-si gma digita l to analo g converters (DACs) and have similar requirements to the ADCs. Th e DACs are pre -compensated to expect a single-pole RC filter with a corner frequency at 4 kHz. The full scale voltage output from a DAC is 1 V

(2.8 Vpp) swinging around a DC bias o f

rms

2.12 V.

Acoustic Interface

The pins API (pin 20), APO (pin 18), MB (pin 19), and AO (pin 3) make up the A coustic Inter face. A block diagram of the Acoustic Interface is shown in Figure 4.

AO 3

PGA

0,6,9.5,12 dB

Ω

2.12V

BANDGAP

NEAR-END

34 dB

3.5V 19 MB18 APO

API 20

API and APO are, respective ly, the input and out put of the built-in analog pre-amplifier. The preamplifier is an inverting amplifier with a fixed gain of 34 dB biased around an input offset voltage

) of 2.12 V. APO is the ou tput of t he pre-a m-

off

plifier after a 1 kΩ resistor. The circuitry connected to the amplifier input must present low source impedance (<100Ω) to the API pin or the gain will be reduced. When using the pre-amplifier, connecting a 0.022 µF capa citor to g round off AP O will pro vide the anti-aliasing filter required by the ADC, as shown in Figure 2. The pre-amplifier may be bypassed by clearing Mic (Register 0, bit 15) using the Microcontroller Interface (see Microcontroller In- terface se ctio n), grounding API th rough a capacito r, and driving APO direc tly. In this case , the signal into APO must be low-pass filtered by a single-pole RC filter with a corner f requency at 8 kHz (see Figu re 3 ).

Following the pre-amplifier is a programmable analog gain stage (PGA) which is controllable through the Microcontroller Interface. This gain

DS205PP2 9

CS6420

stage a llows gai ns of 0 dB, 6 dB, 9. 5 dB, an d 12 dB to be added prior to the ADC input. The default gain stage setting i s 0 dB.

The signal at APO sh ould no t exceed 2.8 V

at the

default gai n stage setting. If other gain stages are used then the full-scale signal at APO must also change. Ta ble 1 shows ful l-scale voltages as measured at APO for given programmable gains:

Gain Setting Full-scale Voltage

0 dB 6 dB

9.5 dB 12 dB

Table 1. Full scale voltages for each gain stage.

2.8 V

1.4 V

0.94 V

0.71 V

pp pp

MB provides a stable 3.5 VDC output from the onboard voltage reference of the CS64 20. MB may not be connected to any load. MB serves to provide decoupling for the inte rnal 2.12 VDC bandgap reference, and must have a 0.1 µF and a 10 µF capacitor to ground for bypass. Noise on MB will

strongly influence the overall analog performance of the CS6420.

The acoustic out put, AO, should connect to a single-pole low-pass RC network with a corner frequency of 4 kHz, which will filter out-of-band components. The maximum voltage swing at AO is

2.8 V

. AO is capable of driving down to a 10 kΩ

load.

Network Interface

The pins NI (pin 17) and NO (pin 4) make up t he Network Inter face. The deta ils of the Netwo rk Interface are shown in Figure 4.

NI is the input from the telephone network side into the CS6420 . The signal i nto NI mu st be low pass filtered by a single-pole RC filter with a corner frequency of 8 kHz.

A programmable analog gain stage (PGA) accessible through the Microcontroller Interface amplifies signals received at NI. This gain stage allows gains of 0 dB, 6 dB, 9.5 d B, and 12 dB to be added prio r to the ADC input. The default gain stage setting for the network sid e is 0 dB .

The signal at NI should not exceed 2.8 V

at the

default gai n stage setting. If other gain stages are used then the full-scale signal at NI must also change. Ta ble 1 shows ful l-scale vo ltages as me asured at NI for given prog rammable gains.

The output to the telephone network side, NO, should conne c t t o a single pole RC network with a corner frequency at 4 kHz, which will filter out-ofband component s. The maximum swing NO is capable of producing is 2.8 V

. NO is capable of

driving down to a 10 kΩ load.

Microcontroller Interface

Several control functions of the CS6420 are accessible through its Microc ontroller Interface, which consists of three pins: DATA (pin 8), STROBE (pin 7), and DRDY

(pin 6). These inputs are intended to connect to th e outputs of a microcontroll er to allow write-only access to the 16-bit Microcontroller Control Regi ster (MCR).

The RST

(pin 5 ) pin, wh ich aff ects th e entir e inte grated circuit, is especially significant to the Microcontroller Interface. RST

is used to place the CS6420 into a known state of opera tion. Two subtypes of reset are possible: cold reset and warm reset.

Description

The Microcont roller Interface is imple mented by a serial shift register gated by DRDY troller begins the transaction by setting DRDY and STROBE low. The most significant bit (MSB), Bit 15, of the 16-bit data word should be presented to the DATA pin and then STROBE should be brought hi gh to shi ft the data bi t into the CS64 20. STROBE should be brought low again so it is ready

. The microcon-

low

10 DS205PP2

CS6420

to shift t h e next bit into the shift register. The next data bit s hould then be p res ented to the DA T A pin ready to be latched by the rising edge of STROBE. This procedure repeats for all sixteen bits as shown in Figure 5. A fter the last bit has be en shifted in, DRDY

should be brou ght high to indicate the conclusion of the transfer, and four extra STROBE pulses must be applied to latch the data into the CS6420.

Since the MCR is a shift register, the STROBE can be run arbitrarily slow with a duty cycle limited only by the hold time specified in the Switching Characterstics table. The Microcontroller Interface

STROBE

is read once every 125 µs, so it must not be updated faster than thi s .

The four control registers accessible through the MCR are described in detail in the following tables. These regi sters are a ddresse d by bits b 2 and b1 of the MCR. Bit b0 must always be 0. Table 2 shows the relat ive bit positions of al l the registers. T ables 3 to 6 show the four control registers in more detail.

The Register Map at the top of each register description shows the names of all the bits, with their reset va lues belo w the bit field name. The reset va lue can also be found in the Word column of the bit-

field summ ary as indicated by an ‘*’.

four extra strobe pulses

1234

Bit15 Bit14 Bit13

DRDY

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Mic TSD GB ACC RVol TGain 0 0 0 HD RSD Taps NCC TVol RGain 0 1 0

NErle NFNse RHDet HDly NseRmp RSThd PCSen 1 0 0 AErle AFNse THDet TSAtt TSBias TSThd HHold 1 1 0

Bit12

Bit11 Bit10

Bit9

Bit8

Bit7 Bit6 Bit5 Bit4

Figure 5. Microcontroller Interface

Table 2. MCR Control Register Mapping

Bit3

Bit2

Bit1

Bit0DATA

DS205PP2 11

CS6420

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Mic TSD GB ACC RVol TGain 0 0 0

1 0 10 00 00100 00 0 0 0

Bits Name Function Word Operation

15 Mic Microphone Preamplifier Enable

14 TSD Tx Suppression Disable

13-12 GB Graded Beta

11-10 ACC AEC Coefficient Control

9-5 RVol Rx Volume Control

4-3 TGa i n Tx Ana log Gain

1* 0*

00 01

10*

00*

01 10

11 00000 00001

---

00100*

--01010 01011

--11101 11110 11111

00*

01 10 11

disable preamp

enable preamp

enable Tx suppression

disable Tx suppression

0.00 dB/ms

0.75 dB/ms

0.38 dB/ms

0.19 dB/ms Normal

Clear

Freeze

reserved

+30 dB +27 dB

+18 dB

+0 dB

-3 dB

-57 dB

-60 dB mute

0 dB 6 dB

9.5 dB

12 dB

* Denotes reset value

Mic - Microphone Preamplifier Enable

The microphone preamplifier described in the Acoustic Interface section is enabled by default, but may be disabled by se tting Mic to 0. Refer to the Acoustic Interf ace section for more de tails on using/disabling the Microphone Preamplifier.

Table 3. Register 0 Bit Definitions

(see Register 3) dB of attenuation into the transmit path only when there is sp eech d etected in th e receive path and no near-end speech. When only near-end speec h is presen t, or if t he re is no sp ee ch in either direction, the suppression attenuation is removed. By default, the transmit suppression function is enabled.

TSD - Transmit Suppression Disable

GB - Graded Beta

The Transmit Supplementary Echo Suppression function i s a non-linear echo control mechanism . The Transmit Suppression will introduce TSAtt

12 DS205PP2

The room-size adjustment scheme called “graded beta,” provided for the acoustic echo canceller in the

CS6420

CS6420, is controlled by GB. The network echo canceller does not support gr aded beta.

Graded be ta is an architectural enhancement to the CS6420 which takes advantage of the fact that acoustic echoes tend to decay exponentially with time. The CS6 420 can i ncre ase th e bet a, o r up date gain, for the coefficients of the adaptive filter which occur earlier in time and decrease it for those that occur later in time, which increases convergence speed while maintaining stability. In order to make this improvement, there is an implicit assumption that the decay rate of the echo is known. The graded beta control allows the system designer to adjust this. For very acoustically live r ooms, use either no decay (00) o r sl ight decay (11) . Cars and acou stically dead rooms can benefit fr om the most rapid decay (01).

ACC - Acoustic Coefficient Control

The coeffi cients of t he AEC adap tive fi lters i n the CS6420 are control led by ACC. The default position (00) yields normal operation, which means the coefficients are free to adjust themselves to the echo path in order to ca ncel ec ho. Whe n set to the clear posit ion (01), the a daptive filte r coefficient s are all held at zero, so the echo canceller is effectively disabled. Note that unless the half-duplex mode is dis abled, this will force the CS6420 i nto half-duplex m ode. Th e freeze position (10) cause s the coefficients to hold their cu rrent values.

RVol - Receive Volume Control

Volume in th e recei ve pat h is set by RVol . The vo lume control in the receive direction is implemented by a peak-lim iting automatic gain control (AGC) and digital attenuation at the near-end output DAC.

The AGC is discussed in det ail in the Design Con- siderations section. See the sub-section on AGC for a full explana ti on of how it functions.

When the refere nce l evel is set to +0 dB , the AGC is effectively disabled. Volume control is implemented by digital attenuation in 3 dB steps from this point on down. The maximum gain is +30 dB and the minimum is -60 dB in 3 dB steps. The lowest gain setting (11111) mutes th e receive path.

The default setting for the receive reference level is +18 dB.

TGain - Transmit Analog Gain

TGain selects the amount of additional on-chip analog gain to be supplied to the acoustic input of the CS6420. A programmable gain amplifier (PGA) exists be fore each A DC wh ich allo ws 0 dB , 6 d B,

9.5 dB, or 12 dB of ga in to be adde d to the signal path. The aco usti c si de de faults to 0 dB of gain.

Note: Changing the analog gain will change the full-

scale voltage as applied to the input pin. Make sure that the ADC input does not clip with the gain stage on.

DS205PP2 13

CS6420

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

HD RSD Taps NCC TVol RGain 0 1 0

0 0 10 00 01010 00 0 1 0

Bits Name Function Word Operation

15 HD Half-Duplex Disable

14 RSD Rx Suppression Disable

13-12 Taps AEC/NEC Tap Allocati on

11-10 NCC NEC Coefficient Control

9-5 TVol Tx Volume Control

4-3 RGai n Rx An alog Gain

00 01

10*

00*

01 10

11 00000 00001

---

00100

---

01010*

01011

--11101 11110 11111

00*

01 10 11

enable half-duplex

disable half-duplex

enable Rx suppression

disable Rx suppression

444/0 (55.5ms/disabled)

380/128 (47.5ms/16ms) 316/192 (39.5ms/24ms) 252/256 (31.5ms/32ms)

Normal

Clear

Freeze

reserved

+30 dB +27 dB

+18 dB

+0 dB

-3 dB

-57 dB

-60 dB mute

0 dB 6 dB

9.5 dB

12 dB

* Denotes reset value

HD - Half-Duplex Disable

In normal opera tion, th e CS6420 will be in a half duplex mode i f the echo canc ell er is n ot prov id ing

Table 4. Register 1 Bit Definitions

mode is undesirable. By default, the half-duplex mode is enable d.

RSD - Receive Suppression Disable

enough loop gain reduction to prevent howling. This half-dup lex mode would be act ive at powerup, for example, before the adaptive filter has had a chance to adapt. This half-duplex mode prevents howling an d al s o ma s k s the convergence proc es s .

In some cases, such as when measuring convergence speed (see Testing Issues), the half-duplex

14 DS205PP2

The Receive Supplementary Echo Suppression function i s a non-linear echo control mechanism . Supplementary Echo Suppression attenuates signals in the receive direction by 24 dB when far-end speech is ab sent in the receiv e path. The atten uation is released only when the receive channel is active. It is also designed to not be triggered by

CS6420

network echo. By de fault , the re cei ve suppre ssion function is ena bled.

Taps - AEC/NEC Tap Allocation

The CS6420 has a total of 63.5 ms of echo canceller taps that it can partition for use by the network and acoustic echo cancellers. By default, the CS6420 allocate s 39.5 ms for th e AEC and 24 ms f or the NEC. Some applications will never have a network echo path, and so should allocate all taps for the AEC. See NErle and NFNse in Register 2, and AErle and AFNse in Register 3 for more options when an echo path i s none xistent.

NCC - Network Coefficient Control

The NEC adaptive filter’s coefficients are controlled by NCC. See ACC in Register 0 for more details. The default setting for NCC is Normal mode.

TVol - Transmit Volume Control

Volume in the transmit path is co ntrolled by TVol . Like receive volume, the transmit vol ume is controlled by an AGC. See RVol in Register 0 for more details. The default setting for the transmit reference level is +0 dB.

RGain - Receive Analog Gain

RGain selects the amount of additional on-chip analog gain to be supplied to the network input of the CS6420. A programmable gain amplifier (PGA) exists be fore each A DC wh ich allow s 0 dB , 6 d B,

9.5 dB, or 12 dB of ga in to be adde d to the signal path. The network side defaults to 0 dB of gain.

Note: Changing the analog gain will change the full-

scale voltage as applied to the input pin. Make sure that the ADC input does not clip with the gain stage on.

DS205PP2 15

CS6420

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

NErle NFNse RHDet HDly NseRmp RSThd PCSen 1 0 0

00 00 00 00 00 00 0 1 0 0

Bits Name Function Word Operation

15-14 NErle NEC ERLE Threshold

13-12 NFNse NEC Full-Duplex Noise Threshold

11-10 RHDet Rx Half-Duplex Detection Threshold

9-8 HDly Half-Duplex Holdover Delay

7-6 NseRmp Background Power Estimator Ramp Rate

5-4 RSThd Rx Suppression Threshold

3 PCSen Path Change Sensitivity

00*

01 10 11

00*

01 10 11

00*

01 10 11

00*

01 10 11

00*

01 10 11

00*

01 10 11

24 dB 18 dB 30 dB

reserved

zero

-42 dB

-54 dB

reserved

5 dB 3 dB 6 dB

reserved

200 ms 100 ms 150 ms

reserved

1 s

0.5 s 2 s

reserved

5 dB 3 dB 6 dB

reserved

high sensitivity

low sensit iv it y

* Denotes reset value

NErle - Network ERLE Threshold

The CS6420 wil l allow full- duplex ope ration only when the Ne tw o rk ERLE exceed s th e threshold s et by NErle. See also NFNse. See Glossary for a definition o f ERLE.

Table 5. Register 2 Bit Definitions

far-end input is greater than NFNse , then NErle is used to determ ine if full-dupl ex is allowed. If the noise level is below the level of NFNse, the CS6420 uses an internal estimate of asymptotic performance to determine whether or not to transition to full-duplex. If NFNse is zero, NErle is al-

NFNse - Network Full-Duplex Noise Threshold

NFNse works in conjunction with NErle to determine when the CS64 20 should tra nsition in to fullduplex ope ration. If the curr ent noise leve l at the

16 DS205PP2

ways used as the full-duplex criterion. The other values exi st f or c ase s wh ere the re is n ot a net work path to converge to, or the existence of a network path can not be determined prior to pl acing a call.

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