Cirrus Logic CS61884-IQ, CS61884-IB Datasheet
Octal T1/E1/J1 Line Interface Unit
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CS61884
Features
Industry Standard Footprint
Octal E1/T1/J1 Short-haul Line Interface Unit
Low Power
No External Component Changes for
100 Ω/120 Ω/75 Ω Operation
Pulse Shapes can be customized by the user
Internal AMI, B8ZS, or HDB3 Encoding/Decoding
LOS Detection per T1.231, ITU G.775, ETSI 300-233
G.772 Non-Intrusive Monitoring
G.703 BITS Clock Recovery
Crystal-less Jitter Attenuation
Serial/Parallel Microprocessor Control Interfaces
Transmitter Short Circuit Current Limiter (<50mA)
TX Drivers with Fast High-Z and Power Down
JTAG Boundary Scan compliant to IEEE 1149.1
144-Pin LQFP or 160-Pin BGA Package
ORDERING INFORMATION
CS61884-IQ 144-pin LQFP
CS61884-IB 160-pin FBGA
Description
The CS61884 is a full-featured Octal E1/T1/J1 shorthaul LIU that supports both 1.544 Mbps or 2.048 Mbps
data transmission. Each channel provides crystal-less
jitter attenuation that complies with the most stringent
standards. Each channel also provides internal
AMI/B8ZS/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be
configured for G.772 non-intrusive monitoring of any of
the other 7 channels’ receive or transmit paths.
The CS61884 makes use of ultra low power matched impedance transmitters and receivers to reduce power
beyond that achieved by traditional driver designs. By
achieving a more precise line match, this technique also
provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the
external component count. All transmitters have controls
for independent power down and High-Z.
Each receiver provides reliable data recovery with over
12 dB of cable attenuation. The receiver also incorporates LOS detection compliant to the most recent
specifications.
Note: Click on any text in blue to go to cross-references.
LOS
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Decoder
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RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
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0
Encoder
Remote Loopback
Jitter
Attenuator
7
JTAG
Serial
Port
JTAG Interface
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
LOS
Digital Loopback
Clock
Recovery
Recovery
Data
Receiver
Analog Loopback
G.772 Monitor
RTIP
RRING
Driver
Transmit
Control
Pulse
Shaper
Host Interface
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
CopyrightCirrus Logic, Inc. 2002
(All Rights Reserved)
TTIP
TRING
Host
Serial/Parallel
Port
DS485PP4
MAY ‘02
1
CS61884
TABLE OF CONTENTS
1. PINOUT - LQFP ........................................................................................................................................ 7
2. PINOUT - FBGA ........................................................................................................................................ 8
3. PIN DESCRIPTIONS ................................................................................................................................. 9
3.1 Power Supplies .................................................................................................................................. 9
3.2 Control .............................................................................................................................................. 10
3.3 Address Inputs/Loopbacks ............................................................................................................... 14
3.4 Cable Select ..................................................................................................................................... 15
3.5 Status ............................................................................................................................................... 15
3.6 Digital Rx/Tx Data I/O ....................................................................................................................... 16
3.7 Analog RX/TX Data I/O .................................................................................................................... 19
3.8 JTAG Test Interface ......................................................................................................................... 21
3.9 Miscellaneous ................................................................................................................................... 21
4. OPERATION ........................................................................................................................................... 22
5. POWER-UP ............................................................................................................................................. 22
6. MASTER CLOCK .................................................................................................................................... 22
7. G.772 MONITORING ............................................................................................................................... 22
8. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE .................................................. 23
9. TRANSMITTER ....................................................................................................................................... 24
9.1 Bipolar Mode .................................................................................................................................... 25
9.2 Unipolar Mode .................................................................................................................................. 25
9.3 RZ Mode ........................................................................................................................................... 25
9.4 Transmitter Powerdown / High-Z ...................................................................................................... 25
9.5 Transmit All Ones (TAOS) ................................................................................................................ 25
9.6 Automatic TAOS ............................................................................................................................... 26
9.7 Driver Failure Monitor ....................................................................................................................... 26
9.8 Driver Short Circuit Protection .......................................................................................................... 26
10. RECEIVER ............................................................................................................................................ 26
10.1 Bipolar Output Mode ...................................................................................................................... 26
10.2 Unipolar Output Mode .................................................................................................................... 26
10.3 RZ Output Mode ............................................................................................................................. 27
10.4 Receiver Powerdown/High-Z .......................................................................................................... 27
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at:
http://www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE
"Preliminary" product inf ormation describes products that are in production, but for which full characterization data is not yet available. "Advance" product inf ormation describes products that are i n development and subject to development changes. Cirrus Logic, I nc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty
of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being
relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and l imitation of liability. No responsibil ity is assumed by Ci rrus f or the use of this information, including use of this
information as the basis for manufacture or sale of any items, or for i nfringement of patents or other rights of third parties. This document is the property of Cir rus
and by furnishi ng this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or
other intellectual property rights. Cirr us owns the copyrights of the i nformation contained herein and gives consent for copies to be made of the information only
for use within your or ganization with respect to Cirrus integrated circui ts or ot her parts of Cir rus. This consent does not ext end to other copying such as copying
for general distribution, advertising or pr omotional purposes, or for creating any work for resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thismaterial and controll ed under the "Foreign Exchange and Forei gn Trade Law" i s to be exported or taken out of Japan. An export l icense and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies describe d in this material is subject to the PRC Foreign
Trade Law and i s to be exported or taken out of the PRC.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS
IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.
Cirrus Logic, Cirrus, and the Ci rrus Logi c logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in thi s document may be trademarks or service marks of their respective owners.
2 DS485PP4
CS61884
10.5 Loss-of-Signal (LOS) .......................................................................................................................27
10.6 Alarm Indication Signal (AIS) ..........................................................................................................28
11. JITTER ATTENUATOR .........................................................................................................................28
12. OPERATIONAL SUMMARY ..................................................................................................................29
12.1 Loopbacks .......................................................................................................................................29
12.2 Analog Loopback ............................................................................................................................29
12.3 Digital Loopback ..............................................................................................................................30
12.4 Remote Loopback ...........................................................................................................................30
13. HOST MODE ..........................................................................................................................................32
13.1 SOFTWARE RESET ....................................................................................................................... 32
13.2 Serial Port Operation .......................................................................................................................32
13.3 Parallel Port Operation ....................................................................................................................33
13.4 Register Set ....................................................................................................................................34
14. REGISTER DESCRIPTIONS .................................................................................................................35
14.1 Revision/IDcode Register (00h) ......................................................................................................35
14.2 Analog Loopback Register (01h) .....................................................................................................35
14.3 Remote Loopback Register (02h) ...................................................................................................35
14.4 TAOS Enable Register (03h) ..........................................................................................................35
14.5 LOS Status Register (04h) ..............................................................................................................35
14.6 DFM Status Register (05h) .............................................................................................................35
14.7 LOS Interrupt Enable Register (06h) ...............................................................................................36
14.8 DFM Interrupt Enable Register (07h) ..............................................................................................36
14.9 LOS Interrupt Status Register (08h) ................................................................................................36
14.10 DFM Interrupt Status Register (09h) .............................................................................................36
14.11 Software Reset Register (0Ah) .....................................................................................................36
14.12 Performance Monitor Register (0Bh) ............................................................................................36
14.13 Digital Loopback Reset Register (0Ch) .........................................................................................37
14.14 LOS/AIS Mode Enable Register (0Dh) ..........................................................................................37
14.15 Automatic TAOS Register (0Eh) ...................................................................................................37
14.16 Global Control Register (0Fh) .......................................................................................................38
14.17 Line Length Channel ID Register (10h) .........................................................................................38
14.18 Line Length Data Register (11h) ...................................................................................................39
14.19 Output Disable Register (12h) .......................................................................................................39
14.20 AIS Status Register (13h) ............................................................................................................. 39
14.21 AIS Interrupt Enable Register (14h) ..............................................................................................39
14.22 AIS Interrupt Status Register (15h) ...............................................................................................40
14.23 AWG Broadcast Register (16h) .....................................................................................................40
14.24 AWG Phase Address Register (17h) ............................................................................................40
14.25 AWG Phase Data Register (18h) ..................................................................................................40
14.26 AWG Enable Register (19h) ..........................................................................................................40
14.27 AWG Overflow Interrupt Enable Register (1Ah) ............................................................................41
14.28 AWG Overflow Interrupt Status Register (1Bh) .............................................................................41
14.29 JA Error Interrupt Enable Register (1Ch) ......................................................................................41
14.30 JA Error Interrupt Status Register (1Dh) .......................................................................................41
14.31 Bits Clock Enable Register (1Eh) ..................................................................................................41
14.32 Reserved Register (1Fh) ...............................................................................................................41
14.33 Status Registers ............................................................................................................................42
14.33.1 Interrupt Enable Registers ...................................................................................................42
14.33.2 Interrupt Status Registers ....................................................................................................42
15. ARBITRARY WAVEFORM GENERATOR ............................................................................................43
16. JTAG SUPPORT ....................................................................................................................................45
16.1 TAP Controller .................................................................................................................................45
16.1.1 JTAG Reset ...........................................................................................................................45
DS485PP4 3
CS61884
16.1.2 Test-Logic-Reset ................................................................................................................... 45
16.1.3 Run-Test-Idle ........................................................................................................................ 45
16.1.4 Select-DR-Scan .................................................................................................................... 46
16.1.5 Capture-DR ........................................................................................................................... 46
16.1.6 Shift-DR ................................................................................................................................ 46
16.1.7 Exit1-DR ................................................................................................................................ 46
16.1.8 Pause-DR ............................................................................................................................. 46
16.1.9 Exit2-DR ................................................................................................................................ 46
16.1.10 Update-DR .......................................................................................................................... 46
16.1.11 Select-IR-Scan .................................................................................................................... 47
16.1.12 Capture-IR .......................................................................................................................... 47
16.1.13 Shift-IR ................................................................................................................................ 47
16.1.14 Exit1-IR ............................................................................................................................... 47
16.1.15 Pause-IR ............................................................................................................................. 47
16.1.16 Exit2-IR ............................................................................................................................... 47
16.1.17 Update-IR ........................................................................................................................... 47
16.2 Instruction Register (IR) ................................................................................................................. 47
16.2.1 EXTEST ................................................................................................................................ 47
16.2.2 SAMPLE/PRELOAD ............................................................................................................. 47
16.2.3 IDCODE ................................................................................................................................ 47
16.2.4 BYPASS ............................................................................................................................... 47
16.3 Device ID Register (IDR) ................................................................................................................ 48
17. BOUNDARY SCAN REGISTER (BSR) ................................................................................................ 48
18. APPLICATIONS .................................................................................................................................... 51
18.1 Transformer specifications ............................................................................................................. 53
18.2 Crystal Oscillator Specifications ..................................................................................................... 53
18.3 Designing for AT&T 62411 ............................................................................................................. 53
18.4 Line Protection ............................................................................................................................... 53
19. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 54
19.1 Absolute Maximum Ratings ............................................................................................................ 54
19.2 Recommended Operating Conditions ............................................................................................ 54
19.3 Digital Characteristics ..................................................................................................................... 55
19.4 Transmitter Analog Characteristics ................................................................................................ 55
19.5 Receiver Analog Characteristics .................................................................................................... 56
19.6 Jitter Attenuator Characteristics ..................................................................................................... 57
19.7 Master Clock Switching Characteristics .........................................................................................59
19.8 Transmit Switching Characteristics ................................................................................................ 59
19.9 Receive Switching Characteristics ................................................................................................. 59
19.10 Switching Characteristics - Serial Port ......................................................................................... 61
19.11 Switching Characteristics - Parallel Port (Multiplexed Mode) ...................................................... 62
19.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode) ............................................... 65
19.13 Switching Characteristics - JTAG ................................................................................................. 68
20. COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS ........................................................... 69
21. FBGA PACKAGE DIMENSIONS .......................................................................................................... 70
22. LQFP PACKAGE DIMENSIONS ..................................................................................................... 71
4 DS485PP4
CS61884
LIST OF FIGURES
Figure 1. CS61884 144-Pin Outs ....................................................................................................... 7
Figure 2. CS61884 160-Ball FBGA Pin Outs .................................................................................... 8
Figure 3. G.703 BITS Clock Mode in NRZ Mode .......................................................................... 23
Figure 4. G.703 BITS Clock Mode in RZ Mode ............................................................................. 23
Figure 5. G.703 BITS Clock Mode in Remote Loopback ............................................................... 23
Figure 6. Pulse Mask at T1/J1 Interface .......................................................................................... 24
Figure 7. Pulse Mask at E1 Interface .............................................................................................. 24
Figure 8. Analog Loopback Block Diagram .................................................................................... 30
Figure 9. Analog Loopback with TAOS Block Diagram ................................................................ 30
Figure 10. Digital Loopback Block Diagram .................................................................................. 31
Figure 11. Digital Loopback with TAOS ........................................................................................ 31
Figure 12. Remote Loopback Block Diagram ................................................................................. 31
Figure 13. Serial Read/Write Format (SPOL = 0) ........................................................................... 33
Figure 14. Arbitrary Waveform UI .................................................................................................. 43
Figure 15. Test Access Port Architecture ........................................................................................ 45
Figure 16. TAP Controller State Diagram ....................................................................................... 46
Figure 17. Internal RX/TX Impedance Matching ............................................................................ 51
Figure 18. Internal TX, External RX Impedance Matching ............................................................ 52
Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 ........................... 58
Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 ............................................ 58
Figure 21. Recovered Clock and Data Switching Characteristics ................................................... 60
Figure 22. Transmit Clock and Data Switching Characteristics ...................................................... 60
Figure 23. Signal Rise and Fall Characteristics ............................................................................... 60
Figure 24. Serial Port Read Timing Diagram .................................................................................. 61
Figure 25. Serial Port Write Timing Diagram ................................................................................. 61
Figure 26. Parallel Port Timing - Write; Intel Multiplexed Address / Data Bus Mode ................... 63
Figure 27. Parallel Mode Port Timing - Read; Intel Multiplexed Address / Data Bus Mode ........ 63
Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus .................. 64
Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus ................... 64
Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode ....... 66
Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode ........ 66
Figure 32. Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67
Figure 33. Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode . 67
Figure 34. JTAG Switching Characteristics .................................................................................... 68
DS485PP4 5
CS61884
LIST OF TABLES
Table 1. Operation Mode Selection ................................................................................................. 10
Table 2. Mux/Bits Clock Selection .................................................................................................. 11
Table 3. Cable Impedance Selection ................................................................................................ 15
Table 4. G.772 Address Selection ....................................................................................................22
Table 5. Hardware Mode Line Length Configuration Selection ...................................................... 25
Table 6. Jitter Attenuator Configurations .........................................................................................28
Table 7. Operational Summary ........................................................................................................ 29
Table 8. Host Control Signal Descriptions ...................................................................................... 32
Table 9. Host Mode Register Set ..................................................................................................... 34
Table 10. JTAG Instructions ............................................................................................................ 47
Table 11. Boundary Scan Register ................................................................................................... 48
Table 12. Transformer Specifications .............................................................................................. 53
6 DS485PP4
1. PINOUT - LQFP
TPOS7/TDATA7
TCLK7
LOS6
RNEG6/BPV6
RPOS6/RDATA6
RCLK6
TNEG6/UBS6
TPOS6/TDATA6
TCLK6
MCL K
MOD E
A4
A3
A2
A1
A0
VCCIO
GNDIO
RV0+
RGND0
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
TCLK1
TPOS1/TDATA1
TNEG1/UBS1
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
LOS1
TCLK0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
TNEG7/UBS7
144
RCLK7
RPOS7/RDATA7
143
142
CS61884
RNEG7/BPV7
LOS7
RTIP7
RRING7
TV+7
TTIP7
TRING7
TGND7
RRING6
RTIP6
TGND6
TRING6
TTIP6
TV+6
RTIP5
RRING5
TV+5
TTIP5
TRING5
TGND5
RRING4
RTIP4
TGND4
TRING4
TTIP4
TV+4
CLKE
TXOE
LOS4
RNEG4/BPV4
RPOS4/RDATA4
RCLK4
TNEG4/UBS4
118
116
115
140
139
138
137
136
141
135
134
133
132
131
130
129
127
126
125
124
123
122
120
128
121
119
CS6188 4
144-Pin
LQFP
(Top View)
117
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TPOS4/TDATA4
TCLK4
LOS5
RNEG5/BPV5
RPOS5/RDATA5
RCLK5
TNEG5/UBS5
TPOS5/TDATA5
TCLK5
TDI
TDO
TCK
TMS
TRST
REF
CBLSEL
VCCIO
GNDIO
RV1+
RGND1
INTL/MOT/CODEN
CS/JASEL
ALE/AS/SCLK/LEN2
RD/RW/LEN1
WR/DS/SDI/LEN0
RDY/ACK/SDO
INT
TCLK2
TPOS2/TDATA2
TNEG2/UBS2
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
LOS2
TCLK3
TPOS3/TDATA3
37
3839414243
40
RCLK0
TNEG0/USB0
TPOS0/TDATA0
RPOS0/RDATA0
47
444546
TV+0
LOS0
RNEG0/BPV0
MUX/BITSEN0
484950
TTIP0
RTIP0
TGND0
TRING0
525354
51
TGND1
TRING1
RRING0
TV+1
TTIP1
5556575859
TV+2
RTIP1
RRING1
TTIP2
61
60
RTIP2
TGND2
TRING2
RRING2
626364
TGND3
TRING3
TTIP3
65
TV+3
66
67
RTIP3
RRING3
6869707172
LOS3
RCLK3
RNEG3/RBPV3
RPOS3/RDATA3
TNEG3/UBS3
Figure 1. CS61884 144-Pin Outs
DS485PP4 7
2. PINOUT - FBGA
CS61884
1234567891011121314
G
4
4
5
5
TCK
RPOS
TPOS
RPOS
TPOS
CLKE
CBLSEL
RCLK
A
TCLK
B
RCLK
C
TCLK
D
E
TXOE
F
VCCIO
4
4
5
5
TDO
RNEG
TNEG
RNEG
TNEG
TRST
4
4
5
5
LOS
TDI
TVCC
TVCC
TVCC
TVCC
5
GNDIO
4
4
5
5
LOS
4
TMS
TRING
4
TTIP
4
TRING
5
TTIP
5
TGND
4
TGND
4
TGND
5
TGND
5
RTIP
RRING
RTIP
RRING
RTIP
4
4
5
5
7
RRING
7
RTIP
6
RRING
6
CS61884
TGND
7
TGND
7
TGND
6
TGND
6
TRING
TTIP
TRING
TTIP
TVCC
7
TVCC
7
TVCC
6
TVCC
6
GNDIO
7
6
6
LOS
7
A4
RNEG
7
TNEG
RNEG
TNEG
LOS
A3
A0
RPOS
7
TPOS
7
RPOS
6
TPOS
6
MODE
6
LOOP
RCLK
7
TCLK
7
RCLK
6
TCLK
6
MCLK
A2
A1
VCCIO
0
A
7
B
7
C
6
D
6
E
F
G
160 FBGA
RGND
INTL
ALE
LOS
2
CS
LOS
1
3
(Bottom View)
WR
REF
RD
INT
RV1+
H
J
RDY
K
RGND
0
LOOP
3
LOS
0
LOOP
1
LOOP
4
LOS
1
LOOP
2
LOOP
5
MUX
RV0+
LOOP
6
LOOP
7
H
J
K
TVCC
2
TVCC
2
TVCC
3
TVCC
3
TTIP
2
TRING
2
TTIP
3
TRING
3
TGND
2
TGND
2
TGND
3
TGND
3
RRING
2
2
RRING
3
3
2
RTIP
2
3
RTIP
3
RRING
1
RTIP
1
RRING
0
RTIP
0
TGND
1
TGND
1
TGND
0
TGND
0
TTIP
1
TRING
1
TTIP
0
TRING
0
TVCC
1
TVCC
1
TVCC
0
TVCC
0
TNEG
1
RNEG
1
TNEG
0
RNEG
0
TPOS
1
RPOS
1
TPOS
0
RPOS
0
TCLK
1
RCLK
1
TCLK
0
RCLK
0
L
M
N
P
M
TCLK
L
RCLK
TCLK
N
RCLK
P
TPOS
2
RPOS
2
TPOS
3
RPOS
3
TNEG
2
RNEG
2
TNEG
3
RNEG
3
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Figure 2. CS61884 160-Ball FBGA Pin Outs
8 DS485PP4
3. PIN DESCRIPTIONS
3.1 Power Supplies
SYMBOL LQFP FBGA TYPE DESCRIPTION
CS61884
17
VCCIO
GNDIO 18
RV0+
RV1+
RGND0
RGND1
TV+0 44 N4, P4 Power Supply, Transmit Driver 0
TGND0 47 N6, P6 Ground, Transmit Driver 0
TV+1 53 L4, M4 Power Supply, Transmit Driver 1
TGND1 50 L6, M6 Ground, Transmit Driver 1
TV+2 56 L11
TGND2 59 L9, M9 Ground, Transmit Driver 2
TV+3 65 N11
92
91
19
90
20
89
G1
G14
G4
G11
H1
H14
H4
H11
M11
P11
Power Supply, Digital Interface: Power supply for digital
interface pins; typically 3.3V.
Ground, Digital Interface:
Power supply ground for the digital interface; typically 0 Volts
Power Supply, Core Circuitry: Power supply for all sub-circuits except the transmit driver; typically +3.3 Volts
Ground, Core Circuitry:
Ground for sub-circuits except the TX driver; typically 0 Volts
Power supply for transmit driver 0; typically +3.3 Volts
Power supply ground for transmit driver 0; typically 0 Volts
Power Supply, Transmit Driver 2
Power Supply, Transmit Driver 3
TGND3 62 N9, P9 Ground, Transmit Driver 3
TV +4 116 A11
B11
TGND4 119 A9, B9 Ground, Transmit Driver 4
TV+5 125 C11
D11
TGND5 122 C9,
D9
TV+6 128 C4,
D4
TGND6 131 C6,
D6
TV+7 137 A4, B4 Power Supply, Transmit Driver 7
TGND7 134 A6, B6 Ground, Transmit Driver 7
DS485PP4 9
Power Supply, Transmit Driver 4
Power Supply, Transmit Driver 5
Ground, Transmit Driver 5
Power Supply, Transmit Driver 6
Ground, Transmit Driver 6
3.2 Control
SYMBOL LQFP FBGA TYPE DESCRIPTION
MCLK 10 E1 I
MODE 11 E2 I
CS61884
Master Clock Input
This pin is a free running reference clock that should be
either 1.544 MHz for T1/J1 or 2.048 MHz for E1 operation.
This timing reference is used as follows:
- Timing reference for the clock recovery and jitter attenuation circuitry.
- RCLK reference during Loss of Signal (LOS) conditions
- Transmit clock reference during Transmit all Ones (TAOS)
condition
- Wait state timing for microprocessor interface
- When this pin is held “High”, the PLL clock recovery circuit is disabled. In this mode, the CS61884 receivers
function as simple data slicers.
- When this pin is held “Low”, the receiver paths are powered down and the output pins RCLK, RPOS, and RNEG
are High-Z.
Mode Select
This pin is used to select whether the CS61884 operates in
Serial host, Parallel host or Hardware mode.
Host Mode
serial or a parallel microprocessor interface (Refer to HOST
MODE (See Section 13 on page 32).
Hardware Mode
and the device control/status are provided through the pins
on the device.
- The CS61884 is controlled through either a
- The microprocessor interface is disabled
Table 1. Operation Mode Selection
Pin State OPERATING Mode
LOW Hardware Mode
HIGH Parallel Host Mode
VCCIO/2 Serial Host Mode
NOTE: For serial host mode connect this pin to a resistor
divider consisting of two 10KΩ resistors between
VCCIO and GNDIO.
10 DS485PP4
SYMBOL LQFP FBGA TYPE DESCRIPTION
Multiplexed Interface/Bits Clock Select
MUX/BITSEN0 43 K2 I
Host Mode
face for multiplexed or non-multiplexed operation.
Hardware mode
a G.703 BITS Clock recovery channel (Refer to BUILDING
INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE
(See Section 8 on page 23). Channel 1 through 7 are not
affected by this pin during hardware mode. During host
mode the G.703 BITS Clock recovery function is enabled by
the Bits Clock Enable Register (1Eh) (See Section 14.31
on page 41).
-This pin configures the microprocessor inter-
- This pin is used to enable channel 0 as
Table 2. Mux/Bits Clock Selection
Pin State Parallel Host Mode Hardware Mode
HIGH multiplexed BITS Clock ON
LOW non multiplexed BITS Clock OFF
NOTE: The MUX pin only controls the BITS Clock function in
Hardware Mode
CS61884
INT
RDY/ACK
82 K13 O
/SDO 83 K14 O
Interrupt Output
This active low output signals the host processor when one
of the CS61884’s internal status register bits has changed
state. When the status register is read, the interrupt is
cleared. The various status changes that would force INT
active are maskable via internal interrupt enable registers.
NOTE: This pin is an open drain output and requires a 10 kΩ
pull-up resistor.
Data Transfer Acknowledge/Ready/Serial Data Output
IntelParallelHostMode
access, RDY is asserted “Low” to acknowledge that the device has been accessed. An asserted “High” acknowledges
that data has been written or read. Upon completion of the
bus cycle, this pin High-Z.
Motorola Parallel Host Mode
operation this pin “ACK
data on the bus is valid. An asserted “Low” on this pin during a write operation acknowledges that a data transfer to
the addressed register has been accepted. Upon completion of the bus cycle, this pin High-Z.
NOTE: Wait state generation via RDY/ACK
RZ mode (No Clock Recovery).
Serial Host Mode
configured for serial bus operation, “SDO” is used as a serial data output. This pin is forced into a high impedance
state during a serial write access. The CLKE pin controls
whether SDO is valid on the rising or falling edge of SCLK.
Upon completion of the bus cycle, this pin High-Z.
Hardware Mode
open.
- When the microprocessor interface is
- This pin is not used and should be left
- During a read or write register
- During a data bus read
” is asserted “High” to indicate that
is disabled in
DS485PP4 11
SYMBOL LQFP FBGA TYPE DESCRIPTION
Data Strobe/ Write Enable/Serial Data/Line Length Input
WR/DS/SDI/LEN0 84 J14 I
RD
/RW/LEN1 85 J13 I
IntelParallelHostMode
write enable.
Motorola Parallel Host Mode
a data strobe input.
Serial Host Mode
data input.
Hardware Mode
pulse shapes for both E1 and T1/J1 modes. This pin also
selects which mode is used E1 or T1/J1 (Refer to Ta b le 5
on page 25).
Read/Write/ Read Enable/Line Length Input
IntelParallelHostMode
read enable.
Motorola Parallel Host Mode
the read/write input signal.
Hardware Mode
pulse shapes for both E1 and T1/J1 modes. This pin also
selects which mode is used E1 or T1/J1 (Refer to Ta b le 5
on page 25).
- This pin “SDI” functions as the serial
- As LEN0, this pin controls the transmit
- As LEN1, this pin controls the transmit
- This pin “WR” functions as a
- This pin “RD” functions as a
CS61884
- This pin “DS“ functions as
- This pin “R/W” functions as
ALE/AS
CS
/SCLK/LEN2 86 J12 I
/JASEL 87 J11 I
Address Latch Enable/Serial Clock/Address Strobe/Line
Length Input
IntelParallelHostMode
Address Latch Enable when configured for multiplexed address/data operation.
Motorola Parallel Host Mode
the active “low” address strobe when configured for multiplexed address/data operation.
Serial Host Mode
used for data I/O on SDI and SDO.
Hardware Mode
pulse shapes for both E1 and T1/J1 modes. This pin also
selects which mode is used E1 or T1/J1 (Refer to Ta b le 5
on page 25).
Chip Select Input/Jitter Attenuator Select
Host Mode
cesses to the microprocessor interface in either serial or
parallel mode.
Hardware Mode
Attenuator.
- This active low input is used to enable ac-
Pin State Jitter Attenuation Position
LOW Transmit Path
HIGH Receive Path
OPEN Disabled
- This pin “SCLK” is the serial clock
- As LEN2, this pin controls the transmit
- This pin controls the position of the Jitter
- This pin “ALE” functions as the
- This pin “AS” functions as
12 DS485PP4
SYMBOL LQFP FBGA TYPE DESCRIPTION
Motorola/Intel/Coder Mode Select Input
INTL/MOT/CODEN 88 H12 I
TXOE 114 E14 I
Parallel Host Mode
cessor interface is configured for operation with Motorola
processors. When this pin is “High” the microprocessor interface is configured for operation with Intel processors.
Hardware Mode
polar operation, this pin, CODEN
encoding/decoding function. When CODEN
B8ZS/HDB3 encoders/decoders are enabled for T1/J1 or
E1 operation respectively. When CODEN
coding/decoding is activated. This is done for all eight
channels.
Transmitter Output Enable
Host mode
dividual drivers can be set to a high impedance state via
the Output Disable Register (12h) (See Section 14.19 on
page 39).
Hardware Mode
TX drivers are forced into a high impedance state. All other
internal circuitry remains active.
- Operates the same as in hardware mode. In-
- When this pin is “Low” the micropro-
- When the CS61884 is configured for uni-
- When TXOE pin is asserted Low, all the
CS61884
, configures the line
is low,
is high, AMI en-
CLKE 115 E13 I
Clock Edge Select
In clock/data recovery mode, setting CLKE “high” will cause
RPOS/RNEG to be valid on the falling edge of RCLK and
SDOtobevalidontherisingedgeofSCLK.WhenCLKEis
set “low”, RPOS/RNEG is valid on the rising edge of RCLK,
and SDO is valid on the falling edge of SCLK. When the
part is operated in data recovery mode, the RPOS/RNEG
output polarity is active “high” when CLKE is set “high” and
active “low” when CLKE is set “low”.
DS485PP4 13
3.3 Address Inputs/Loopbacks
SYMBOL LQFP FBGA TYPE DESCRIPTION
A4 12 F4 I
A3
A2
A1
A0
13
14
15
16
F3
F2
F1
G3
Address Selector Input
Parallel Host Mode
mode operation, this pin function as the address 4 input for
the parallel interface.
Hardware Mode
Non-Intrusive Monitoring/Address Selector Inputs
Parallel Host Mode
mode operation, these pins function as address A[3:0] inputs for the parallel interface.
Hardware Mode
tion during non-intrusive monitoring. In non-intrusive
I
monitoring mode, receiver 0’s input is internally connected
to the transmit or receive ports on one of the other 7 chan-
I
nels. The recovered clock and data from the selected port
are output on RPOS0/RNEG0 and RCLK0. Additionally, the
I
data from the selected port can be output on
TTIP0/TRING0 by activating the remote loopback function
I
for channel 0 (Refer to Performance Monitor Register
(0Bh) (See Section 14.12 on page 36).
- During non-multiplexed parallel host
- The A4 pin must be tied low at all times.
- During non-multiplexed parallel host
- The A[3:0] pins are used for port selec-
CS61884
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
21
22
23
24
25
26
27
28
G2
H3
H2
J4
J3
J2
J1
K1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Loopback Mode Selector/Parallel Data Input/Output
Parallel Host Mode
terface mode, these pins function as the bi-directional 8-bit
data port. When operating in multiplexed microprocessor interface mode, these pins function as the address and data
inputs/outputs.
Hardware Mode
- No Loopback - The CS61884 is in a normal operating
state when LOOP is left open (unconnected) or tied to
VCCIO/2.
- Local Loopback - When LOOP is tied High, data transmitted on TTIP and TRING is looped back into the analog
input of the corresponding channel’s receiver and output on
RPOS and RNEG. Input Data present on RTIP and RRING
is ignored.
- Remote Loopback - When LOOP is tied Low the recovered clock and data received on RTIP and RRING is looped
back for transmission on TTIP and TRING. Data on TPOS
and TNEG is ignored.
- In non-multiplexed microprocessor in-
14 DS485PP4
3.4 Cable Select
SYMBOL LQFP FBGA TYPE DESCRIPTION
CS61884
Cable Impedance Select
Host Mode
normal operation.
Hardware Mode
LEN control pins (Refer to Ta bl e 5 , “Hardware Mode Line
Length Configuration Selection,” on page 25)tosettheline
impedance for all eight receivers and transmitters. This pin
also selects whether or not all eight receivers use an internal or external line matching network (Refer to the Table
below for proper settings).
- The input voltage to this pin does not effect
- Thispinisusedincombinationwiththe
3.5
CBLSEL 93 G13 I
E1/T1/J1 CBLSEL Transmitters Receivers
NOTE: Refer to Figure 17 on page 51 and Figure 18 on
Table 3. Cable Impedance Selection
T1/J1 No Connect 100 Ω Internal Internal
T1/J1 HIGH 100 Ω Internal Internal
T1/J1 LOW 100 Ω Internal External
E1 No Connect 120 Ω Internal Inter or Ext
E1 HIGH 75 Ω Internal Internal
E1 LOW 75 Ω Internal External
page 52 for appropriate external line matching com-
ponents. All transmitters use internal matching networks.
Status
SYMBOL LQFP FBGA TYPE DESCRIPTION
Loss of Signal Output
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
42
35
75
68
113
106
3
140
K4
K3
K12
K11
E11
E12
E3
E4
O
O
The LOS output pins can be configured to indicate a loss of
O
signal (LOS) state that is compliant to either T1.231, ITU
O
G.775 or ETSI 300 233. These pins are asserted “High” to
O
indicate LOS. The LOS output returns low when an input
O
signal is present for the time period dictated by the associ-
O
ated specification (Refer to Loss-of-Signal (LOS) (See
O
Section 10.5 on page 27)).
DS485PP4 15
3.6 Digital Rx/Tx Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION
TCLK0 36 N1 I
CS61884
Transmit Clock Input Port 0
- When TCLK is active, the TPOS and TNEG pins function
as NRZ inputs that are sampled on the falling edge of
TCLK.
- If MCLK is active, TAOS will be generated when TCLK is
held High for 16 MCLK cycles.
NOTE: MCLK is used as the timing reference during TAOS
and must have the appropriate stability.
-IfTCLKisheldHighintheabsenceofMCLK,theTPOS
and TNEG inputs function as RZ inputs. In this mode, the
transmit pulse width is set by the pulse-width of the signal
input on TPOS and TNEG. To enter this mode, TCLK must
be held high for at least 12 µS.
- If TCLK is held Low, the output drivers enter a low-power,
high impedance state.
Transmit Positive Pulse/Transmit Data Input Port 0
Transmit Negative Pulse/Unipolar-Bipolar Select Port 0
The function of the TPOS/TDATA and TNEG/UBS inputs
are determined by whether Unipolar, Bipolar or RZ input
mode has been selected.
Bipolar Mode
TNEG are sampled on the falling edge of TCLK and transmitted onto the line at TTIP and TRING respectively. A
“High” input on TPOS results in transmission of a positive
pulse; a “High” input on TNEG results in a transmission of a
negative pulse. The translation of TPOS/TNEG inputs to
TTIP/TRING outputs is as follows:
- In this mode, NRZ data on TPOS and
TPOS0/TDATA0
TNEG0/UBS
16 DS485PP4
37
38
N2
N3
I
I
TPOS TNEG OUTPUT
0 0 Space
1 0 Positive Mark
0 1 Negative Mark
1 1 Space
Unipolar mode
TNEG/UBS “High” for more than 16 TCLK cycles, when
MCLK is present. The falling edge of TCLK samples a unipolar data steam on TPOS/TDATA.
RZ Mode
absence of MCLK. In this mode, the duty cycle of the
TPOS and TNEG inputs determine the pulse width of the
output signal on TTIP and TRING.
- Unipolar mode is activated by holding
- To activate RZ mode tie TCLK “High” with the
SYMBOL LQFP FBGA TYPE DESCRIPTION
Receive Clock Output Port 0
- When MCLK is active, this pin outputs the recovered clock
from the signal input on RTIP and RRING. In the event of
LOS, the RCLK output transitions from the recovered clock
RCLK0 39 P1 O
RPOS0/RDATA0
RNEG0/BPV0
40
41
P2
P3
to MCLK.
- If MCLK is held “High”, the clock recovery circuitry is disabled and the RCLK output is driven by the XOR of RNEG
and RPOS.
- If MCLK is held “Low”, this output is in a high-impedance
state.
Receive Positive Pulse/ Receive Data Output Port 0
Receive Negative Pulse/Bipolar Violation Output Port 0
The function of the RPOS/RDATA and RNEG/BPV outputs
are determined by whether Unipolar, Bipolar, or RZ input
mode has been selected. During LOS, the RPOS/RNEG
outputs will remain active.
NOTE: The RPOS/RNEG outputs can be High-Z by holding
MCLK Low.
Bipolar Output Mode
O
tion, NRZ Data is recovered from RTIP/RRING and output
on RPOS/RNEG. A high signal on RPOS or RNEG corre-
O
spond to the receipt of a positive or negative pulse on
RTIP/RRING respectively. The RPOS/RNEG outputs are
valid on the falling or rising edge of RCLK as configured by
CLKE.
Unipolar Output Mode
the recovered data is output on RDATA. The decoder signals bipolar Violations on the RNEG/BPV pin.
RZ Output Mode
output RZ data recovered by slicing the signal present on
RTIP/RRING. A positive pulse on RTIP with respect to
RRING generates a logic 1 on RPOS; a positive pulse on
RRING with respect to RTIP generates a logic 1 on RNEG.
The polarity of the output on RPOS/RNEG is selectable using the CLKE pin. In this mode, external circuitry is used to
recover clock from the received signal.
- When configured for Bipolar opera-
- When unipolar mode is activated,
- In this mode, the RPOS/RNEG pins
CS61884
TCLK1 29 L1 I Transmit Clock Input Port 1
TPOS1/TDATA1 30 L2 I Transmit Positive Pulse/Transmit Data Input Port 1
TNEG1/UBS1 31 L3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 1
RCLK1 32 M1 O Receive Clock Output Port 1
RPOS1/RDATA1 33 M2 O Receive Positive Pulse/ Receive Data Output Port 1
RNEG1/BPV1 34 M3 O Receive Negative Pulse/Bipolar Violation Output Port 1
TCLK2 81 L14 I Transmit Clock Input Port 2
TPOS2/TDATA2 80 L13 I Transmit Positive Pulse/Transmit Data Input Port 2
TNEG2/UBS2 79 L12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 2
DS485PP4 17
CS61884
SYMBOL LQFP FBGA TYPE DESCRIPTION
RCLK2 78 M14 O Receive Clock Output Port 2
RPOS2/RDATA2 77 M13 O Receive Positive Pulse/ Receive Data Output Port 2
RNEG2/BPV2 76 M12 O Receive Negative Pulse/Bipolar Violation Output Port 2
TCLK3 74 N14 I Transmit Clock Input Port 3
TPOS3/TDATA3 73 N13 I Transmit Positive Pulse/Transmit Data Input Port 3
TNEG3/UBS3 72 N12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 3
RCLK3 71 P14 O Receive Clock Output Port 3
RPOS3/RDATA3 70 P13 O Receive Positive Pulse/ Receive Data Output Port 3
RNEG3/BPV3 69 P12 O Receive Negative Pulse/Bipolar Violation Output Port 3
TCLK4 107 B14 I Transmit Clock Input Port 4
TPOS4/TDATA4 108 B13 I Transmit Positive Pulse/Transmit Data Input Port 4
TNEG4/UBS4 109 B12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 4
RCLK4 110 A14 O Receive Clock Output Port 4
RPOS4/RDATA4 111 A13 O Receive Positive Pulse/ Receive Data Output Port 4
RNEG4/BPV4 11 2 A12 O Receive Negative Pulse/Bipolar Violation Output Port 4
TCLK5 100 D14 I Transmit Clock Input Port 5
TPOS5/TDATA5 101 D13 I Transmit Positive Pulse/Transmit Data Input Port 5
TNEG5/UBS5 102 D12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 5
RCLK5 103 C14 O Receive Clock Output Port 5
RPOS5/RDATA5 104 C13 O Receive Positive Pulse/ Receive Data Output Port 5
RNEG5/BPV5 105 C12 O Receive Negative Pulse/Bipolar Violation Output Port 5
TCLK6 9 D1 I Transmit Clock Input Port 6
TPOS6/TDATA6 8 D2 I Transmit Positive Pulse/Transmit Data Input Port 6
TNEG6/UBS6 7 D3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 6
RCLK6 6 C1 O Receive Clock Output Port 6
RPOS6/RDATA6 5 C2 O Receive Positive Pulse/ Receive Data Output Port 6
RNEG6/BPV6 4 C3 O Receive Negative Pulse/Bipolar Violation Output Port 6
TCLK7 2 B1 I Transmit Clock Input Port 7
TPOS7/TDATA7 1 B2 I Transmit Positive Pulse/Transmit Data Input Port 7
TNEG7/UBS7 144 B3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 7
18 DS485PP4
CS61884
SYMBOL LQFP FBGA TYPE DESCRIPTION
RCLK7 143 A1 O Receive Clock Output Port 7
RPOS7/RDATA7 142 A2 O Receive Positive Pulse/ Receive Data Output Port 7
RNEG7/BPV7 141 A3 O Receive Negative Pulse/Bipolar Violation Output Port 7
3.7 Analog RX/TX Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION
Transmit Tip Output Port 0
Transmit Ring Output Port 0
TTIP and TRING pins are the differential outputs of the
transmit driver. The driver internally matches impedances
for E1 75 Ω, E1 120 Ω and T1/J1 100 Ω lines requiring only
TTIP0
TRING0
45
46
N5
P5
a1:2transformer.TheCBLSELpinisusedtoselectthe
O
appropriate line matching impedance only in “Hardware”
mode. In host mode, the appropriate line matching imped-
O
ance is selected by the Line Length Data Register (11h)
(See Section 14.18 on page 39).
NOTE: TTIP and TRING are forced to a high impedance state
when the TCLK pin is “Low” for over 12µSorthe
TXOE pin is forced “Low”.
Receive Tip Input Port 0
Receive Ring Input Port 0
RTIP and RRING are the differential line inputs to the receiver. The receiver uses either Internal Line Impedance or
External Line Impedance modes to match the line imped-
RTIP0
RRING0
TTIP1 52 L5 O Transmit Tip Output Port 1
48
49
P7
N7
ances for E1 75Ω, E1 120Ω or T1/J1 100Ω modes.
I
Internal Line Impedance Mode
same external resistors to match the line impedance (Refer
I
to Figure 17 on page 51).
External Line Impedance Mode
ent external resistors to match the line impedance (Refer to
Figure 18 on page 52).
- In host mode, the appropriate line impedance is selected
by the Line Length Data Register (11h) (See Section
14.18 on page 39).
- In hardware mode, the CBLSEL pin in combination with
the LEN pins select the appropriate line impedance. (Refer
to Table 3 on page 15 for proper line impedance settings).
NOTE: Data and clock recovered from the signal input on
these pins are output via RCLK, RPOS, and RNEG.
- The receiver uses the
- The receiver uses differ-
TRING1 51 M5 O Transmit Ring Output Port 1
RTIP1 55 M7 I Receive Tip Input Port 1
RRING1 54 L7 I Receive Ring Input Port 1
DS485PP4 19
SYMBOL LQFP FBGA TYPE DESCRIPTION
TTIP2 57 L10 O Transmit Tip Output Port 2
TRING2 58 M10 O Transmit Ring Output Port 2
RTIP2 60 M8 I Receive Tip Input Port 2
RRING2 61 L8 I Receive Ring Input Port 2
TTIP3 64 N10 O Transmit Tip Output Port 3
TRING3 63 P10 O Transmit Ring Output Port 3
RTIP3 67 P8 I Receive Tip Input Port 3
RRING3 66 N8 I Receive Ring Input Port 3
TTIP4 117 B10 O Transmit Tip Output Port 4
TRING4 118 A10 O Transmit Ring Output Port 4
RTIP4 120 A8 I Receive Tip Input Port 4
RRING4 121 B8 I Receive Ring Input Port 4
CS61884
TTIP5 124 D10 O Transmit Tip Output Port 5
TRING5 123 C10 O Transmit Ring Output Port 5
RTIP5 127 C8 I Receive Tip Input Port 5
RRING5 126 D8 I Receive Ring Input Port 5
TTIP6 129 D5 O Transmit Tip Output Port 6
TRING6 130 C5 O Transmit Ring Output Port 6
RTIP6 132 C7 I Receive Tip Input Port 6
RRING6 133 D7 I Receive Ring Input Port 6
TTIP7 136 B5 O Transmit Tip Output Port 7
TRING7 135 A5 O Transmit Ring Output Port 7
RTIP7 139 A7 I Receive Tip Input Port 7
RRING7 138 B7 I Receive Ring Input Port 7
20 DS485PP4
3.8 JTAG Test Interface
SYMBOL LQFP FBGA TYPE DESCRIPTION
TRST
TMS 96 F11 I
TCK 97 F14 I
TDO 98 F13 O
95 G12 I
CS61884
JTAG Reset
This active Low input resets the JTAG controller. This input
is pulled up internally and may be left as a NC when not
used.
JTAG Test Mode Select Input
This input enables the JTAG serial port when active High.
This input is sampled on the rising edge of TCK. This input
is pulled up internally and may be left as a NC when not
used.
JTAG Test Clock
Data on TDI is valid on the rising edge of TCK. Data on
TDO is valid on the falling edge of TCK. When TCK is
stopped high or low, the contents of all JTAG registers remain unchanged. Tie pin low through a 10 KΩ resistor
when not used.
JTAG Test Data Output
JTAG test data is shifted out of the device on this pin. Data
is output on the falling edge of TCK. Leave as NC when not
used.
TDI 99 F12 I
3.9 Miscellaneous
SYMBOL LQFP FBGA TYPE DESCRIPTION
REF 94 H13 I Reference Input
JTAG Test Data Input
JTAG test data is shifted into the device using this pin. The
pin is sampled on the rising edge of TCK. TDI is pulled up
internally and may be left as a NC when not used.
This pin must be tied to ground through 13.3 KΩ 1% resistor. This pin is used to set the internal current level.
DS485PP4 21
CS61884
4. OPERATION
The CS61884 is a full featured line interface unit
for up to eight E1/T1/J1 lines. The device provides
an interface to twisted pair or co-axial media. A
matched impedance technique is employed that reduces power and eliminates the need for matching
resistors. As a result, the device can interface directly to the line through a transformer without the
need for matching resistors on the transmit side.
The receive side uses the same resistor values for
all E1/T1/J1 settings.
5. POWER-UP
On power-up, the device is held in a static state until the power supply achieves approximately 70%
of the power supply voltage. Once the power supply threshold is passed, the analog circuitry is calibrated, the control registers are reset to their default
settings, and the various internal state machines are
reset. The reset/calibration process completes in
about 30 ms.
6. MASTER CLOCK
7. G.772 MONITORING
The receive path of channel zero of the CS61884
can be used to monitor the receive or transmit paths
of any of the other channels. The signal to be monitored is multiplexed to channel zero through the
G.772 Multiplexer. The multiplexer and channel
zero then form a G.772 compliant digital Protected
Monitoring Point (PMP). When the PMP is connected to the channel, the attenuation in the signal path is
negligible across the signal band. The signal can be
observed using RPOS, RNEG, and RCLK of channelzeroorbyputtingchannelzeroinremoteloopback, the signal can be observed on TTIP and
TRING of channel zero.
The G.772 monitoring function is available during
both host mode and hardware mode operation. In
host modes, individual channels are selected for
monitoring via the Performance Monitor Regis-
ter (0Bh) (See Section 14.12 on page 36)). In hard-
ware mode, individual channels are selected
through the A3:A0 pins (Refer to Table 4 below for
address settings).
The CS61884 requires a 2.048 MHz or 1.544 MHz
reference clock with a minimum accuracy of ±100
ppm. This clock may be supplied from internal system timing or a CMOS crystal oscillator and input
to the MCLK pin.
The receiver uses MCLK as a reference for clock
recovery, jitter attenuation, and the generation of
RCLK during LOS. The transmitter uses MCLK as
the transmit timing reference during a blue alarm
transmit all ones condition. In addition, MCLK
provides the reference timing for wait state generation.
In systems with a jittered transmit clock, MCLK
should not be tied to the transmit clock, a separate
crystal oscillator should drive the reference clock
input. Any jitter present on the reference clock will
not be filtered by the jitter attenuator and can cause
the CS61884 to operate incorrectly.
Table 4. G.772 Address Selection
Address [A3:A0] Channel Selection
0000 Monitoring Disabled
0001 Receiver Channel # 1
0010 Receiver Channel # 2
0011 Receiver Channel # 3
0100 Receiver Channel # 4
0101 Receiver Channel # 5
0110 Receiver Channel # 6
0111 Receiver Channel # 7
1000 Monitoring Disabled
1001 Transmitter Channel # 1
1010 Transmitter Channel # 2
1011 Transmitter Channel # 3
1100 Transmitter Channel # 4
1101 Transmitter Channel # 5
1110 Transmitter Channel # 6
1111 Tr a n smitte r Chan n el # 7
NOTE: In hardware mode the A4 pin must be tied low
at all times.
22 DS485PP4
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