Cirrus Logic CS61880 User Manual
Octal E1 Line Interface Unit
CS61880
Features
Octal E 1 Short-haul Line Int erface Unit
Low Power
No External Component Changes for 120 Ω / 75 Ω
Operation
Pulse Shapes can be customized by the user
Internal AMI, or HDB3 Encoding/Decoding
LOS Detecti on pe r ITU G.775 or ETS I 300- 233
G.772 Non-Intrusive Monitoring
G.703 BI T S Clock Recovery
Cryst al-less Jit ter Attenuation
Serial/Parallel Microprocessor Control Interfaces
Tra nsmitter Short Circui t Current Limiter ( <50 mA)
TX Drivers with Fast High-Z and Power Down
JT AG Boundary Scan compliant to IEE E 1149.1
144-Pin L QF P or 160-Pin FBGA Package
ORDERING INFORMATION
CS61880-IQ 144-pin LQFP
CS61880-IB 160-pin FBGA
Description
The CS61880 is a full -featured Octal E 1 short-haul LIU
that supports 2.048 Mbps data transmission for both E1
75 Ω and E1 120 Ω applications. Each channel provides
crystal-less jitter attenuation that complies with the most
stringent standards. Each channel also provides internal
AMI/HDB3 encoding/decoding. To support enhanced
system diagnostics, cha nnel z ero can be configured for
G.772 non-intrusive monitoring of any of the other 7
channels’ receive or transmit paths.
The CS61880 makes use of ultra low power matched impedance transmitters and receivers to reduce power
beyond that achieved by traditional driver designs. By
achieving a more precise line match, this technique also
provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the
external component count. All transmitters have controls
for independent power down and High-Z.
Each receiver provides reliable data recovery wi th over
12 dB of cable atte nuation. The receiver also incorpo rates LOS detection compliant to the most recent
specifications.
LOS
RCLK
RPOS
RNEG
TCLK
TPOS
TNEG
JTAG
Serial
Port
Decoder
Remote Loopback
Jitter
Attenuator
Encoder
0
1
7
JTAG Interface
Preliminary Product Information
http://www.cirrus.com
LOS
Digital Loopback
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2003
Clock
Recovery
Transmit
Control
(All Rights Reserved)
Recovery
Pulse
Shaper
Host Interface
Data
Receiver
Driver
Analog Loopback
G.772 Monitor
RTIP
RRING
TTIP
TRING
Host
Serial/Parallel
Port
DS450PP3
JUL ‘03
1
TABLE OF CONTENTS
1. PIN OUT - 144-PIN LQFP PACKAGE ................................................................................... 7
2. PIN OUT - 160-BALL FBGA PACKAGE ..................................................................................8
3. PIN DESCRIPTIONS ................................................................................................................9
3.1 Power Supplies ........................... .. .......... .. ....... .......... .. ....... ....... ..... ....... ..... ....... .. ..............9
3.2 Control ..................... .......... ......... ................. ......... .......... ................................. ................10
3.3 Address Inputs/Loopbacks ...............................................................................................14
3.4 Cable Select ............ .......... ................................. ......... .......... ................ .......... ......... .......15
3.5 Status ....................... .......... ......... ................. ......... .......... ................ .......... ......... ..............15
3.6 Digital Rx/Tx Data I/O ......................................................................................................16
3.7 Analog RX/T X Dat a I/ O ........ ......... .................................. ......... .......... ................ .......... ....19
3.8 JTAG Test Inter fa ce ............... ................. ......... .......... ................ .......... ......... ...................21
3.9 Miscellaneous .................................................................................................................. 21
4. OPERATION ...........................................................................................................................22
5. POWER-UP .............................................................................................................................22
6. MASTER CLOCK ...................................................................................................................22
7. G.772 MONITORING ..............................................................................................................22
8. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE ..................................23
9. TRANSMITTER .......................................................................................................................24
9.1 Bipolar Mo d e .......... ......... .......... ................ .......... ......... ................. ......... .......... ................24
9.2 Unipolar Mode .................................................................................................................. 24
9.3 RZ Mode ............................................................... ....... ....... ..... ....... ....... ....... ..... ....... .......25
9.4 Transmit te r Po wer down / High - Z .......... ......... .................................................. ......... .......25
9.5 Transmit All Ones (TAOS) ...............................................................................................25
9.6 Automatic TAOS ............. .......... ................ .......... ......... ................. ......... ........................ ..25
9.7 Driver Failure Monitor ......................................................................................................25
9.8 Driver Short Circuit Protection .........................................................................................25
CS61880
Contacting Cirrus Logic Support
For all product quest ions and inquir ies contact a Cirr us Logi c Sales Representativ e.
To find the one nearest to you go to:
IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its
subsidiaries (“Cirrus”) believe that t he information contained in this document is accurate and reliable. However , the infor mation i s subj ect to change without
notice and is provi ded “AS IS” without warranty of any kind (express or implied) . Customers ar e advised to obtain t he lates t versi on of relevant informati on to
verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus
for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of
third parti es. This document is the property of Cirrus and by furnishing th is information, Cirrus grants no license, express or implied under any patents, mask
work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of
Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for
resale.
An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be
obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign
Trade Law and is to be exported or taken out of the PRC.
CERTAIN APPLI CATI ONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTI AL RI SKS OF DEATH, PERSONAL I NJURY, OR SEVERE
PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED
FOR USE IN AIRCRA FT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY I MPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS
OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE
SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF
THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL A PPLICATI ONS, CUSTOMER
AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, IT S OFFICERS, DIRECTORS, EM PLO YEES, DISTRIBUTORS AND OTHER AGENTS FROM
ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.
Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Intel is a registered trademark of Intel Corporation.
Motorola is a registered trademark of Motorola, Inc.
http://w ww.cirrus.com/
2 DS450PP3
CS61880
10. RECEIVER ........................... .......... ......... ................................. .......... ......... ..........................26
10.1 Bipolar Output Mode ............................................................................ ....... ....... ............26
10.2 Unipolar Output Mode ................................................................................................... 26
10.3 RZ Output Mode .............................. ....... ....... ............ ..... ....... ....... ....... ....... ....... .......... ..26
10.4 Receiver Po we rd own/High-Z ................ ......... .......... ......... ................. ......... .......... .........27
10.5 Loss-of-Signal (LOS) ........... ....... ..... ....... ....... .......... .. ....... ....... ..... ....... ....... ....... ..... .......27
10.6 Alarm Indication Signal (AIS) ......................................................................................... 27
11. JITTER ATTENUATOR ........................................................................................................28
12. OPERATIONAL SUMMARY .................. .............................................................................. 29
12.1 Loopbacks ..................................................................................................................... 29
12.2 Analog Loopback ...........................................................................................................29
12.3 Digital Loopback ...................................................................... ............ ....... ....... ............ 30
12.4 Remote Loopback ..................................................... ....... ....... ..... ....... ....... ....... ............30
13. HOST MODE ........................................................................................................................ 32
13.1 SOFTWARE RESET .... ................. ......... .......... ................ .......... ......... ................. .........32
13.2 Serial Po r t Ope ra tion .. ......... ................. ......... .......... ................ .......... ......... ................. ..32
13.3 Parallel Port Operation ..................................................................................................33
13.4 Register Set ........... ................. ......... .......... ................................. ......... .......... ................34
14. REGISTER DESCRIPTIONS ......... ......... .......... ................ .......... ......... .......... ................ ....... 35
14.1 Revision/IDcode Register (00h) .................................................... ....... ....... ..... ....... ..... ..35
14.2 Analog Loopback Register (01h) ...................................................................................35
14.3 Remote Loopback Register (02h) ..................................................................................35
14.4 TAOS Enable Regi ste r (0 3 h) ............................ ......... .......... ................ .......... ......... ....... 35
14.5 LOS Status Register (04h) ................... ......... .................................. ......... ..................... 35
14.6 DFM Status Regi ste r ( 0 5h) ................... .................................................. ......... .......... .... 35
14.7 LOS Interrupt Enable Register (06h) ................................................. ....... .. ....... ..... .......36
14.8 DFM Interrupt Enable Register (07h) ............................................................................ 36
14.9 LOS Interrupt Status Register (0 8 h) ....... ................. ......... .......... ................ .......... .........36
14.10 DFM Interrupt Status Register (09h) ...........................................................................36
14.11 Software Reset Register (0Ah) .................................................................................... 36
14.12 Performance Monitor Register (0Bh) ........................................................................... 36
14.13 Digital Loopback Reset Register (0Ch) .......................................................................36
14.14 LOS/AIS Mode Enable Register (0Dh) ........................................................................ 37
14.15 Automati c TAOS Register (0Eh) ................ ................. ......... .......... ......... ................. .... 37
14.16 Global Control Register (0F h) ............... ................. ......... .......... ...................................37
14.17 Line Length Channel ID Register (10h) ....................................................................... 38
14.18 Line Length Data Register (11h) .................................................................................38
14.19 Output Disable Register (12h) .....................................................................................38
14.20 AIS Status Register (13h) ............................................................................................ 38
14.21 AIS Interrupt Enable Register (14h) ............................................................................ 39
14.22 AIS Interrupt Status Register (15h) ............................................................................. 39
14.23 AWG Broadcast Register (16h) ...................................................................................39
14.24 AWG Phase Address Register (17h) ...........................................................................39
14.25 AWG Phase Data Register (18h) ................................................................................39
14.26 AWG Enable Register (19h) ........................................................................................ 40
14.27 Reserved Register (1Ah) .............................................................................................40
14.28 Reserved Register (1Bh) .............................................................................................40
14.29 Reserved Register (1Ch) ............................................................................................. 40
14.30 Reserved Register (1Dh) ............................................................................................. 40
14.31 Bits Clock Enable Register (1Eh) ............................................... ....... ....... ..... ....... .......40
14.32 Reserved Register (1Fh) ............................................................................................. 40
14.33 Status Registers ..........................................................................................................40
14.33.1 Interrupt Enable Registers ..............................................................................41
DS450PP3 3
CS61880
14.33.2 Inter r u pt Sta tu s Re g ist e r s ....................... ......... ......... ......................................41
15. ARBITRARY WAVEFORM GENERATOR ...........................................................................42
16. JTAG SUPPORT .................... ................ .......... ......... .......... ................ .......... ......... .............. 43
16.1 TAP Control ler ............................................. .......... ................................. ......... ..............44
16.1.1 JTAG Reset .......................................................................................................44
16.1.2 Test-Logic-Reset ...............................................................................................44
16.1.3 Run-Test-Idle ....................................................................................................44
16.1.4 Select-DR-Scan ................................................................................................44
16.1.5 Capture-DR .......................................................................................................44
16.1.6 Shift-DR .............................................................................................................44
16.1.7 Exit1-DR ............................................................................................................44
16.1.8 Pause-DR ..........................................................................................................45
16.1.9 Exit2-DR ............................................................................................................45
16.1.10 Update-DR ......................................................................................................45
16.1.11 Select-IR-Scan ................................................................................................45
16.1.12 Capture-IR .......................................................................................................45
16.1.13 Shift-IR ............................................................................................................45
16.1.14 Exit1-IR ...........................................................................................................46
16.1.15 Pause-IR .........................................................................................................46
16.1.16 Exit2-IR ...........................................................................................................46
16.1.17 Update-IR ........................................................................................................46
16.2 Instruction Register (IR) .................................................................................................46
16.2.1 EXTEST ............................................................................................................46
16.2.2 SAMPLE/PRELOAD .........................................................................................46
16.2.3 IDCODE ............................................................................................................46
16.2.4 BYPASS ............................................................................................................46
16.3 Device ID Register (IDR) .......... .......... ...........................................................................47
17. BOUNDARY SCAN REGISTER (BSR) ................................................................................47
18. APPLICATIONS ........................ ......... .......... ................................. .......... ......... .....................50
18.1 Transf ormer Specificat ion s ................... ......... .......... ................ .......... ............................52
18.2 Cryst a l Os c illat o r Specifica tions .... .. .. . .... .............. . .. .... . .. .... . .... .. . .... . .. .... . .. .... . .. .... . .... . .. ... 52
18.3 Line Prote c ti o n ................. ................ .......... ................................. ......... .......... ................ 52
19. CHARACTERISTICS AND SPECIFICATIONS .................................................................... 53
19.1 Absolute Maximum Ratings ...........................................................................................53
19.2 Recommended Operating Conditions . .. .. ....... ............ ....... ....... .......... ....... ....... ....... .......53
19.3 Digital Chara cteristics ........ ......... ...................................................................................54
19.4 Transmitter Analog Characteristics ................................................................................54
19.5 Receiver An a log Chara c teristics ......... ................................................. .......... ......... .......5 5
19.6 Jitter Attenuator Characte r istics ..................... .................................. ......... ......... .......... ..56
19.7 Master Clock Switching Characteristics .........................................................................58
19.8 Transmit Switching Characteristics ................................................................................58
19.9 Receive Swi tch i n g Char ac te r istics .................... ......... .......... ......... .................................58
19.10 Switching Characteristics - Serial Port .........................................................................60
19.11 Switching Characteristics - Parallel Port (Multiplexed Mode) .............................. .......61
19.12 Switching Characteristics- Parallel Port (Non-Multiplexed Mode) ...............................64
19.13 Switching Characteristics - JTAG ................... ......... .......... ..........................................67
20. COMPLIANT RECOMMENDATIONS AND SPECIFIC ATIONS ....... ................ .......... .........68
21. 160-BALL FBGA PACKAGE DIMENSIONS ........................... ... .. .. .......................... ............69
22. 144-PIN LQFP PACKAGE DIMENSIONS .......................................................................70
4 DS450PP3
LIST OF FIGURES
Figure 1. CS61880 144-Pin LQFP Package Pin Outs ....................................................................7
Figure 2. CS61880 160-Ball FBGA Package Pin Outs ................................................................... 8
Figure 3. G.703 BITS Clock Mode in NRZ Mode.......................................................................... 23
Figure 4. G.703 BITS Clock Mode in RZ Mode............................................................................. 23
Figure 5. G.703 BITS Clock Mode in Remote Loopback .............................................................. 23
Figure 6. Pulse Ma sk at E1 Inter face......... .......... ......... .................................. ......... ......... ............24
Figure 7. Analog Loopback Block Diagram...................................................................................30
Figure 8. Analog Loopback with TAOS Block Diagram.................................................................30
Figure 9. Digital Loopback Block Diagram................................ ..... ....... ....... ....... ....... ....... ..... .......31
Figure 10. Digital Loopback with TAOS........ ......... ....................................................................... 31
Figure 11. Remote Loopback Block Diagram ..................................................... ..... ....... .. .......... ..31
Figure 12. Serial Read/Write Format (SPOL = 0)......................................................................... 33
Figure 13. Arbitrary Waveform UI.................................................................................................42
Figure 14. Test Acce ss Po r t Arch itecture........... ......... .......... ................................. ......... .......... .... 44
Figure 15. TAP Cont r o lle r Sta te Diag r a m.............. .......... ................ .......... ......... .......... ................45
Figure 16. Internal RX/TX Impedance Matching.................................................................... .......50
Figure 17. Internal TX, External RX Impedance Matching............................................................ 51
Figure 18. Jit te r Tran s fer Chara cteristic vs. G.7 3 6 & TBR 12/13........ ......... .......... ....................... 56
Figure 19. Jitter Tolerance Characteristic vs. G.823..................................................................... 57
Figure 20. Recovered Clock and Data Switching Characteristics................................................. 59
Figure 21. Tran smi t Cloc k and Data Switching Charact e ristics..... ......... .......... ......... .......... .........59
Figure 22. Signal Rise and Fall Characteristics............................................................................ 59
Figure 23. Serial Port Read Timing Diagram................................................................................ 60
Figure 24. Serial Port Write Timing Diagram................................................................................ 60
Figure 25. Parallel Port Timing - Writ e ; In te l® Multiplexed Addre ss / Data Bus Mode .................62
Figure 26. Paral lel Port Timing - Read; Inte l Mul ti p lexed Address / Data Bus Mode....................62
Figure 27. Parallel Port Timing - Write; Motorola® Multiplexed Address / Data Bus Mode .......... 63
Figure 28. Parallel Port Timing - Read; Motorola Multiplexed Address / Data Bus Mode............. 63
Figure 29. Paral lel Port Timing - Write; In te l Non-Multiplexe d Addr e ss / Data Bus Mode.......... ..65
Figure 30. Parallel Port Timing - Read; Intel Non-Multiplexed Address / Data Bus Mode............ 65
Figure 31. Parallel Port Timing - Write; Motorola Non-Multiplexed Address / Data Bus Mode.....66
Figure 32. Parallel Port Timing - Read; Motorola Non-Multiplexed Address / Data Bus Mode. ....66
Figure 33. JTAG Switching Characteristics................................................................................... 67
Figure 34. 160-Ball FBGA Package Drawing.................................................................. .. .......... ..69
Figure 35. 144-Pin LQFP Package Drawing................................................................................. 70
CS61880
DS450PP3 5
LIST OF TABLES
Table 1. Operation Mode Selection...............................................................................................10
Table 2. Mux/Bits Clock Selection.................................................................................................11
Table 3. Jitter Attenuation Selection..............................................................................................12
Table 4. Cable Impedance Selection ..................................................................................... .......15
Table 5. Bipolar Mode Translations...............................................................................................16
Table 6. G.772 Address Selection .. ...............................................................................................22
Table 7. Jitter Attenuator Configurations .......................................................................................28
Table 8. Operational Summary .....................................................................................................29
Table 9. Host Control Signal Descriptions.....................................................................................32
Table 10. Host Mode Register Set................................................................................................34
Table 11. Jitter Attenuator Position Selection ...............................................................................37
Table 12. Transmitter Pulse Shape Selection...............................................................................38
Table 13. JTAG Instructions..........................................................................................................46
Table 14. Boundary Scan Register ...............................................................................................47
Table 15. Trans fo r mer Sp e cifications.. .......... ......... ................. ......... .......... ................ .......... .........52
Table 16. 144-Pin Package Dimensions .......................................................................................70
CS61880
6 DS450PP3
1. PIN OUT - 144-PIN LQFP PACKAGE
TNEG7/UBS7
RCLK7
RPOS7/RDATA7
RNEG7/BPV7
LOS7
RTIP7
RRING7
TV+7
TTIP7
TRING7
TGND7
RRING6
RTIP6
TGND6
TRING6
TTIP6
144
143
142
140
139
138
137
136
135
134
133
132
131
130
129
CS61880
144-Pin
LQFP
(Top View)
TPOS7/TDATA7
TCLK7
LOS6
RNEG6/BPV6
RPOS6/RDATA6
RCLK6
TNEG6/UBS6
TPOS6/TDATA6
TCLK6
MCLK
MODE
A4
A3
A2
A1
A0
VCCIO
GNDIO
RV0+
RGND0
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
TCLK1
TPOS1/TDATA1
TNEG1/UBS1
RCLK1
RPOS1/RDATA1
RNEG1/BPV1
LOS1
TCLK0
141
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
CS61880
TV+6
RTIP5
RRING5
TV+5
TTIP5
TRING5
TGND5
RRING4
RTIP4
TGND4
TRING4
TTIP4
TV+4
CLKE
TXOE
LOS4
RNEG4/BPV4
RPOS4/RDATA4
RCLK4
TNEG4/UBS4
120
118
116
115
114
113
112
111
110
127
126
125
124
123
122
121
119
128
117
109
108
107
106
105
104
103
102
101
100
TPOS4/TDATA4
TCLK4
LOS5
RNEG5/BPV5
RPOS5/RDATA5
RCLK5
TNEG5/UBS5
TPOS5/TDATA5
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
TCLK5
TDI
TDO
TCK
TMS
TRST
REF
CBLSEL
VCCIO
GNDIO
RV1+
RGND1
INTL/MOT/CODEN
CS/JASEL
ALE/AS/SCLK
RD/RW
WR/DS/SDI
RDY/ACK/SDO
INT
TCLK2
TPOS2/TDATA2
TNEG2/UBS2
RCLK2
RPOS2/RDATA2
RNEG2/BPV2
LOS2
TCLK3
TPOS3/TDATA3
373839
RCLK0
TNEG0/USB0
TPOS0/TDATA0
4142434445
40
LOS0
RNEG0/BPV0
RPOS0/RDATA0
MUX/BITSEN0
47
46
484950
51525354555657
TV+0
TTIP0
RTIP0
TGND0
TRING0
RRING0
TGND1
TV+1
TTIP1
TRING1
RRING1
585960616263646566676869707172
TV+2
TTIP2
RTIP1
RTIP2
TGND2
TRING2
RRING2
TGND3
TV+3
TTIP3
TRING3
LOS3
RTIP3
RRING3
RNEG3/RBPV3
RPOS3/RDATA3
RCLK3
TNEG3/UBS3
Figure 1. CS61880 144-Pin LQFP Package Pin Outs
DS450PP3 7
2. PIN OUT - 160-BALL FBGA PACKAGE
CS61880
1234567891011121314
A
B
C
D
E
F
G
H
K
LOS
A3
A0
RPOS
7
TPOS
7
RPOS
6
TPOS
6
MODE
6
LOOP
RCLK
7
TCLK
7
RCLK
6
TCLK
6
MCLK
A2
VCCIO
0
A
7
B
7
C
6
D
6
E
A1
F
G
RCLK
4
TCLK
4
RCLK
5
TCLK
5
TXOE
TCK
VCCIO
RPOS
4
TPOS
4
RPOS
5
TPOS
5
CLKE
TDO
CBLSEL
RNEG
4
TNEG
4
RNEG
5
TNEG
5
LOS
5
TDI
TRST
TVCC
4
TVCC
4
TVCC
5
TVCC
5
LOS
4
TMS
GNDIO
TRING
4
TTIP
4
TRING
5
TTIP
5
TGND
4
TGND
4
TGND
5
TGND
5
RTIP
RRING
RTIP
RRING
RTIP
4
4
5
5
7
RRING
7
RTIP
6
RRING
6
CS61880
TGND
7
TGND
7
TGND
6
TGND
6
TRING
7
TTIP
7
TRING
6
TTIP
6
TVCC
7
TVCC
7
TVCC
6
TVCC
6
LOS
7
A4
GNDIO
RNEG
TNEG
RNEG
TNEG
160 FBGA
RV1+
WR
J
RDY
REF
RD
INT
INTL
ALE
LOS
RGND
1
CS
LOS
2
3
(Bottom View)
RGND
LOOP
0
3
LOS
0
LOOP
LOOP
LOS
LOOP
1
LOOP
4
MUX
1
RV0+
2
LOOP
5
LOOP
H
J
6
K
7
TPOS
2
RPOS
2
TPOS
3
RPOS
3
TNEG
2
RNEG
2
TNEG
3
RNEG
3
TVCC
2
TVCC
2
TVCC
3
TVCC
3
TTIP
2
TRING
2
3
TRING
3
2
2
TTIP
3
3
TGND
TGND
TGND
TGND
RRING
2
2
RRING
3
3
2
RTIP
2
3
RTIP
3
RRING
1
RTIP
1
RRING
0
RTIP
0
TGND
1
TGND
1
TGND
0
TGND
0
TTIP
1
TRING
1
TTIP
0
TRING
0
TVCC
1
TVCC
1
TVCC
0
TVCC
0
TNEG
1
RNEG
1
TNEG
0
RNEG
0
TPOS
1
RPOS
1
TPOS
0
RPOS
0
TCLK
1
RCLK
1
TCLK
0
RCLK
0
L
M
N
P
M
TCLK
L
RCLK
TCLK
N
RCLK
P
1234567891011121314
Figure 2. CS61880 160-Bal l FB GA Package Pin Outs
8 DS450PP3
3. PIN DESCRIPTIONS
3.1 Power Supplies
SYMBOL LQFP FBGA TYPE DESCRIPTION
CS61880
17
VCCIO
GNDIO 18
RV0+
RV1+
RGND0
RGND1
TV+0 44 N4, P4 Power Supply, Transmit Driver 0
TGND0 47 N6, P6 Ground, Transmit Driver 0
TV+1 53 L4, M4 Pow er S upp ly, Transmit Driver 1
TGND1 50 L6, M6 Ground, Transmit Driver 1
TV+2 56 L11
TGND2 59 L9, M9 Ground, Transmit Driver 2
TV+3 65 N11
92
91
19
90
20
89
G1
G14
G4
G11
H1
H14
H4
H11
M11
P11
Power Supply, Digital Interface: Power supply for digital
interface pins; typically 3.3 V
Ground, Digital Interface:
Power supply ground for the digital interface; typically 0 V
Power Supp ly, Core Circuitry: Power supply for all sub-cir-
cuits except the transmit driver; typically +3.3 V
Ground , Core Circuitry:
Ground for sub-circuits except the TX driver; typically 0 V
Power supply for transmit driver 0; typically +3.3 V
Power supply ground for transmit driver 0; typically 0 V
Power Supply, Transmit Driver 2
Power Supply, Transmit Driver 3
TGND3 62 N9, P9 Ground, Transmit Driver 3
TV+4 116 A11
B11
TGND4 119 A9, B9 G rou nd , Transmit Driver 4
TV+5 125 C11
D11
TGND5 122 C9,
D9
TV+6 128 C4,
D4
TGND6 131 C6,
D6
TV+7 137 A4, B4 Pow er S upply, Transmit Driver 7
TGND7 134 A6, B6 Ground, Transmit Driver 7
DS450PP3 9
Power Supply, Transmit Driver 4
Power Supply, Transmit Driver 5
Ground, Transmit Driver 5
Power Supply, Transmit Driver 6
Ground, Transmit Driver 6
3.2 Control
SYMBOL LQFP FBGA TYPE DESCRIPTION
MCLK 10 E1 I
MODE 11 E2 I
CS61880
Master Clock Input
This pin is a free running reference clock that sh ould be
2.048 MHz. This timing reference is used as follows:
- Timing reference for the clock recovery and jitter attenuation circuitry.
- RCLK reference during Loss of Signal (LOS) conditions
- Transmit clock reference during Transmit all Ones (TAOS)
condition
- Wait state timing for microprocessor interface
- When this pin is held “High”, the PLL clock recovery circuit is disabled. In this mode, the CS61880 rece ivers
function as simple data slicers.
- When this pin is held “Low”, the receiver paths are powered down and the output pins RCLK, RPO S, and RNEG
are High-Z.
Mode Select
This pin is used to select whether the CS61880 operates in
Serial host, Parallel host or Hardware mode.
Host Mode
serial or a parallel microprocessor interface (Ref er to HOST
MODE (See Section 13 on page 32).
Hardware Mode
and the device control/status are provided through the pi ns
on the device.
- The CS61880 is controlled through either a
- The microprocessor interface is disabled
Table 1. Operation Mode Selection
Pin State OPERATING Mode
LOW Hardware Mode
HIGH Parallel Host Mode
VCCIO/2 Serial Host Mode
NOTE: For serial host mode connect this pin to a resistor
divider consi sting of two 10 kΩ res istors between
VCCIO and GNDIO.
10 DS450PP3
SYMBOL LQFP FBGA TYPE DESCRIPTION
Multiplexed Interface/Bits Clock Select
MUX/BITSEN0 43 K2 I
Host Mode
face for multiplexed or non-multiplexed operation.
Hardware mode
a G.703 BITS Clock recovery channel (Refer to BUILDING
INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE
(See Section 8 on page 23). Channel 1 through 7 are not
affected by this pin during hardware mode. During host
mode the G.703 BITS Clock recovery function is enabled by
the Bits Clock Enable Register (1Eh) (See Section 14.31
on page 40).
Pin St a t e Parallel Host Mode Hardware Mode
NOTE: The MUX pin only controls the BITS Clock function in
-This pin configures the microproces sor inter-
- This pin is used to enable channel 0 as
Table 2. Mux/Bits Clock Selection
HIGH multiplexed BITS Clock ON
LOW non multiplexed BITS Clock OFF
Hardware Mode
CS61880
INT
RDY/ACK
82 K13 O
/SDO 83 K14 O
Interrupt Output
This active low output signals the host processor when one
of the CS61880’s internal status register bits has changed
state. When the status register is read, the interrupt is
cleared. The various status changes that would force INT
active are maskable via internal interrupt enable registers.
NOTE: This pin is an open drain output and requires a 10 kΩ
pull-up resistor.
Ready/Data Transfer Acknowledge/Serial Data Output
Intel Parallel Host Mode
access, RDY is asserted “Low” to acknowledge that the device has been accessed. An asserted “High” acknowledges
that data has been written or read. Upon completion of the
bus cycle, this pin High-Z.
Motorola P arallel Host Mo de
operation this pin, “ACK
data on the bus is valid. An asserted “Low” on this pin during a write operation acknowledges that a data transfer to
the addressed register has been ac cepted. Upon completion of the bus cycle, this pin High-Z.
NOTE: Wait state generation via RDY/ACK
RZ mode (No Clock Recovery).
Serial Host Mode
configured for serial bus operation, “SDO” is used as a serial data output. This pin is forced into a high impedance
state during a serial write access. The CLKE pin controls
whether SDO is valid on the rising or falling edge of SC LK.
Upon completion of the bus cycle, this pin High-Z.
Hardware Mode
open.
- When the microprocessor interface is
- This pin is not used and should be left
- During a read or write register
- During a data bus read
”, is asserted “High” to indicate that
is disabled in
DS450PP3 11
SYMBOL LQFP FBGA TYPE DESCRIPTION
Write Enable/Data Strobe/Serial Data
WR/DS/SDI 84 J14 I
RD
/RW 85 J13 I
ALE/AS
/SCLK 86 J12 I
Intel Parallel Host Mode
a write enable.
Motorola Parallel Host Mode
a data strobe input.
Serial Host Mode
data input.
Hardware Mode
nected to ground.
Read Enable/Read/Write
Intel Parallel Host Mode
read enable.
Motorola P arallel Host Mo de
as the read/write input signal.
Hardware Mode
nected to ground.
Address Latch Enable/Add ress Strobe/Serial Clock
Intel Parallel Host Mode
Address Latch Enable when co nfigured for multiplexed address/data operation.
Motorola Para llel H ost Mo de
the active “low” address strobe when configured for multiplexed address/data operation.
Serial Host Mode
used for data I/O on SDI and SDO.
Hardware Mode
nected to ground.
- This pin, “SDI”, functions as the serial
- This pin is not used and should be con-
- This pin is not used and should be con-
- This pin, “SCLK”, is the serial clock
- This pin is not used and should be con-
- This pin, “WR”, functions as
- This pin, “DS“, functions as
- This pi n, “R D”, func tions as a
- This pin, “R/W”, functions
- This pin, “ALE”, functions as the
- This pin, “AS”, fun ctio ns as
CS61880
/JASEL 87 J11 I
CS
Chip Select Input/Jitter Attenuator Select
Host Mode
cesses to the microprocessor interface in either serial or
parallel mode.
Hardware Mode
Attenuator.
- This active low input is used to enable ac-
- This pin controls the positio n of the Jitter
Table 3. Jitter Attenuation Selection
Pin State Jitter Attenuation Position
LOW Transmit Path
HIGH Receive Path
OPEN Disabled
12 DS450PP3
SYMBOL LQFP FBGA TYPE DESCRIPTION
Intel/Motorola/Coder Mode Select Input
INTL/MOT/CODEN 88 H12 I
TXOE 114 E14 I
Parallel Host Mode
cessor interface is configured for operation with Motorola
processors. When this pin is “High” the microprocessor interface is configured for operation with Intel processors.
Hardware Mode
polar operation, this pin, CODEN
encoding/decoding function. Whe n CODEN
encoders/decoders are enabled. Whe n CODEN
AMI encoding/decoding is ac tivated. This is done for all
eight channels.
Transmitter Output Enable
Host mode
dividual drivers can be set to a high impeda nce state via
the Ou tput Disable Register (12h) (See S ection 14.19 on
page 38).
Hardware Mode
TX drivers are forced into a high impedance state. All other
inter nal cir cuitr y rem ain s acti ve .
- Operates the same as in hardware mode. In-
- When this pin is “Low” the micropro-
- When the CS61880 is configured for uni-
- When TXOE pin is asserted Lo w, all the
CS61880
, configures the line
is low, HDB3
is high,
CLKE 115 E13 I
Clock E dge S elec t
In clock/ data recover y mode , setting CL KE “high” will cause
RPOS/RNEG to be valid on the falling edge of RCLK and
SDO to be valid on the rising edge of SCLK. When CLKE is
set “low”, RPOS/RNEG is v alid on the rising edge of RCLK,
and SDO is valid on the falling edge of SC LK. When the
part is operated in data recovery mode, the RPOS/RNEG
output polarity is active “high” when CLKE is set “high” and
active “low” when CLKE is set “low”.
DS450PP3 13
3.3 Address Inputs/Loopbacks
SYMBOL LQFP FBGA TYPE DESCRIPTION
A4 12 F4 I
A3
A2
A1
A0
13
14
15
16
F3
F2
F1
G3
CS61880
Address Selector Input
Parallel Host Mode
mode operation, this pin function as the address 4 input for
the parallel interface.
Hardware Mode
Non-Intr usive Mo nitoring /Addre ss Selecto r Inputs
Parallel Host Mode
mode operation, these pins funct ion as address A[3:0] inputs for the parallel interface.
Hardware Mode
tion during non-intrusive monitoring. In non-intrus ive
I
monitoring mode, receiver 0’s input is internally connected
to the transmit or receive ports on one of the other 7 chan-
I
nels. The recovered clock and data from the sele cted port
are output on RPOS0/RNEG0 and RCLK0. Additionally, the
I
data from the selected port can be output on
TTIP0/TRING0 by activating the remote loopback function
I
for channel 0 (Refer t o Performan ce Monitor Register
(0Bh) (See Section 14.12 on page 36).
- During non-multiplexed parallel host
- The A4 pin must be tied low at all times.
- During non-multiplexed parallel host
- The A[3:0] pins are used for port selec-
LOOP0/D0
LOOP1/D1
LOOP2/D2
LOOP3/D3
LOOP4/D4
LOOP5/D5
LOOP6/D6
LOOP7/D7
21
22
23
24
25
26
27
28
G2
H3
H2
J4
J3
J2
J1
K1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Loopback Mode Selecto r/Parallel Data Input/Output
Parallel Host Mode
terface mode, these pins function as the bi-directional 8-bit
data port. When operating in multiplexed microproc essor interface mode, these pins function as the address and data
inputs/outputs.
Hardware Mode
- No Loopback - The CS61880 is in a norm al operating
state when LOOP is left open (unconnected) or tied to
VCCIO/2.
- Local Loopback - When LOOP is tied High, data transmitted on TTIP and TRING is loo ped back into the analog
input of the corresponding channel’s receiver and output on
RPOS and RNEG. Input Data present on RTIP and RRING
is ignored.
- Remote Loopback - When LOOP is tied Low the recovered clock and data received on RTIP and RRING is looped
back for transmission on TTIP and TRI NG. Data on TPOS
and TNEG is ignored.
- In non-multiplexed microprocessor in-
14 DS450PP3
3.4 Cable Select
SYMBOL LQFP FBGA TYPE DESCRIPTION
CBLSEL 93 G13 I
CS61880
Cable Impedan ce Sele ct
Host Mode
normal operation.
Hardware Mode
pulse shape and set the line imped ance for all eight receivers and transmitters. This pin also selects whether or not all
eight receivers use an internal or external line matching
network (Refer to the Table 4 below for proper settings).
CBLSEL Transmitters Recei vers
No Connect 120 Ω Internal 120 Ω Internal or External
HIGH 75 Ω Internal 75 Ω Internal
LOW 75 Ω Internal 75 Ω External
- The input voltage to this pin does not effect
- This pin is used to select the transmitted
Table 4. Cable Impedance Selection
3.5
NOTE: Refer to Figure 16 on page 50 and Figure 17 on
page 51 for a ppropriate extern al line matchin g com-
ponents. All transmitters use intern al matching networks.
Status
SYMBOL LQFP FBGA TYPE DESCRIPTION
Loss of Signal Output
LOS0
LOS1
LOS2
LOS3
LOS4
LOS5
LOS6
LOS7
42
35
75
68
113
106
3
140
K4
K3
K12
K11
E11
E12
E3
E4
O
O
The LOS output pins can be c onfigured to indi cate a loss of
O
signal (LOS) state that is compliant to either ITU G.775 or
O
ETSI 300 233. These pins are ass erted “High” to indicate
O
LOS. The LOS output returns low wh en an input signal is
O
present for the time period dictated by the associated speci-
O
fication (Refer to Loss-of-Signal (LOS) (See Section 10.5
O
on page 27)).
DS450PP3 15
3.6 Digital Rx/Tx Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION
TCLK0 36 N1 I
CS61880
Transmit Clock Input Port 0
- When TCLK is active, the TPOS an d TNEG pins function
as NRZ inputs that are sampled on the falling edge of
TCLK.
- If MCLK is active, TAOS will be generated when TCLK is
held High for 16 MCLK cycles.
NOTE: MCLK is used as the timing reference during TAOS
and mus t hav e th e ap pr o pr iat e sta b ilit y.
- If TCLK is held High in the absence of MCLK, the T POS
and TNEG inputs function as RZ inputs. In this mode, the
transmit pulse width is set by the pulse-width of the signal
input on TPOS and TNEG. To enter this mode, TCLK m ust
be held high for at least 12 µs.
- If TCLK is held Low, the output drivers enter a low-power,
high impedance state.
Transmit Positive Pulse/Transmit Data Input Port 0
Transmit Negative Pulse/Unipolar-Bipolar Select Port 0
The function of the TPOS/TDATA and TNEG/UBS inputs
are determined by whether Unipolar, Bipolar or RZ input
mode has been selected.
Bipolar Mode
TNEG are sampled on the falling edge of TCLK and transmitted onto the line at TTIP and TR ING respectively. A
“High” input on TPOS results in transmission of a positive
pulse; a “High” input on TNEG results in a transmission of a
negative pulse. The translation of TPOS /TNEG inputs to
TTIP/TRING outputs is as follows:
- In this mode, NRZ data on TPOS and
TPOS0/TDATA0
TNEG0/UBS
16 DS450PP3
37
38
N2
N3
I
I
Unipolar mode
TNEG/UBS “High” for more than 16 TCLK cycles, when
MCLK is present. The falling edge of TCLK samples a unipolar data steam on TPOS/TDATA.
RZ Mode
absence of MCLK. In this mod e, the duty cycle of the
TPOS and TNEG inputs determine th e pulse width of the
output signal on TTIP and TRING.
Table 5. Bipolar Mode Translations
TPOS TNEG OUTPUT
0 0 Space
1 0 Positive Mark
0 1 Negative Mark
1 1 Space
- Unipolar mode is activated by holding
- To activate RZ mode tie TCLK “High” in the
SYMBOL LQFP FBGA TYPE DESCRIPTION
Receive Clock Output Port 0
- When MCLK is active, this pin outputs the recovered clock
from the signal input on RTIP and RRING. In the event of
LOS, the RCLK output transitions from the rec overed clock
RCLK0 39 P1 O
RPOS0/RDATA0
RNEG0/BPV0
40
41
P2
P3
to MCLK.
- If MCLK is held “High”, the clock recovery circuitry is disabled and the RCLK output is driven by the XO R of RNEG
and RPOS.
- If MCLK is held “Low”, this output is in a high-impedance
state.
Receive Positive Pulse/ Receive Data Output Port 0
Receive Negative Pulse/Bipolar Violation Outpu t Port 0
The function of the RPOS/RDATA and RNEG/BPV outputs
are determined by whether Unipolar, Bipolar, or RZ input
mode has been selected. During LOS , the RPOS/RNEG
outputs will remain active.
NOTE: The RPOS/RNEG ou tputs can be High-Z by hold ing
MCLK Low.
Bipolar Output M ode
O
tion, NRZ Data is recovered from RTIP/RRING and output
on RPOS/RNEG. A high signal on RPOS or RNEG corre-
O
spond to the receipt of a positive or negative pulse on
RTIP/RRING respectively. The RPOS/RNEG outputs are
valid on the falling or rising edge of RCLK as configured by
CLKE.
Unipolar Output Mode
the recovered data is output on RDATA. The decoder signals bipolar violations are output on the RNEG/BPV pin.
RZ Output Mode
output RZ data recovered by slicing the signal present on
RTIP/RRING. A positive pulse on RTIP with respect to
RRING generates a logic 1 on RPOS; a positive pulse on
RRING with respect to RTIP generates a logic 1 on RNEG.
The polarity of the output on RPOS/RNE G is selectable using the CLKE pin. In this mode, external circuitry is used to
recover clock from the received signal.
- When configured for Bipolar opera-
- When unipolar mode i s a ctivated,
- In this mode, the RPOS/RNEG pins
CS61880
TCLK1 29 L1 I Transmit Clock Input Port 1
TPOS1/TDATA1 30 L2 I Transmit Positive Pulse/Transmit Data Input Port 1
TNEG1/UBS1 31 L3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 1
RCLK1 32 M1 O Receive Clock Output Port 1
RPOS1/RDATA1 33 M2 O Receive Positive Pulse/ Receive Data Output Port 1
RNEG1/BPV1 34 M3 O Receive Negative Pulse/Bipolar Violation Output Port 1
TCLK2 81 L14 I Transmit Clock Input Port 2
TPOS2/TDATA2 80 L13 I Transmit Positive Pulse/Transmit Data Input Port 2
TNEG2/UBS2 79 L12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 2
DS450PP3 17
CS61880
SYMBOL LQFP FBGA TYPE DESCRIPTION
RCLK2 78 M14 O Receive Clock Output Port 2
RPOS2/RDATA2 77 M13 O Rec eive Positive Pulse/ Receive Data Output Port 2
RNEG2/BPV2 76 M12 O Receive Negative Pulse/Bipolar Violation Output Po rt 2
TCLK3 74 N14 I Transmit Clock Input Port 3
TPOS3/TDATA3 73 N13 I Transmit Positive Pulse/Transmit Data Input Port 3
TNEG3/UBS3 72 N12 I Transmit Negative Pulse/Unipolar-Bipolar Select Po rt 3
RCLK3 71 P14 O Receive Clock Output Port 3
RPOS3/RDATA3 70 P13 O Receive Positive Pulse/ Receive Data Output Port 3
RNEG3/BPV3 69 P12 O Receive Negative Pulse/Bipolar Violation Output Port 3
TCLK4 107 B14 I Transmit Clock Input Port 4
TPOS4/TDATA4 108 B13 I Transmit Positive Pulse/Transmit Data Input Port 4
TNEG4/UBS4 109 B12 I Transmit Negative Pulse/Unipolar-Bipolar Sele ct Port 4
RCLK4 110 A14 O Receive Clock Output Port 4
RPOS4/RDATA4 111 A13 O Receive Positive Pulse/ Recei ve Data Output Port 4
RNEG4/BPV4 112 A12 O Receive Negative P ulse/Bipolar Violation Output Port 4
TCLK5 100 D14 I Transmit Clock Input Port 5
TPOS5/TDATA5 101 D13 I Transmit Positive Pulse/Transmit Data Input Port 5
TNEG5/UBS5 102 D12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 5
RCLK5 103 C14 O Receive Clock Output Port 5
RPOS5/RDATA5 104 C13 O Receive Positive P ulse/ Receive Data Output Port 5
RNEG5/BPV5 105 C12 O Receive Negative Pulse/Bipolar Violation Output Po rt 5
TCLK6 9 D1 I Transmit Clock Input Port 6
TPOS6/TDATA6 8 D2 I Transmit Positive Pulse/Transmit Data Input Port 6
TNEG6/UBS6 7 D3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 6
RCLK6 6 C1 O Receive Clock Output Port 6
RPOS6/RDATA6 5 C2 O Rec eive Positive Pulse/ Receive Data Output Port 6
RNEG6/BPV6 4 C3 O Receive Negative Pulse/ Bipolar Violation Output Port 6
TCLK7 2 B1 I Transmit Clock Input Port 7
TPOS7/TDATA7 1 B2 I Transmit Positive Pulse/Transmit Data Input Port 7
TNEG7/UBS7 144 B3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 7
18 DS450PP3
CS61880
SYMBOL LQFP FBGA TYPE DESCRIPTION
RCLK7 143 A1 O Receive Clock Output Port 7
RPOS7/RDATA7 142 A2 O Receive Po sitive Pulse/ Receive Data Output Port 7
RNEG7/BPV7 141 A3 O Receive Negative Pulse/Bipolar Violation Outpu t Port 7
3.7 Analog RX/TX Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION
Transmit Tip Output Port 0
Transmit Ring Output Port 0
These pins are the di fferential outputs of the transmi t driver.
The driver internally matches impedances f or E1 75 Ω or
E1 120 Ω lines requirin g only a 1:1.15 transformer. The
TTIP0
TRING0
45
46
N5
P5
CBLSEL pin is used to select the appropriate line ma tching
O
impedance only in “Hardware” mode . In host mode, the appropriate line matching impedan ce is selected by the Line
O
Length Data Register (11h) (See Section 14.18 on
page 38).
NOTE: TTIP and TRING are forced to a high impedance state
when the TCLK or the TXOE pin is forced “Low”.
Receive Tip Input Port 0
Receive Ring Input Port 0
These pins are the differential line inputs to the receiver.
The receiver uses either Internal Line Impedance or E xternal Line Impedance modes t o match the line impedances
RTIP0
RRING0
TTIP1 52 L5 O Transmit Tip Output Port 1
48
49
P7
N7
for E1 75Ω or E1 120Ω modes.
I
Internal Li ne I mped ance M ode
same external resistors to match the line impedanc e (Refer
I
to Figure 16 on page 50).
External Line Impedance Mode
ent external resistors to match the line impedance (Refer to
Figure 17 on page 51).
- In host mode, the appropriate line impedan ce is selected
by the Line Le ngth Data Reg ister (11h) (See Section
14.18 on page 38).
- In hardware mode, the CBLSEL pin selects the appropriate line impedance. (Refer to Table 4 on page 15 for proper
line impedance settings).
NOTE: Data and clock recovered from the signal input on
these pins are output via RCLK, RPOS, and RNEG.
- The receiver uses the
- The receiver uses differ-
TRING1 51 M5 O Transmit Ring Output Po rt 1
RTIP1 55 M7 I Receive Tip Input Port 1
RRING1 54 L7 I Receive Ring Input Port 1
TTIP2 57 L10 O Transmit Tip Output Port 2
DS450PP3 19
SYMBOL LQFP FBGA TYPE DESCRIPTION
TRING2 58 M10 O Transmit Ring Output Port 2
RTIP2 60 M8 I Receive Tip Input Port 2
RRING2 61 L8 I Receive Ring Input Port 2
TTIP3 64 N10 O Transmit Tip Output Port 3
TRING3 63 P10 O Transmit Ring Output Port 3
RTIP3 67 P8 I Receive Tip Input Port 3
RRING3 66 N8 I Receive Ring Input Port 3
TTIP4 117 B10 O Transmit Tip Output Port 4
TRING4 118 A10 O Transmit Ring Output Port 4
RTIP4 120 A8 I Receive Tip Input Port 4
RRING4 121 B8 I Receive Ring Input Port 4
TTIP5 124 D10 O Transmit Tip Output Port 5
CS61880
TRING5 123 C10 O Transmit Ring Output Port 5
RTIP5 127 C8 I Receive Tip Input Port 5
RRING5 126 D8 I Receive Ring Input Port 5
TTIP6 129 D5 O Transmit Tip Output Port 6
TRING6 130 C5 O Transmit Ring Output Port 6
RTIP6 132 C7 I Receive Tip Input Port 6
RRING6 133 D7 I Receive Ring Input Port 6
TTIP7 136 B5 O Transmit Tip Output Port 7
TRING7 135 A5 O Transmit Ring Output Port 7
RTIP7 139 A7 I Receive Tip Input Port 7
RRING7 138 B7 I Receive Ring Input Port 7
20 DS450PP3
3.8 JTAG Test Interface
SYMBOL LQFP FBGA TYPE DESCRIPTION
TRST
TMS 96 F11 I
TCK 97 F14 I
TDO 98 F13 O
95 G12 I
CS61880
JTAG Reset
This active Low input resets the JTAG controller. This input
is pulled up internally and may be left as a NC when not
used.
JTAG Test Mode Select Input
This input enables the JTAG serial port when active High.
This input is sampled on the rising edge of TCK . This input
is pulled up internally and may be left as a NC when not
used.
JTAG Test Clock
Data on TDI is valid on the rising edge of TCK. Data on
TDO is valid on the falling edge of T CK. When TCK is
stopped high or low, the contents of all JTAG registers remain unchanged. Tie pin low through a 10 kΩ resistor when
not used.
JTAG Test Data Output
JTAG test data is shifted out of the device on this pin. Data
is output on the fallin g edge of TCK . Leave as NC w hen not
used.
TDI 99 F12 I
3.9 Miscellaneous
SYMBOL LQFP FBGA TYPE DESCRIPTION
REF 94 H13 I Reference Input
JTAG Test Data Input
JTAG test data is shifted into the device using this pin. Th e
pin is sampled on the rising edge of TCK . TDI is pulled up
internally and may be left as a NC when not used.
This pin must be tied to ground through 13. 3 kΩ 1% resistor. This pin is used to set the internal current level.
DS450PP3 21
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